Self-correcting clock recovery circuit with improved jitter performance

In the letter we present a new clock recovery circuit with self-correction of the position of the retiming clock, which shows the reduction of the output jitter by deleting the phase difference of ? radians in the output of the phase detector existing in Hogge's scheme.     

Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection

A fully integrated clock and data recovery circuit (CDR) using a multiplying shifted-averaging delay locked loop and a rate-detection circuit is presented. It can achieve wide range and low jitter operation. A duty-cycle-insensitive phase detector is also proposed to mitigate the dependency on clock duty cycle variations. The experimental prototype has been fabricated in a 0.25-/spl mu/m 1P5M CMOS technology and occupies an active area of 2.89 mm/sup 2/. The measured CDR could operate from 125 Mb/s to 2.0 Gb/s with a bit error rate better than 10/sup -12/ from a 2.5-V supply. Over the entire operating frequency range, the maximum rms jitter of the recovered clock is less than 4 ps.     

A low power DLL based clock and data recovery circuit with wide range anti-harmonic lock

This paper presents a wide frequency range CDR circuit for second generation AiPi+ intra-panel interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with conventional AiPi+. The DLL-based CDR architecture is adopted to generate multi-phase clocks. We propose a simple scheme for a frequency detector (FD) to overcome the limited frequency range and false lock problem of a conventional delay-locked loop (DLL) to reduce the complexity. In addition, a duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatches between rising and falling time of delay cells in the VCDL. Also, the proposed simple DLL architecture comprised of frequency and phase detectors has better process-portability. The proposed CDR is implemented in 0.18 μm technology and the active die area is 660 × 250 μm. The implemented DLL covers a frequency range from 62 to 128 MHz, which is limited only by the characteristics of the delay cell. The peak-to-peak jitter is less than 13 ps when the input frequency is 128 MHz, and the power consumption of the CDR except the input buffer, equalizer, and de-serializer is 5.94 mW from the supply voltage of 1.8 V.     

An analog PLL-based clock and data recovery circuit with high inputjitter tolerance

A clock and data recovery circuit for a T1 network is described. A fully integrated phase-locked loop (PLL) extracts the carrier signal embedded in the data. Two trimming DACs simultaneously bring the VCO center frequency and the PLL closed-loop bandwidth to their specified values. A triple sampler captures the jittering data and aligns them with the recovered clock. The input jitter of this circuit is three times more than previously reported PLL-based circuits     

高速时钟与数据恢复电路技术研究

本文根据数据恢复时,本地时钟与输入数据之间的相位关系及其实现方式的不同,将高速时钟与数据恢复(CDR,Clock and Data Recovery)电路技术分为三类,也即前馈相位跟踪型,反馈相位跟踪型,以及盲过采样型。进而又分别对每一类型进行了细分并分别进行了深入的剖析和比较。最后又给出了不同应用环境下,CDR技术的选择策略,并指出了CDR技术的发展趋势。本文通过对高速CDR技术详尽而又深刻的分析比较,勾勒出了一个高速CDR技术的关系及发展演化图,使读者能够对现存的高速CDR技术及其发展趋势有一个前面而又清晰的认识。     

基于FPGA的高速时钟数据恢复电路的实现

介绍了一种利用输出时钟在具有不同相位的时钟信号之间进行切换实现高速时钟恢复电路的方法。利用Altera公司Quartus软件提供的修改逻辑单元和逻辑块锁定及插入buffer的方法,消除了时钟切换产生的毛刺,弥补了不同相位时钟由于不同的传输延迟而造成的相位偏移。设计的电路实现了数字光端机要求的204．8MHz的工作频率。同时,分析了决定该电路工作频率的主要因素,通过仿真验证使用EP3C10El44C7芯片最高工作频率可以达到400MHz。     

A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit

A 155.52 Mbps-3.125 Gbps continuous-rate clock and data recovery (CDR) circuit using the full-rate bang-bang phase detector is presented. A frequency detector is proposed to eliminate the harmonic locking problem even with a wide range of data rates and its theoretical analysis is also discussed. A quadrature divider is also presented to generate the clocks with accurate quadrature phases. This CDR circuit has been realized in a 0.18-/spl mu/m CMOS process and its die area is 1.1/spl times/0.8 mm/sup 2/. It consumes 95 mW at the highest bit rate of 3.125 Gbps. It can recover the NRZ data of a 2/sup 31/-1 PRBS with the bit rate ranging from 155.52 Mbps to 3.125Gbps for the incremental frequency acquisition and the NRZ data of a 2/sup 7/-1 PRBS for the decremental frequency acquisition. All the measured bit error rates are less than 10/sup -12/.     

10Gb/s突发模式时钟数据恢复电路设计

突发模式的时钟数据恢复是10G EPON系统的关键技术之一。本文介绍了一种基于XNOR/XOR门的振荡器,分析了其工作原理与性能,以此为基础设计了半速率突发时钟恢复电路。设计采用SMIC 0.13?m CMOS工艺进行了流片验证,芯片面积为675?m ? 625?m。测试结果表明,该电路可以即时的实现10Gbit/s的突发数据恢复,恢复出的时钟数据符合IEEE 802.3av标准,锁定时间小于5bit。     

一种快速同步的时钟数据恢复电路的设计实现

时钟数据恢复(CDR)电路是通信传输设备中的重要部分,对于突发式的接收,基于锁相环的传统的CDR往往不能满足其快速同步的要求.对此,文章采用过采样方式基于FPGA设计实现了一种全数字化的155.52Mb/s下的CDR电路.理论分析、仿真和实验测试结果表明,该CDR电路可以有效地对相位变化实现快速同步,有很大的捕捉范围,且系统较锁相环便于集成.     

A self correcting clock recovery circuit

Conventional approaches to the problem of extracting clock from NRZ data do not automatically hold the clock in the center of the data eye. Other means must be used to keep the clock properly centered in the eye at the decision flip-flop. A new approach to the problem is described. The circuit is both simple and self correcting.     

A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit

A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency of interest. The circuit was designed in a 0.18 μm CMOS process and occupies an active area of 0.2 × 0.32 mm². The CDR exhibits an RMS jitter of ± 1.2 ps and a peak-to-peak jitter of 5 ps. The power dissipation is 97 mW from a 1.8 V supply.     

A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-μm digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 2⁷-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8×0.4 mm²     

时钟提取与抖动衰减数字锁相环设计研究

文章简要介绍了数字锁相环(DPLL)的工作原理,重点提出了用于V5接口芯片中的时钟提取锁相环和抖动衰减锁相环的设计,并对其进行了分析．     

一种误码率为10-12的750MHz半数字结构时钟和数据恢复电路的研究

A semi-digital clock and data recovery (CDR) is presented. In order to lower CDR trace jitter and decrease loop latency, an average-based phase detection algorithm is adopted and realized with a novel circuit. Implemented in a 0.13 μm standard 1P8M CMOS process, our CDR is integrated into a high speed serial and de-serial (SERDES) chip. Measurement results of the chip show that the CDR can trace the phase of the input data well and the RMS jitter of the recovery clock in the observation pin is 122 ps at 75 MHz clock frequency, while the bit error rate of the recovery data is less than 10 × 10^-12.     

A 10-Gb/s CMOS clock and data recovery circuit with a half-ratelinear phase detector

A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-μm CMOS technology in an area of 1.1×0.9 mm², the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28×10^-6, with random data input of length 2²³-1. The power dissipation is 72 mW from a 2.5-V supply     

A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator

This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications. The module aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation. Thus, coupling between voltage-controlled oscillators (VCOs) in adjacent channels can be avoided. The controller for the phase interpolator is realized with analog circuitry to overcome the speed and phase resolution limitations of digital implementations. Fabricated in a 0.11-/spl mu/m CMOS technology the module has a size of 0.25/spl times/1.4 mm/sup 2/. The power consumption is 220 mW from a supply voltage of 1.5 V. The CDR exceeds the SDH/SONET jitter tolerance specifications with a pseudo random bit sequence of length 2/sup 23/-1 and a bit-error rate threshold of 10/sup -12/. The re-timed and demultiplexed data has an rms jitter of 3.2 ps at a data rate of 2.7 Gb/s.     

A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-/spl mu/m standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2/sup 31/-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10/sup -6/ for 2/sup 31/-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.     

A power and area efficient CMOS clock/data recovery circuit forhigh-speed serial interfaces

A power and area efficient CMOS clock/data recovery circuit designed for a wide range of applications in high-speed serial data communications is described. It uses an analog phase-locked loop (PLL) to generate the high-speed clocks with an absolute rms jitter of less than 60 ps and a digital PLL which is designed to minimize chip area and power consumption to recover the clock and data signals from the incoming data stream. Fabricated in a 0.8 μm single-polysilicon, double-metal CMOS process, the digital PLL only consumes 45 mW at 125 Mb/s from a single 5 V supply, while the analog PLL consumes 92 mW. The chip area is 1.7 mm² for the digital PLL and 0.44 mm² for the analog PLL. It can handle an input data rate up to 280 Mb/s     

2.5 Gbit/s clock and data recovery circuit IC using novelduplicated PLL technique

A 2.5 Gbit/s monolithic clock and data recovery integrated circuit (CDR IC) based on a novel duplicated phase-locked loop (PLL) technique has been fabricated using 0.5 μm Si bipolar technology. This CDR IC operates more stably in that it can tolerate greater variations in temperature and supply voltage while continuing to meet the specifications for jitter characteristics stipulated in the ITU-T recommendations