InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operating and standby power application below supply voltage of 0.5 V

An In_0.53Ga_0.47As/InP heterojunction-channel tunneling field-effect transistor (TFET) with enhanced subthreshold swing (S) and on/off current ratio (I_on/I_off) is studied. The proposed TFET achieves remarkable characteristics including S of 16.5 mV/dec, on-state current (I_on) of 421 μA/μm, I_on/I_off of 1.2 × 10¹² by design optimization in doping type of In_0.53Ga_0.47As channel at low gate (V_GS) and drain voltages (V_DS) of 0.5 V. Comparable performances are maintained at V_DS below 0.5 V. Moreover, an extremely fast switching below 100 fs is accomplished by the device. It is confirmed that the proposed TFET has strong potentials for the ultra-low operating power and high-speed electron device.     

Subthreshold swing characteristics of nanowire tunneling FETs with variation in gate coverage and channel diameter

In this study, we demonstrate the simulated subthreshold swing (SS) of silicon nanowire tunneling field-effect transistors (NWTFETs) by varying both the channel diameter from 10 nm to 40 nm and the gate coverage ratio from 30% to 100%. Our simulation work reveals that both a decrease in the channel diameter and an increase in the gate coverage ratio contribute to a reduction in the SS. Additionally, our work shows that the magnitude of the on-current depends linearly on the gate coverage ratio and that the drain current increases with a decrease in the channel diameter. Thus, an NWTFET with a channel diameter of 10 nm and a gate coverage ratio of 100% exhibits superior electrical characteristics over other silicon NWTFETs in that the NWTFET shows a point SS of 22.7 mV/dec, an average SS of 56.3 mV/dec, an on/off current ratio of ∼10¹³, and an on-current of ∼10⁻⁵ A/μm.     

Low-voltage-drive and high output current ZnO thin-film transistors with sputtering SiO2 as gate insulator

Low-voltage-drive ZnO thin-film transistors (TFTs) with room-temperature radio frequency magnetron sputtering SiO₂ as the gate insulator were fabricated successfully on the glass substrate. The ZnO-TFT operates in the enhancement mode with a threshold voltage of 4.2 V, a field effect mobility of 11.2 cm²/V s, an on/off ratio of 3.1 × 10⁶ and a subthreshold swing of 0.61 V/dec. The drain current can reach to 1 mA while the gate voltage is only of 12 V and drain voltage of 8 V. The C–V characteristics of a MOS capacitor with the structure of ITO/SiO₂/ZnO/Al was investigated. The carrier concentration N_D in the ZnO active layer was determined, the calculated N_D is 1.81 × 10¹⁶ cm⁻³, which is the typical value of undoped ZnO film used as the channel layer for ZnO-TFT devices. The experiment results show that SiO₂ film is a promising insulator for the low voltage and high drive capability oxide TFTs.     

Room-temperature fabrication of ultra-thin ZrOx dielectric for high-performance InTiZnO thin-film transistors

In this letter, indium–titanium–zinc–oxide thin-film transistors with zirconium oxide (ZrO_x) gate dielectric were fabricated at room temperature. In the devices, an ultra-thin ZrO_x layer was formed as the gate dielectric by sol–gel process followed by ultraviolet (UV) irradiation. The devices can be operated under a voltage of 4 V. Enhancement mode operations with a high field-effect mobility of 48.9 cm²/V s, a threshold voltage of 1.4 V, a subthreshold swing of 0.2 V/decade, and an on/off current ratio of 10⁶ were realized. Our results demonstrate that UV-irradiated ZrO_x dielectric is a promising gate dielectric candidate for high-performance oxide devices.     

Highly stable hafnium–tin–zinc oxide thin film transistors with stacked bilayer active layers

Hf–Sn–Zn–O (HTZO) thin films were prepared on SiO₂/SiN_x substrates at room temperature by the direct current (DC) magnetron sputtering of Hf-doped Sn–Zn–O targets. The characteristics of films with different amounts of Hf were analyzed. Amorphous HTZO films were obtained by increasing the Hf content, while polycrystalline films have not shown with Hf doping. With the proper Hf concentration in the HTZO films (∼2.0 atomic % Hf/(Hf + Sn + Zn + O)), HTZO films demonstrated good performance as an oxide semiconductor channel material in thin film transistors (TFTs) with a field effect mobility (μ_FE) of 10.9 cm²V⁻¹ s⁻¹, an on/off current ratio of 10⁹, and a subthreshold voltage swing of 0.71 V/decade.     

Memory characteristics and tunneling mechanism of Pt nano-crystals embedded in HfAlOx films for nonvolatile flash memory devices

A non-volatile flash memory device based on metal oxide semiconductor (MOS) capacitor structure has been fabricated using platinum nano-crystals(Pt–NCs) as storage units embedded in HfAlO_x high-k tunneling layers. Its memory characteristics and tunneling mechanism are characterized by capacitance–voltage(C–V) and flat-band voltage-time(ΔV_FB-T) measurements. A 6.5 V flat-band voltage (memory window) corresponding to the stored charge density of 2.29 × 10¹³ cm⁻² and about 88% stored electron reserved after apply ±8 V program or erase voltage for 10⁵ s at high frequency of 1 MHz was demonstrated. Investigation of leakage current–voltage(J–V) indicated that defects-enhanced Pool-Frenkel tunneling plays an important role in the tunneling mechanism for the storage charges. Hence, the Pt–NCs and HfAlO_x based MOS structure has a promising application in non-volatile flash memory devices.     

A low subthreshold swing tunneling field effect transistor for next generation low power CMOS applications

We propose a low subthreshold swing transistor architecture called Negative Capacitance Single Gate Silicon-On-Insulator Tunneling Field Effect Transistor (NC-SG-SOI-TFET) and present an analytical model to characterize its performance. Electrostatic potential distribution and electric field intensity in the channel region are obtained by solving the Poisson equation, and the drain current is calculated using the band-to-band carrier generation rate. An additional layer of ferroelectric oxide is used to obtain the negative capacitance. Effect of ferroelectric oxide is incorporated using one-dimensional Landau formalism. Through two dimensional theoretical analysis, we show that the proposed device has superior performance over traditional TFETs in terms of subthreshold swing and short channel effects. For example, a subthreshold swing of 11.82 mV/decade and operating voltage of 0.65 V for a drain current of 10⁻⁸ A/µm have been obtained. The physics behind the improved performance is discussed based on the presented model. The analytical model would also be instrumental in designing and optimizing such devices avoiding complexities and cost of numerical models.     

Improved performance of InGaZnO thin-film transistors with Ta2O5/Al2O3 stack deposited using pulsed laser deposition

Ta₂O₅/Al₂O₃ stacked thin film was fabricated as the gate dielectric for low-voltage-driven amorphous indium–gallium–zinc-oxide (IGZO) thin film transistors (TFTs). The Ta₂O₅/Al₂O₃ stacked thin film exhibits a combination of the advantages of Al₂O₃ and Ta₂O₅. The IGZO TFT with Ta₂O₅/Al₂O₃ stack exhibits good performance with large saturation mobility of 26.66 cm² V⁻¹ s⁻¹, high on/off current ratio of 8 × 10⁷, and an ultra-small subthreshold swing (SS) of 78 mV/decade. Such small SS value is even comparable with that of submicrometer single-crystalline Si MOSFET.     

Electrical and microscopic characterization of ZnO films on p-SiC substrates

ZnO/p- SiC heterojunctions were fabricated by thermal evaporation from ZnO high quality powder (99.99%) onto 4H and 6H p-SiC polytypes. We find that, despite the low cost technique employed for the deposition of the ZnO film, the devices exhibited breakdown voltages in excess of 100 V, high rectification ratio (forward to reverse current ratio, I_F/I_R) and low leakage current, respectively, 2×10⁵ and 4.5×10⁻⁷ A/cm² (for the 4H p-SiC based device) and 5×10⁴ and 5×10⁻⁷ A/cm² (for the 6H p-SiC based device). The current-voltage (I×V) characteristics were also measured at the nanometer scale by means of conductive atomic force microscopy. A simple Schottky diode model and conductance divided by current versus conductance plots (G/I×G plots) was used to analyze device characteristics. This analysis shows that, when probing at the nanometric scale, fluctuations of the effective barrier height and/or surface states across individual grains or grain boundaries cause deviations from linear G/I×G plots. These fluctuations are smeared out when probing at the macroscale and thus it becomes possible to obtain linear plots and extract diode parameters.     

Fabrication of thin-film transistor based on self-assembled single-walled carbon nanotube network

Thin-film transistor based on controllable electrostatic self-assembled monolayer single-wall carbon nanotubes (SWNTs) network has been fabricated by varying the density of nanotubes on the silicon substrate. The densities of SWNTs network have been investigated as a function of concentration and assembly time. It has been observed that the density of SWNTs network increases from 0.6 µm⁻² to 2.1 µm⁻², as the average on-state current (I_on) increases from 0.5 mA to 1.47 mA. The device has a current on/off ratio (I_on/I_off) of 1.3×10⁴ when I_on reaches to 1.34 mA.     

Microwave irradiation on a-axis oriented Y123/Pr123 two-stacked Josephson junctions device

Two-stacked submicron Josephson junctions devices were fabricated in a-axis oriented YBaCu₃O₇ and PrBa₂Cu₃O₇ (Y123/Pr123) multi layered thin films using focused ion beam milling technique. The transition temperature and critical current density (J_c) of the device are about 83 K and 5 × 10⁵ A/cm² at 20 K, respectively. The device was irradiated with external microwave of 10 GHz and studied at 20 K. The microwave induced voltage steps are observed in I–V characteristics. The supercurrent branch become resistive above a certain microwave power and also the J_c was suppressed as we increased the microwave power. Magnetic field modulation of critical current shows periodicity of about 2000 gauss correspond to the Josephson junctions in the stack.     

Effects of Ti addition on sol-gel derived InO and InZnO thin film transistors

In this study, we have newly developed titanium-indium oxide (TiInO) and titanium-indium zinc oxide (TiInZnO) thin films as the active channel layer in thin film transistors (TFTs) by the sol-gel process. The effects of adding Ti on TiInO and TiInZnO TFTs were investigated. The addition of Ti elements can suppress formation of oxygen vacancies because of the stronger oxidation tendency of Ti relative to that of Zn or In. TiInO and TiInZnO TFTs showed lower off currents and higher on/off current ratios than pure InO and InZnO TFTs. A TiInO TFT doped with 10.31 mol% Ti showed good performance with an on/off current ratio greater than 10⁷, and a field-effect mobility of 1.91 cm² V^?1 S^?1. A TiInZnO TFT doped with 2.92 mol % Ti showed an on/off current ratio greater than 10⁶, and a field-effect mobility of 0.45 cm² V^?1 S^?1.     

The effect of annealing in forming gas on the a-IGZO thin film transistor performance and valence band cut-off of IGZO on SiNx

In this investigation, the carrier concentration gradient between channel and contact region is achieved to improve the Thin film Transistors (TFT) performance by employing annealing at 350 °C in forming gas (N₂ + 5% H₂). The contact region is covered with Mo metal and the channel region is only exposed to forming gas to facilitate the diffusion controlled reaction. The TFT using a-IGZO active layer is fabricated in ambient of Ar:O₂ in ratio 60:40 and the conductivity of the order of 10⁻³ S/cm is measured for as-deposited sample. The electrical conductivity of an annealed sample is of the order of 10² S/cm. The device performance is determined by measuring merit factors of TFT. The saturation mobility of magnitude 18.5 cm²V⁻¹ s⁻¹ has been determined for W/L (20/10) device at 15 V drain bias. The extrapolated field effect mobility for a device with channel width (W) 10 μm is 19.3 cm²V⁻¹ s⁻¹. The on/off current ratio is 10⁹ and threshold voltage is in the range between 2 and 3 V. The role of annealing on the electronic property of a-IGZO is carried out using X-ray photoelectron spectroscopy (XPS). The valance band cut-off has been approximately shifted to higher binding energy by 1 eV relative to as-deposited sample.     

The effect of Ag layer thickness on the properties of WO3/Ag/MoO3 multilayer films as anode in organic light emitting diodes

Transparent conductive WO₃/Ag/MoO₃ (WAM) multilayer electrodes were fabricated by thermal evaporation and the effects of Ag layer thickness on the optoelectronic and structural properties of multilayer electrode as anode in organic light emitting diodes (OLEDs) were investigated using different analytical methods. For Ag layers with thickness varying between 5 and 20 nm, the best WAM performances, high optical transmittance (81.7%, at around 550 nm), and low electrical sheet resistance (9.75 Ω/cm²) were obtained for 15 nm thickness. Also, the WAM structure with 15 nm of Ag layer thickness has a very smooth surface with an RMS roughness of 0.37 nm, which is suitable for use as transparent conductive anode in OLEDs. The current density?voltage?luminance (J?V?L) characteristics measurement shows that the current density of WAM/PEDOT:PSS/TPD/Alq₃/LiF/Al organic diode increases with the increase in thickness of Ag and WO₃/Ag (15 nm)/MoO₃ device exhibits a higher luminance intensity at lower voltage than ITO/PEDOT:PSS/TPD/Alq₃/LiF/Al control device. Furthermore, this device shows the highest power efficiency (0.31 lm/W) and current efficiency (1.2 cd/A) at the current density of 20 mA/cm², which is improved 58% and 41% compared with those of the ITO-based device, respectively. The lifetime of the WO₃/Ag (15 nm)/MoO₃ device was measured to be 50 h at an initial luminance of 50 cd/m², which is five times longer than 10 h for ITO-based device.     

Nanoscale observations of the operational failure for phase-change-type nonvolatile memory devices using Ge2Sb2Te5 chalcogenide thin films

In this study, a phase-change memory device was fabricated and the origin of device failure mode was examined using transmission electron microscopy (TEM) and energy dispersive X-ray spectroscopy (EDS). Ge₂Sb₂Te₅ (GST) was used as the active phase-change material in the memory device and the active pore size was designed to be 0.5 m. After the programming signals of more than 2×10⁶ cycles were repeatedly applied to the device, the high-resistance memory state (reset) could not be rewritten and the cell resistance was fixed at the low-resistance state (set). Based on TEM and EDS studies, Sb excess and Ge deficiency in the device operating region had a strong effect on device reliability, especially under endurance-demanding conditions. An abnormal segregation and oxidation of Ge also was observed in the region between the device operating and inactive peripheral regions. To guarantee an data endurability of more than 1×10¹⁰ cycles of PRAM, it is very important to develop phase-change materials with more stable compositions and to reduce the current required for programming.     

Low power resistive random access memory using interface-engineered dielectric stack of SiOx/a-Si/TiOy with 1D1R-like structure

In this study, we report a resistive random access memory (RRAM) using trilayer SiO_x/a-Si/TiO_y film structure. The low switching energy of <10 pJ, highly uniform current distribution (<13% variation), fast 50-ns speed and stable cycling endurance for 10⁶ cycles are simultaneously achieved in this RRAM device. Such good performance can be ascribed to the use of interface-engineered dielectric stack with 1D1R-like structure. The SiO_x tunnel barrier in contact with top Ni electrode to form diode-like rectifying element not only lowers self-compliance switching currents, but also improves cycling endurance, which is favorable for the application of high-density 3D memory.     

Embedded-Ge source and drain in InGaAs/GaAs dual channel MESFET

We report the first demonstration of n-type III–V metal-semiconductor field-effect transistors (nMESFETs) with IV group material hetero-junction source and drain (S/D) technology. A selective epitaxial growth of germanium (Ge) in the recessed gallium arsenide (GaAs) S/D regions is successfully developed using ultra-high vacuum chemical vapor deposition (UHVCVD) system. The dual channel structure includes an additional 10-nm higher mobility n-In_0.2Ga_0.8As layer on n-GaAs channel and is introduced to further improve the device performance. The n-MESFET, combining embedded-Ge S/D with In_0.2Ga_0.8As/GaAs channel, exhibits good transfer properties with a drain current on/off ratio of approximately 10³. Due to the small barrier height of Ti/In_0.2Ga_0.8As Schottky contact, a lattice-matched wide bandgap In_0.49Ga_0.51P dielectric layer is also integrated into the device architecture to build a higher electron Schottky barrier height (SBH) for gate leakage current reduction. The Ti/In_0.49Ga_0.51P/n-In_0.2Ga_0.8As Schottky diode shows a comparable leakage level to Ti/n-GaAs with 2 × 10^?2 A/cm² at a gate voltage of ?2.0 V.     

Transport properties and device-design of Z-shaped MoS2 nanoribbon planar junctions

Based on MoS₂ nanoribbons, metal-semiconductor-metal planar junction devices were constructed. The electronic and transport properties of the devices were studied by using density function theory (DFT) and nonequilibrium Green's functions (NEGF). It is found that a band gap about 0.4 eV occurs in the planar junction. The electron and hole transmissions of the devices are mainly contributed by the Mo atomic orbitals. The electron transport channel is located at the edge of armchair MoS₂ nanoribbon, while the hole transport channel is delocalized in the channel region. The I-V curve of the two-probe device shows typical transport behavior of Schottky barrier, and the threshold voltage is of about 0.2 V. The field effect transistors (FET) based on the planar junction turn out to be good bipolar transistors, the maximum current on/off ratio can reach up to 1 × 10⁴, and the subthreshold swing is 243 mV/dec. It is found that the off-state current is dependent on the length and width of the channel, while the on-state current is almost unaffected. The switching performance of the FET is improved with increasing the length of the channel, and shows oscillation behavior with the change of the channel width.     

An organic electrophosphorescent device driven by all-organic thin-film transistor using photoacryl as a gate insulator

Organic electrophosphorescent devices have been intensively investigated for using in full-color flat-panel display. Since the quantum efficiency of electrophosphorescent device decreases rapidly as the luminance increases, it is desirable to operate the electrophosphorescent display with active matrix rather than passive matrix. Here we report the study of driving electrophosphorescent diode with all-organic TFT. We obtained the maximum power luminance that was obtained about 90 cd/m². Turn-on voltage is approximately 10 V. Field effect mobility, threshold voltage, and on–off current ratio in 0.5-μm thick gate dielectric layer were 0.13 cm²/V s, −7 V, and 10⁶ A/A. The structure of electrophosphorescent diode is ITO/TPD/BCP:Ir(ppy)₃/BCP/Alq₃/Li:Al/Al. In organic TFT, photoacryl is used as an insulator and pentacene as an active layer.     

Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics

Recently, a number of semiconductor devices have been widely researched in order to make breakthroughs from the short-channel effects (SCEs) and high standby power dissipation of the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, a design optimization for the silicon nanowire tunneling field-effect transistor (SNW TFET) based on PNPN multi-junction structure and its radio frequency (RF) performances are presented by using technology computer-aided design (TCAD) simulations. The design optimization was carried out in terms of primary direct-current (DC) parameters such as on-current (I_on), off-current (I_off), current ratio (I_on/I_off), and subthreshold swing (SS). Based on the parameters from optimized DC characteristics, basic radio frequency (RF) performances such as cut-off frequency (f_T) and maximum oscillation frequency (f_max) were analyzed. The simulated device had a channel length of 60 nm and a SNW radius of 10 nm. The design variable was width of the n-doped layer. For an optimally designed PNPN SNW TFET, SS of 34 mV/dec and I_on of 35 μA/μm were obtained. For this device, f_T and f_max were 80 GHz and 800 GHz, respectively.