浮栅结构SOI LDMOS 器件的模拟研究

研究了一种具有浮栅结构的SOI LDMOS(FGSOI LDMOS)器件模型,并分析了该结构的耐压机理,通过Silvaco TCAD软件对该结构进行仿真优化。通过仿真验证可知,该结构通过类场板的结终端技术可以调节器件的横向电场,从而得到比普通SOI LDMOS器件更高的耐压并且降低了器件的比导通电阻。仿真结果表明,该结构与普通SOI LDMOS器件结构在相同的尺寸条件下耐压提高了41%,比导通电阻降低了21.9%。     

一种超低比导通电阻的L型栅漏极LDMOS

提出了一种具有超低比导通电阻的L型栅漏极LDMOS器件。该器件在两个氧化槽中分别制作L型多晶硅槽栅。漏极n型重掺杂区向下延伸,与衬底表面重掺杂的n型埋层相接形成L型漏极。L型栅极不仅可以降低导通电阻,还具有纵向栅场板的特性,可有效改善表面电场分布,提高击穿电压。L型漏极为电流提供了低阻通路,降低了导通电阻。另外,氧化槽折叠漂移区使得在相同耐压下元胞尺寸及导通电阻减小。二维数值模拟软件分析表明,在漂移区长度为0.9 μm时,器件耐压达到83 V,比导通电阻仅为0.13 mΩ·cm²。     

高k介质阶梯变宽度SOI LDMOS

本文提出了一种具有高k介质阶梯变宽度结构的新型的SOI LDMOS器件,该器件通过在漂移区内引入介质区域使得漂移区的宽度呈阶梯变化.借助三维器件仿真软件DAVINCI对其势场分布及耐压特性进行了深入分析.首先,阶梯变宽度结构能够在漂移区内引入新的电场峰值来优化势场分布,提高击穿电压.其次,采用高k材料作为侧壁介质区域可以进一步优化漂移区内势场分布,并提高漂移区浓度来降低导通电阻.结果表明,与常规结构相比,新器件的击穿电压可提高42%,导通电阻可降低37.5%,其FOM优值是常规器件的3.2倍.     

一种快速关断沟槽型SOI LDMOS器件

围绕降低沟槽型SOI LDMOS功率器件的优值,提出了一种新型多栅沟槽 SOI LDMOS器件(MG-TMOS)。与常规沟槽型SOI LDMOS(C-TMOS)器件相比,新型MG-TMOS器件在不牺牲击穿电压的同时,降低了器件开关切换时充放电的栅漏电荷和器件的比导通电阻。这是因为:1) 新型MG-TMOS器件沟槽里的保护栅将器件的栅漏电容转换为器件的栅源电容和漏源电容,大幅度降低了器件的栅漏电荷;2) 保护栅偏置电压的存在使得器件导通时会在沟槽底部形成一层低阻积累层,从而降低器件的导通电阻。仿真结果表明:该新型沟槽型SOI LDMOS器件的优值从常规器件的503.4 mΩ·nC下降到406.6 mΩ·nC,实现了器件的快速关断。     

带有P型埋层的新型双栅SOI MOSFET

本文提出一种超低比导通电阻(Ron,sp)可集成的SOI 双栅triple RESURF (reduced surface field)的n型MOSFET (DG T-RESURF)。这种MOSFET具有两个特点：平面栅和拓展槽栅构成的集成双栅结构(DG),以及位于n型漂移区中的P型埋层。首先, DG形成双导电通道并且缩短正向导电路径,降低了比导通电阻。DG结构在反向耐压时起到了纵向场板作用,提高了器件的击穿电压特性。其次, P型埋层形成triple RESURF结构 (T-RESURF),这不仅增加了漂移区的浓度,而且调节了器件的电场。这在降低了比导通电阻的同时提高了击穿电压。最后,与p-body区连接在一起的P埋层和拓展槽栅结构,可以显著降低击穿电压对P型埋层位置的敏感性。通过仿真,DG T-RESURF的击穿电压为325V,比导通电阻为8.6 mΩ?cm2,与平面栅single RESURF MOSFET(PG S-RESURF)相比,DG T-RESURF的比导通电阻下降了63.4%,击穿电压上升9.8%。     

一种新型的低导通电阻折叠硅SOI LDMOS

提出了一种具有折叠硅表面SOI-LDMOS(FSOI-LDMOS)新结构.它是将硅表面从沟道到漏端的导电层刻蚀成相互排列的折叠状,且将栅电极在较薄的场氧化层上一直扩展到漏端.由于扩展栅电极的电场调制作用使FSOI-LDMOS在比一般SOI-LDMOS浓度高的漂移区表面,包括折叠硅槽侧面形成多数载流子积累,积累的多数载流子大大降低了漂移区的导通电阻.并且沟道反型层浓度基于折叠的硅表面而双倍增加,沟道导通电阻降低.通过三维仿真软件ISE分析,这种结构可以在低于40V左右的击穿电压下,获得超低的比导通电阻.     

Numerical analysis of SOI LDMOS using a recessed source and a trench drain

A new SOI LDMOS using a recessed source and a trench drain was proposed to improve the on-characteristics at a given breakdown voltage. On-resistance and breakdown voltages of the proposed LDMOS are investigated by the two-dimensional simulator, MEDICI. The simulation results show that the on-resistance of the proposed and the conventional LDMOS are 76.3 and 129.5 mΩ mm², respectively. The on-resistance of the proposed LDMOS decreases by 41% compared to that of the conventional LDMOS at the same breakdown voltage of 36.5 V.     

一种RESURF效应增强的高压低阻槽型SOI LDMOS

本文提出一种RESURF效应增强（Enhanced RESURF Effect）的高压低阻SOI LDMOS（ER-LDMOS）新结构,并研究其工作机理。ER-LDMOS的主要特征是：漂移区中具有氧化物槽;氧化物槽靠近体区一侧具有P条;氧化物槽下方的N型漂移区中具有埋P层。首先,从体区延伸到氧化物槽底部的P条,不仅起到纵向结终端扩展的作用,而且具有纵向RESURF效果,此二者都优化体内电场分布且提高漂移区掺杂浓度;其次,埋P层在漂移区中形成triple RESURF效果,能够进一步优化体内电场并降低导通电阻;第三,漂移区中的氧化物槽沿纵向折叠漂移区,减小了器件元胞尺寸,进一步降低比导通电阻;第四,P条、埋P层、氧化物槽和埋氧层对N型漂移区形成多维耗尽作用,实现增强的RESURF效应,可达到提高漂移区掺杂浓度与优化电场分布的目的,从而降低导通电阻且提高器件耐压。仿真结果表明,在相同的器件尺寸参数下,与常规槽型SOI LDMOS相比,ER-LDMOS击穿电压提高67%,比导通电阻降低91%。     

具有L型低阻导电通道的介质场增强SOI LDMOS

A low specific on-resistance（R on;sp/ SOI NBL TLDMOS（silicon-on-insulator trench LDMOS with an N buried layer） is proposed. It has three features： a thin N buried layer（NBL） on the interface of the SOI layer/buried oxide（BOX） layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer.First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the R on;sp. Second, in the y-direction, the BOX＇s electric field（E-field） strength is increased to 154 V/ m from48 V/ m of the SOI Trench Gate LDMOS（SOI TG LDMOS） owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage（BV）, but also reduces the cell pitch and R on;sp. Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 m, and decreases the R on;sp by 80% at the same BV.     

超低比导通电阻SOI双栅槽型MOSFET

本文提出了超低比导通电阻(Ron,sp) SOI双栅槽型MOSFET(DG Trench MOSFET)。此MOSFET的特点是拥有双栅和一个氧化物槽：氧化物槽位于漂移区,一个槽栅嵌入氧化物槽,另一个槽栅延伸到埋氧层。首先,双栅依靠形成双导电沟道来减小Ron,sp;其次,氧化物槽不仅折叠漂移区,而且调制电场,从而减小元胞尺寸,增大击穿电压。当DG Trench MOSFET的半个元胞尺寸为3μm时,它的击穿电压为93V,Ron,sp为51.8mΩ?mm2。与SOI单栅MOSFET(SG MOSFET)和SOI单栅槽型MOSFET(SG Trench MOSFET)相比,在相同的BV下,DG Trench MOSFET的Ron,sp分别地降低了63.3%和33.8%。     

Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

An ultra-low specific on-resistance(R_on,sp) silicon-on-insulator（SOI） double-gate trench-type MOSFET （DG trench MOSFET） is proposed.The MOSFET features double gates and an oxide trench:the oxide trench is in the drift region,one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide.Firstly,the double gates reduce R_on,sp by forming dual conduction channels.Secondly,the oxide trench not only folds the drift region,but also modulates the electric field,thereby reducing device pitch and increasing the breakdown voltage（BV）.A BV of 93 V and a R_on,sp of 51.8 mΩ·mm² is obtained for a DG trench MOSFET with a 3μm half-cell pitch.Compared with a single-gate SOI MOSFET（SG MOSFET） and a single-gate SOI MOSFET with an oxide trench（SG trench MOSFET）,the R_on,sp of the DG trench MOSFET decreases by 63.3%and 33.8% at the same BV,respectively.     

A new double gate SOI LDMOS with a step doping profile in the drift region

uences of device parameters on BV and Ron, sp are investigated by simulation. The results indicate that BV is increased by 35.2% and Ron, sp is decreased by 35.1% compared to a conventional SOILDMOS.     

漂移区阶梯掺杂的双栅SOI LDMOS研究

A new double gate SOI LDMOS with a step doping profile in the drift region is proposed. The structure is characterized by one surface gate and another embedded gate under the P-body region. The broadened current flow path and the majority carrier accumulation layer on the side wall of the embedded gate reduce the specific on-resistance （Ron, sp）. The electric field distribution is improved due to the embedded gate and step doping profile, resulting in a high breakdown voltage （BV） and low Ron, sp. The influences of device parameters on BV and Ron, sp are investigated by simulation. The results indicate that BV is increased by 35.2% and Ron, sp is decreased by 35.1% compared to a conventional SOI LDMOS.     

Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch

An improved breakdown voltage （BV） SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches （DTMOS）, an oxide trench between the source and drain regions, and a trench gate extended to the buried oxide （BOX）. The proposed device has three merits. First, the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide （eox） than that of Si （esi）. Furthermore, the trench gate, the oxide trench, and the BOX cause multi-directional depletion, improving the electric field distribution and enhancing the RESURF （reduced surface field） effect. Both increase the BV. Second, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third, the trench gate not only reduces the on-resistance, but also acts as a field plate to improve the BV. Additionally, the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit （HVIC）, effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.     

High voltage SOI LDMOS with a compound buried layer

An SOI LDMOS with a compound buried layer (CBL) was proposed. The CBL consists of an upper buried oxide layer (UBOX) with a Si window and two oxide steps, a polysilicon layer and a lower buried oxide layer (LBOX). In the blocking state, the electric field strengths in the UBOX and LBOX are increased from 88 V/μm of the buried oxide (BOX) in a conventional SOI (C-SOI) LDMOS to 163 V/μm and 460 V/μm by the holes located on the top interfaces of the UBOX and LBOX, respectively. Compared with the C-SOI LDMOS, the CBL LDMOS increases the breakdown voltage from 477 to 847 V, and lowers the maximal temperature by 6 K.