Resonant tunnelling delta sigma modulator suitable for high-speed operation

A resonant tunnelling logic gate, monostable-bistable transition logic element (MOBILE), was used to test high frequency operation of the /spl Delta//spl Sigma/ modulator based on a frequency modulated intermediate signal. This /spl Delta//spl Sigma/ modulator has no feedback loop and is promising for high-speed operation. Good noise shaping characteristics over four decades were measured. This ideal noise shaping demonstrated that the MOBILE can work as an ideal quantiser.     

Tunable bandpass sigma delta modulator using one input parameter

A bandpass sigma delta modulator is proposed with a noise transfer function that is tunable by means of one parameter only. The centre frequency can be tuned in the range between DC to half the sampling frequency. The modulator stability and nearly constant resolution for the whole frequency range are demonstrated.     

Reliability aware design of low power continuous-time sigma–delta modulator

Circuit reliability has become a major bottleneck due to ageing degradation. In this paper, reliability-aware methodology and ageing analysis of low power sigma–delta (ΣΔ) modulator are presented. HCI and NBTI are considered as the dominating ageing effects. A second order continuous-time (CT) ΣΔ modulator is implemented for medical application. Ageing estimation is performed at both behavioral and transistor level. Results at behavioral level and transistor level show that the feedback loop in CT ΣΔ modulator is more sensitive and less reliable than the analog loop filter. Comparing with HCI, NBTI is the dominating ageing effect in the designed CT ΣΔ modulator.     

Opamp gain insensitive MASH sigma delta modulator for wide bandwidth applications

This work presents a means to enhance the immunity of non-ideal opamp gain effect of the fourth order multi-stage noise shaped (MASH) sigma-delta modulator (SDM) for wide bandwidth applications. The first stage of the SDM is a low-distortion single-loop second order SDM, while the second stage is a low-distortion interpolative second order SDM with Chebyshev type II filter technique. Theoretically, the conventional MASH SDM is impacted by the nonlinear finite gain of the operational amplifier. This impact may have two main phenomena. First, it leaks the incompletely corrected quantization error to the output. Secondly, the nonlinearity causes the harmonic distortion of the input signal. The proposed architecture can reduce the distortion and the sensitivity of the nonlinear finite opamp gain to improve the performance by using low-distortion technique in the MASH SDM. Furthermore, the lower power budget and simplified digital cancellation logic can be achieved. The experimental results indicate that the dynamic range (DR) can reach 87dB with power dissipation of 65 mW. A test SDM chip for Asymmetric Digital Subscriber Line (ADSL) application is designed and implemented by TSMC 0.25 um 1P5M process. Jen-Shiun Chiang was born in Taichung Taiwan, ROC in 1960. He received the B.S. degree in electronics engineering from Tamkang University, Taipei, Taiwan in 1983. In 1988, he received the M.S. degree in electrical engineering from University of Idaho, Moscow Idaho, USA. In 1992, he received the Ph.D. degree in the electrical engineering from Texas A & M University, College Station Texas, USA. He joined the faculty member of the Department of Electrical Engineering at Tamkang University in 1992. Currently, he is a Professor and Department Chair of the Department of Electrical Engineering at Tamkang University. Dr. Chaings research interest includes computer arithmetic, computer architecture, digital signal processing for VLSI architecture, architecture for image data compressing, analog to digital data conversion, and low power circuit design. Hsin-Liang Chen was born in Taipei, Taiwan, in 1974. He received the B.S. degree and M.S. degree in the electrical engineering from Tamkang University, Taipei, Taiwan, in 1997 and 2003, respectively. He is currently working toward the Ph.D. degree at Tamkang University. His research interest focuses on mixed-signal CMOS circuit, sigma delta ADC, and low power circuit.     

Design and implementation of a band-pass sigma delta modulator with distributed resonators

Continuous time band-pass sigma delta converters require the realization of high frequency resonators, which have been usually implemented with g _m-C or LC circuits. However, transmission lines have been for a long time a standard way to implement high Q resonators in RF circuits. Recently, some continuous-time sigma–delta (SD) modulator architectures using transmission lines have been proposed. Theoretical analyses have shown that this kind of architectures share some of the properties of both continuous-time (CT) and discrete-time (DT) modulators. On the other hand they have specific implementation problems which are not present in other modulator architectures. This paper makes a brief review of the particularities of these modulators and shows the experimental results of a band-pass modulator implemented in BiCMOS technology. As an advantage compared to standard continuous time designs, this modulator can be operated as a subsampling ADC, displays a better immunity to clock jitter and is tolerant to loop delay.     

A UHF current-mode continuous-time band-pass delta sigma modulator using fully balanced active inductor

This paper introduces a 2 GHz continuous-time (CT) fourth order current-mode (CM) band-pass 0.18 μm CMOS delta sigma modulator (DSM) utilizing a fully balanced active inductor. The proposed active inductor takes advantage of positive feedback topology and features accurate loss compensation as well as independent tunability of quality factor and resonant frequency. Based on this active inductor, a CM Ultra High Frequency (UHF) resonator is also proposed, exhibiting a very small on-chip area. Moreover, a high speed CM quantizer working with one single clock is brought into eliminate the error introduced by clock generators. The post layout simulation of the DSM exhibits a peak SNDR of 43.6 dB at 500 MHz with a 40 MHz signal bandwidth while the center frequency can be tuned between 450 and 500 MHz. The measured results give an averaged SNDR of 33 dB with 40 MHz signal bandwidth, where the center frequency is tunable from 300 MHz to 350 MHz. This design consumes only 45 mW under 1.8 V power supply and occupies an area of 0.133 mm².     

1GS/s pipelined delta sigma modulator ADC using residue averaging technique

A two stage pipelined delta sigma modulator (PDSM) ADC is presented for broadband, high-resolution applications, which incorporate a first, order delta sigma modulator in each stage and combines the most significant bits of the first stage with the second stage output. A key feature of the PDSM ADC architecture is a SINC filter residue averaging technique, which results in mitigating the effect of track/hold and analog, subtract circuit errors, DAC non-linearity, and component mismatch. The input bandwidth of 62.5 MHz and the sampling frequency of 1 GHz result in an over sampling ratio of 8 for the first order modulators. MATLAB simulations for the two stage ADC show 13–15 bit resolution. A transistor level design in 0.18 um CMOS for the two stage ADC was captured with Cadence tools and simulations show 12 bit resolution with a 50 MHz input.     

A novel noise-shaping DAC for multi-bit sigma-delta modulator

This paper describes a new noise-shaping technique for reducing the noise of the internal digital-analog conversion (DAC) in multi-bit low-pass sigma-delta modulators. The proposed technique works with most existing dynamic element matching (DEM) algorithms to provide noise shaping to the DAC noise. The simulation shows that a 10-dB improvement in the signal-to-noise conversion ratio can be obtained with the proposed noise-shaping with DEM (NSDEM) technique. A dithered DAC employing NSDEM is realized in a 0.35-/spl mu/m CMOS process and the test result shows the first-order high-pass noise shaping to the DAC noise, and validates the proposed concept.     

Constant-factor delta modulator

A companded delta modulator, employing an adaptation principle that produces voltages fed back to the error point in the coder which are discrete and multivalued, is achieved with just a 1 bit memory and simple signal processing, and is a significant invention. The constant-factor-delta-modulator system described here is an extension of this principle, which gives an improved signal/noise ratio at the output of the decoder and remove an objectionable hunting characteristic. These improvements are acquired due to a slight increase in the complexity of the coder.     

高阶级联多位∑-△调制器Simulink仿真设计

为了在低过采样率下实现大带宽、高精度的∑-△调制器,文中采用了级联2-1—1结构,前两级用一位量化器,在最后一级采用4位量化器。讨论了调制器中时钟抖动、热噪声、运放有限直流增益等非理想因素对调制器性能的影响。重点考虑最后一级反馈回路中多位DAC失配引起的非线性,并采用DWA算法对其进行线性化。在Simulink环境下对调制器做行为级仿真,包括理想与非理想模型。在16倍过采样率、35．2MHz采样频率下,可以达到90dB的信噪比。     

Characteristics of a delta modulator

Additional results from a previously described computer simulation of an adaptive delta modulator are presented and interpreted, and their relevance to a proposed upper bound on delta-modulator performance is indicated.     

Adaptive delta modulator for telephony

An adaptive version of the basic delta modulator employing full-width pulses and RC integration has been designed. A digital technique is used to sense the level of the input signal and to control the amplitude of the pulses supplied to the RC integrator in the feedback circuit. For an 800 Hz sinewave input a signal/quantisation-noise ratio of 32 dB has been obtained over a dynamic input range of 30 dB.     

Analysis of a delayed delta modulator

While delta modulation (DM) simply compares the current predictive estimate of the input with the current sample, delayed delta modulation (DDM) also compares with the upcoming sample so as to detect and anticipate slope overloading. Since this future sample must be available before the present output is determined and the estimate updated, delay is introduced at the encoding. The performance of DDM with perfect integration and step-function reconstruction is analyzed for each of three random input signals. In every case, the stochastic stability of the system is established. For a discrete time, independent and identically distributed input, the (limiting) joint distribution of input and output is derived, and the (asymptotic) mean-square sample point error mse(SP) is computed when the input is Gaussian. For a Wiener input, the joint distribution of the sample point and prediction errors is derived, and mse(SP) and the time-averaged mse (mse(TA)) are computed. For a stationary first-order Gauss-Markov input, the joint distribution of input and output is derived and mse(SP) and mse(TA) computed. Graphs of the mse's illustrate the improvement attainable by using DDM instead of DM. With optimal setting of parameters, mse(SP) (mse(TA)) is reduced about15percent (35percent).     

一款调制器和过采样率可配置的单芯片1.2V 95-55dB动态范围的Delta-Sigma模数转换器设计

A single die 1.2 V multi-stage noise shaping（Mash） 2-2 delta sigma analog to digital converter（ADC）for wide applications is implemented. The configurable Mash 2-2 modulator with a new decimation filter design is presented to achieve wide and high dynamic range（DR） for multiple practical applications. The novel modulator can be configured as a Mash 2-2 modulator for high precision or a 2-order modulator for low DR. The decimation filter is designed to select the OSR flexibly among cascaded integrator comb（CIC） filter and two half-band filters（HBF）. The serial peripheral interface（SPI） can be used to adjust the sampling frequency and the oversampling ratio（OSR）. The design was fabricated in a 0.13 m CMOS process with an area of 0.91 mm2and a total power of 5.2 mW. The measurement results show that the dynamic range（DR） of the proposed ADC can change from 55to 95 dB with the configurable OSR from 16 to 256. The spurious free dynamic range（SFDR） and signal-to-noise distortion ratio（SNDR） can get 99 dB and 86.5 dB, respectively.     

On the stability of sigma delta modulators

A framework for stability analysis of sigma-delta modulators is presented. It is argued that limit cycles for constant inputs are natural objects to investigate in this context. A number of analytical and approximate techniques to aid the stability analysis of the double loop and interpolative modulators are discussed and lead to ways of improving the design that explicitly take stability into account     

Precise integrator for linear delta modulator

A constant slope integrator for single integration linear delta modulation (LDM) will be described. The circuit essentially is a bootstrapped sweep generator, capable of generating positive and negative sweep voltages. It uses one transistor, four diodes, and two Zener diodes. The step size can be easily changed by changing the base resistance or charging capacitance. The circuit is versatile and may be used effectively in other waveform generators. The circuit is integrable.     

Two op-amps third-order sigma–delta modulator with 61-dB SNDR, 6-MHz bandwidth and 6-mW power consumption

This low-power SD\Sigma\Delta modulator targets the DVB-H requirements and achieves about 10 bit with 6-MHz signal band. Suitable topological modifications enable the realization of a third order modulator with two op-amps. Moreover, a technique for swing reduction of the last op-amp strongly reduces the number of comparators in the quantizer. The power reduction techniques limit the consumption to 6.18 mW, thus yielding a FoM of 0.58 pJ/conversion. The area of the circuit, fabricated with a 0.18-μm analog CMOS technology, is 0.32 mm². Experimental measurements confirm the behavioral study made accounting for the op-amps limitations.