Formation of Pd catalyst by Nd:YAG laser irradiation for electroless copper deposition

In this study, we attempt to develop an improved approach for patterning a thin activator by decomposing palladium acetate/acetone layer on nonconductive PI substrates with the second harmonic Q-switched Nd:YAG laser, using acetone instead of toxic chloroform as solvent. In particular, we have established a simple method to identify the decomposition mechanism of palladium acetate.Our developed process can produce copper with high purity and low resistivity achieved by electroless copper deposition on this thin activator.     

Room temperature electroless plating copper seed layer process for damascene interlevel metal structures

Described in this paper is the development of a room temperature electroless copper seed layer deposition process on ultra-thin TiN barrier layers. This novel process is compatible with damascene interlevel metal structures for sub-0.18 micron ULSI processes. An optimum copper layer thickness of 50 nm and a deposition rate of 45 nm min⁻¹ was targeted and obtained. Atomic force microscopy (AFM) reveals that the non-uniformity of the seed layer is less than 10% of the film thickness, while four-point probe measurements indicate that the resistivity of the copper seed layer is less than 6 μΩ cm⁻¹. Secondary ion mass spectroscopy (SIMS) reveals that potential metallic contaminants such as sodium, potassium, calcium and magnesium ions do not penetrate the TiN barrier layer. Rutherford back scattering (RBS) indicates that the palladium concentration in the seed layer is approximately 1%, which is low enough to avoid wafer contamination and increased resistivity in the subsequent electroplated copper layer.     

New plating bath for electroless copper deposition on sputtered barrier layers

A new copper plating bath for electroless deposition directly on conductive copper-diffusion barrier layers has been developed. This plating bath can be operated at temperatures between 20 and 50°C and has good stability. High temperature processing allows for increased deposition rates and decreased specific resistivity values for the deposited copper films. Electroless Cu films deposited from this bath showed a conformal step coverage in high aspect ratio trenches and, therefore, are promising as seed layers for copper electroplating. The effect of the bath composition, activation procedure and processing temperature on the plating rate and morphology of the deposited copper has been studied and is presented here.     

Innovative wire bonding method using a chemically reacted thin layer for chips with copper interconnects

This paper presents a novel method in which an oxide film is used to facilitate the thermosonic wire bonding of gold wire onto copper pads. A cuprous oxide film is generated by controlling the pH values of the chemical solution. Compared to cupric oxide films, the cuprous oxide film is denser and more brittle and therefore facilitates the bonding process without the need for the elaborate procedures and equipment required by more conventional wire bonding methods.     

次亚磷酸钠作还原剂化学镀铜工艺研究

近年来,化学镀铜技术在PCB行业、机械工业、航空航天等各行业有着越来越广泛的应用,有关化学镀铜的机理研究和工艺路线改进等课题已成为当今材料表面处理研究领域的热点之一。然而,以甲醛为还原剂的传统化学镀铜工艺受绿色制造的要求,其使用将受到限制,开发非甲醛体系化学镀具有巨大市场潜力。本文采用RF-4环氧树脂为基材,研究了以次亚磷酸钠为还原剂的化学镀铜工艺的改进,并且讨论了添加剂的加入对镀铜层形貌和性能的影响。     

Fabrication of potential NiMoP diffusion barrier/seed layers for Cu interconnects via electroless deposition

Potential NiMoP barrier/seed layers for Cu interconnects have been successfully formed by electroless deposition on SiO₂. Four different wet processes were attempted to activate the surface before electroless deposition. Material properties including the crystal structure, deposition rate, composition, and electrical resistivity of NiMoP layers were investigated by atomic force microscopy (AFM), scanning electron microscopy (SEM), Auger electron spectroscopy, x-ray diffraction (XRD), four-point probe, and surface profilometry (Alpha-step). In this study, different compositions of NiMoP films have been obtained. Ni₈₉Mo₂P₉ with nanocrystalline structure has the highest resistivity due to enriched P content, while Ni₈₈Mo₉P₃ has the lowest value among the compositions considered in this study. The seed layer and the barrier layer functions of NiMoP were verified by direct Cu electrodeposition and secondary ion mass spectroscopy (SIMS).     

纳米化学复合镀的开发及在PCB制造中的应用研究

化学镀表面处理技术使用范围很广,镀层均匀、装饰性好;在防护性能方面,能提高产品的耐蚀性和使用寿命;在功能性方面,能提高加工件的耐磨性和导电性、润滑性能等特殊功能,因而成为表面处理技术的一个重要部分。钠米化学复合镀是在化学镀液中加入纳米粒子,使其与化学镀层共沉积的工艺技术。文章主要研究在化学镀Ni-P中加入纳米颗粒,在基体表面沉积具有镀厚均匀、耐磨、耐腐蚀、可焊的纳米复合镀层,阐明镀液组成和工艺条件对沉积速率、镀液稳定性、镀层与基体的结合力的影响,获得钠米化学复合镀技术的工艺参数,并对纳米复合镀层的性能进行了研究。     

氧化铝陶瓷基板化学镀铜金属化及镀层结构

通过化学镀铜在氧化铝陶瓷基板表面实现了金属化,采用SEM研究了镀铜层表面微观形貌以及热处理的影响,检测分析了金属化镀层附着力。结果表明:通过控制镀液中铜离子浓度以及铜沉积速率,在基板表面可形成均匀致密的铜金属化层;热处理后进一步提高镀层致密化和导电性,其方阻由3.6 mΩ/□降为2.3 mΩ/□。划痕法测试表明镀铜层与氧化铝陶瓷基板结合紧密无起翘,可以满足敷铜基板的要求。     

印制电路板直接电镀技术

印制电路板（PCB）是绝大多数电子产品实现电子器件互联的基板。传统的印制板制造要用到化学镀铜等化学工艺。这些工艺中要用到一些对人体和环境有影响的化学品,同时要使用和排放大量的水,其中含有致癌物甲醛等各种化学物质,因而带来严重环境问题。为此,开发了替代这些对环境有严重污染的工艺的新技术,这就是印制板直接电镀技术。其关键是采用了导电聚合物来替代化学镀铜。     

Conformal electroless deposition of Cu seed layer on a 60-nm trench pattern modified with a self-assembled monolayer

We have developed a novel activation technique for the conformal electroless deposition (ELD) of Cu on a SiO₂ substrate modified with an organic self-assembled monolayer. The SiO₂ substrate was modified with amine groups using 3-aminopropyltriethoxysilane and Au nanoparticles (AuNPs) to form a uniform, continuous catalyst for ELD. The Au catalytic layer formed on the amine-SiO₂ substrate was stabilized by electrostatic interactions between the positively charged protonated-amine self-assembled monolayer (SAM) and negatively charged AuNPs. Cu films were then electrolessly deposited on Au-catalyzed SiO₂ substrates. The Cu seed layer formed by this method showed a highly conformal and continuous structure. Cu electrodeposition on the 60-nm trench was demonstrated using an acid cupric sulfate electrolyte containing chloride, polyethylene glycol 4000 and bis(3-sulfopropyl)disulfide. The resulting electroplated Cu showed excellent filling capability and no voids or other defects were observed in a 60-nm trench pattern.     

Atomic layer chemical vapour deposition of copper

Copper films with (1 1 1) texture are of crucial importance in integrated circuit interconnects. We have deposited strongly (1 1 1)-textured thin films of copper by atomic layer deposition (ALD) using [2,2,6,6-tetramethyl-3,5-heptadionato] Cu(II), Cu(thd)₂, as the precursor. The dependence of the microstructure of the films on ALD conditions, such as the number of ALD cycles and the deposition temperature was studied by X-ray diffraction, scanning electron microscopy (SEM), and transmission electron microscopy. Analysis of (1 1 1)-textured films shows the presence of twin planes in the copper grains throughout the films. SEM shows a labyrinthine structure of highly connected, large grains developing as film thickness increases. This leads to low resistivity and suggests high resistance to electromigration.     

Investigation of electroless cobalt-phosphorous layer and its diffusion barrier properties of Pb-Sn solder

The capability of a cobalt-phosphorous [Co(P)] layer, which was grown via the electroless plating process, to serve as the diffusion barrier of lead-tin (PbSn) solder was investigated in this work. The Auger electron spectroscopy (AES) and energy dispersive spectrometry (EDX) indicated that the phosphorous contents in Co(P) films decrease with increasing film thickness and that the average contents are no less than 8.7 at.% for the specimens prepared in this work. X-ray diffraction in conjunction with composition analyses revealed that the electroless Co(P) layer was a mixture of amorphous and nanocrystalline structures; however, the AES depth profile and subsequent analyses indicated that the first-formed Co(P) layer should be amorphous because it contains as much as 18 at.% P. This implied a good barrier capability for electroless Co(P) because, as revealed by EDX line scan, the Sn and Cu atoms could not penetrate the Co(P) layer after the PbSn/Cu/Co(P)/Cu/Ti/Si sample was subjected to annealing at 250°C in a forming gas ambient for 24 h. The fact that Sn and Cu underlayers could not penetrate the Co layer after such a liquid-state annealing step was evidence that the Co(P) layer may simultaneously serve as a diffusion-barrier interlayer dielectric and as an under-bump metallization for flip-chip copper (Cu) ICs.     

Physical investigation of the impact of electrolessly deposited self-aligned caps on insulation of copper interconnects

With the miniaturization of ULSI circuits and the associated increase of current density up to several MA/cm², copper interconnects are facing electromigration issues at the top interface with the dielectric capping layer SiC(N). A promising solution is to insert selectively on top of copper lines a CoWP metallic self-aligned encapsulation layer, deposited using a wet electroless process. We study the impact of this process on electrical line insulation as a function of cap thickness at the 65 nm technology node and we investigate the physical origin of leakage currents. Below a critical thickness, only a slight leakage current increase of less than one decade is observed, remaining within the specification for self-aligned capping layer processes. Above this critical thickness, large leakage currents are generated due to the combined effect of lateral growth and the presence of parasitic redeposited nodules. We show that a simple phenomenological model allows to reproduce the experimental data, to assess quantitatively the contribution of parasitic defects, and to predict that the self-aligned barrier technology should be extendible up to the 32 nm node, provided that a thin cap layer of less than 8 nm is used.     

纳米钯材料的制备及其在PCB化学镀铜中的应用

以二水合氯化钯为原料,PVP（聚乙烯吡咯烷酮）为分散剂,抗坏血酸（从）为还原剂,在常温下还原Pd^2＋制备纳米钯。通过激光动态散射法（DSL）,透射电子显微镜（TEM）和X射线衍射仪（XRD）对纳米钯进行了表征分析,结果显示,在PVP分散剂的作用下,得到的纳米钯为粒径8nm～22nm,无其他的氧化物存在。该纳米钯材料可作为化学沉铜的活化液,可以减少沉铜的工艺步骤,经过金相显微镜观测化学镀铜后的孔背光级数均达到10级,通过扫描电镜观察镀铜层表面颗粒均匀、平整。所制备的纳米钯是一种优异的化学镀铜活化剂。     

Effect of copper seed aging on electroplating-induced defects in copper interconnects

Voids in copper thin films, observed after electroplating, have been linked to seed aging that occurs when a wafer is exposed, over time, to clean-room ambient. Oxidation of the copper seed surface prevents wetting during subsequent copper electroplating, leading to voids. Several surface treatments were employed to counteract the seed aging effect, including reduction of the copper oxide film by hydrogen, reverse plating of the copper surface, and rinsing the wafer surface with electrolyte. Each treatment was applied to wafers increasingly aged from 2 to 14 days, just prior to electroplating. Results showed a significant decrease in postelectroplating defects with all three treatments. The reduction of copper oxide by hydrogen exhibited the most marked results. An increase in surface wetting is shown by a decrease in contact angle measurements and an increase in film reflectivity for treated versus untreated copper wafers. This study shows that, although the copper surface exhibits strong aging effects over a short period of time, using proper surface treatments can eliminate such effects and voids.     

Annealing textures of copper damascene interconnects for ultra-large-scale integration

The annealing textures of copper interconnects depend upon their deposition textures and geometries. The copper interconnects are subjected to tensile stresses even at room temperature, which in turn gives rise to strain energies. The stress distributions in interconnects are not homogeneous due to trenches, resulting in non-fiber-type textures after annealing. To better understand the formation of the non-fiber-type textures, the textures of specimens of 0.2–6 μm in trench width with 0.2 μm in space were measured, and the strain energy and stress distributions have been simulated. The simulation results indicate that strain energy density is highest at the upper corners of trench. Therefore, the grain growth rate at the upper corners is fastest, resulting in the {111}〈110〉 annealing texture. As the trench width increases, the influence of stresses in the trench increases, even though the strain energy density in the trench is relatively low. In this case the {111}〈112〉 component increases, even though the formation of the {111}〈110〉 orientation cannot be excluded.     

Thermosonic bonding of gold wire onto silver bonding layer on the bond pads of chips with copper interconnects

A copper pad oxidizes easily at elevated temperatures during thermosonic wire bonding for chips with copper interconnects. The bondability and bonding strength of a gold wire onto a bare copper pad are seriously degraded by the formation of a copper oxide film. A new bonding approach is proposed to overcome this intrinsic drawback of the copper pad. A silver layer is deposited as a bonding layer on the surface of copper pads. Both the ball-shear force and the wire-pull force of a gold wire bonded onto copper pads with silver bonding layers far exceed the minimum values stated in the JEDEC standard and MIL specifications. The silver bonding layer improves bonding between the gold ball and copper pads. The reliability of gold ball bonds on a bond pad is verified in a high-temperature storage (HTS) test. The bonding strength increases with the storage time and far exceeds that required by the relevant industrial codes. The superior bondability and high strength after the HTS test were interpreted with reference to the results of electron probe x-ray microanalyzer (EPMA) analysis. This use of a silver bonding layer may make the fabrication of copper chips simpler than by other protective schemes.     

Microstructural characterization of inlaid copper interconnect lines

The microstructure of inlaid Cu lines has been quantified as a function of annealing conditions, post-plating, and post-CMP. The grain size distribution was measured using the median intercept method, crystallographic texture was characterized by pole figure analysis, and mechanical stress was determined using x-ray diffraction. The median grain size and mechanical stress level increase with increasing anneal temperature. The crystallographic texture is independent of the anneal temperature and is predominantly (111) with a small fraction of sidewall-nucleated (111) grains. The (111) grains nucleated from the trench bottom have a preferred in-plane orientation. The grain growth in the trench is independent of that in the overburden.     

Texture investigation of copper interconnects with a different line width

To understand the effect of line width on textural and microstructural evolution of Cu damascene interconnect, three Cu interconnects samples with different line widths are investigated. According to x-ray diffraction (XRD) results, the (111) texture is developed in all investigated lines. Scattered {111}〈112〉 and {111}〈110〉 texture components are present in 0.18-μm-width interconnect lines, and the {111}〈110〉 texture was developed in 2-μm-width interconnect lines. The directional changes of the (111) plane orientation with increased line width were investigated by XRD. In addition, microstructure and grain-boundary character distribution (GBCD) of Cu interconnect were measured using electron backscattered diffraction (EBSD) techniques. This measurement demonstrated that a bamboo-like microstructure is developed in the narrow line, and a polygranular structure is developed in the wider line. The fraction of ∑3 boundaries is increased as the line width increases but is decreased in the blanket film. A new interpretation of textural evolution in damascene interconnect lines after annealing is suggested, based on the state of stress and growth mechanisms of Cu deposits.     

耐电镀光致抗蚀干膜对化学镀镍镀层的影响

文章从FPCB生产案例金裂问题出发,研究讨论了耐电镀光致抗蚀干膜对化学镀镍药水pH值、镀层厚度、表面形貌和脆性的影响,并采用弯折法定性研究了干膜对化学镀镍镀层脆性的影响。结果显示干膜在化学镀镍药水中长时间浸泡使溶出物大量积累会增大化学镀镍镀层脆性。