Rail-to-rail low-power high-slew-rate CMOS analogue buffer

A low-power rail-to-rail CMOS analogue buffer is presented. The circuit is based on an input stage made up of two complementary class AB differential pairs, while a simple additional circuit allows rail-to-rail operation at the output terminal. The proposed circuit combines low static power consumption and high drive capability, resulting in suitability for applications with large capacitive loads. Simulated results are provided.     

Large-swing CMOS buffer amplifier

A circuit configuration for a CMOS buffer amplifier is described. The circuit, which is an enhancement of a previously reported buffer amplifier, features a large output voltage swing and a well-controlled quiescent current. A buffer amplifier of this type has been implemented in a 1.5-μm CMOS technology. The prototype occupies an area of 275 mil². It works with a 5-V supply and can drive more than 4.2 V (peak to peak) in to 300 Ω with a total harmonic distortion of less than 0.025%     

低功耗宽带CMOS低噪声放大器

本文实现了一款低功耗的宽带低噪声放大器(LNA)。该低噪放由输入级、中间级和输出级组成。由于每一级都采用了电流复用技术,显著地降低了功耗。输入级通过电阻、电容负反馈和并联电感,实现了良好的输入匹配。引入电感抵消了电容产生的虚部阻抗并且抵消了电容产生的极点。与电阻负反馈放大器相比,本文提出的结构提高了增益。中间级通过并联电感引入零点,采用低Q值拓展带宽。输出级是源级跟随器,提供了良好的输出匹配。经0.18 μm TSMC CMOS工艺仿真验证,在3 V的电源电压下,功耗仅为4.89 mW。另外在1~4.5 GHz频带范围内,电压增益(S21)为14.8±0.4 dB,噪声系数(NF)介于3.1~4.2 dB之间,输入、输出反射系数(S11、S22)均小于-10 dB。在4GHz时,输入三阶交调点(IIP3)达到-11dBm。     

Low-power CMOS/BiCMOS drivers and receivers for on-chipinterconnects

Novel low-voltage swing CMOS and BiCMOS driver/receiver circuits for low-power VLSI applications are proposed. Interconnect wire drivers with low output signal swing are employed. Special receivers provide single and double level conversion while minimizing the total driver/receiver transmission delay. These level converters have no DC power dissipation. At 3.3 V power supply voltage, the proposed circuits consume less power without delay penalty. The power saving is observed to be as high as 30%. At lower supplies further power and delay improvements are observed     

A highly linear CMOS buffer amplifier

A CMOS buffer amplifier which achieves significant improvements in linearity and drive capability over previously reported high-swing amplifiers is described. The buffer operates from a 5-V supply, is capable of rail-to-rail operation at both the input and output, an exhibits a remarkably high linearity of 0.05% THD while driving 3 V/SUB p-p/ into 100 /spl Omega/ at 20 kHz.     

Fast CMOS current amplifier and buffer stage

A novel CMOS current amplifier stage is described which provides a low impedance and an accurately controlled DC bias voltage at its input terminal, as well as an accurate current gain in a wide frequency range.     

Micro Fabry Perot light modulator for flat panel display

A new type of Fabry Perot light modulator for displays based on micro-electro-mechanical system technology is proposed. Multiple beam interference theory is used to design the modulator and analyze its characteristics. If Fabry Perot cavity length is one-quarter of the incident wavelength, the transmitted light is blocked by the modulator, and the modulator, which is illuminated from its backside, appears black. If the Fabry Perot cavity length is 0 or one-half of the incident wavelength, light may transmit the Fabry Perot modulator from its backside, and the modulator appears bright. Hence, the modulator may be used for flat panel displays. In this paper one Fabry Perot light modulator based on surface microma-chining technology is introduced. The designed modulator has a contrast ratio of 150 and can theoretically be driven by a voltage of 2.4 V.     

Current-feedback architecture for high-slew-rate and low-THD high-end audio amplifier

The design of a current-feedback (CF) amplifier for high end power audio applications, up to 200 W RMS, is presented. Measured results prove that the proposed scheme achieves optimal signal-to-noise ratios and total harmonic distortion levels on the entire audible frequency range. Thanks to the CF topology the amplifier also features high bandwidth and high slew-rate.     

A novel tunable gain CMOS buffer amplifier for large resistive loads

An all-OTA analog buffer amplifier configuration capable of driving large resistive loads is presented. The proposed configuration features high input swing, gain tunability, wide-bandwidth, and low design complexity. The concept is validated with simulation results in Cadence Virtuoso using SCL 0.18-μm technology parameters. Using a ±0.9 V power supply, the buffer with a gain of 1, can drive a 1 V_p−p sinusoid into a 50 Ω load with a THD of better than 0.015%, with a 3-dB bandwidth of 1.55 GHz and consumes 9 mW. The proposed configuration is demonstrated with gain values varying from 0.25 V/V to 5 V/V and with different load values 16 Ω to 5.6 kΩ. The voltage gain is tunable over more than a decade with reasonable power levels. With low-gain OTA, the proposed buffer configuration works well without any complex frequency compensation circuit that makes the all-OTA analog buffer amplifier configuration simple compared to the existing buffer amplifiers.     

Laser soldering for chip-on-glass mounting in flat panel display application

Chip-on-glass (COG) mounting of area array electronic packages was attempted by heating the rear surfrace of a contact pad film deposited on a glass substrate. The pads consisted of an adhesion (i.e., Cr or Ti) and a top coating layer (i.e., Ni or Cu) was heated by an UV laser beam transmitted through the glass substrate. The laser energy absorbed on the pad raised the temperature of a solder ball which was in physical contact with the pad, forming a reflowed solder bump. The effects of the adhesion and top coating layer on the laser reflow soldering were studied by measuring the temperature profile of the ball during the laser heating process. The results were discussed based on the measurement of reflectivity of the adhesion layers. In addition, the microsctructures of solder bumps and their mechanical properties were examined.     

用于平板显示LTPS制备的ELA光束整形系统

介绍了多晶硅薄膜较非晶硅薄膜在平板显示领域的优势以及准分子激光晶化制备多晶硅膜的结晶过程。介绍了透镜阵列实现匀光的原理。阐述了典型的准分子激光退火线型光束整形系统的扩束、匀光、投影等结构。并介绍了连续横向固化技术在准分子激光制备低温多晶硅领域的应用。讨论了准分子激光退火光学系统的发展现状,指出了其在平板显示行业的重要意义。     

一种用于液晶显示的高转换速率恒定跨导运算放大器

To drive the backplane of a liquid crystal display device and achieve different kinds of grey levels, a high-slew-rate operational amplifier with constant-gin input stage is presented. A Zener-diode structure is inserted between the tails of the complementary input pairs to keep the grn of the input stage constant. A novel slew rate enhancement circuit is implemented to achieve a very high slew rate. The chip has been implemented in a 0.5μm CMOS process and the chip area of the operational amplifier circuit is 0.11 mm^2. The testing results indicate that in the 5-8 V input range, the maximum gm fluctuation is only 4.2%. The result exhibits a high slew rate of 111 V/μs and 102 V/μs for the rising and falling edges under a 20 pF capacitance load, and the low frequency gain is up to 109 dB with a phase margin of 70 ℃.     

Utilizing white OLED for full color reproduction in flat panel display

Full color reproduced by white OLED (organic light emitting diodes) coupled with transmission color filters for the application in flat panel display was analyzed theoretically and experimentally. A white emitter made up of three primary emission peaks was found to be superior to a white emitter made up of complementary colors, i.e. two emission peaks. However, though the full color reproduction by white emitter possesses the merit of manufacturing simplicity, it is much worse than the color reproduction by three individual primary color sub-pixels, in terms of power efficiency and the power consumption. Adjusted to the same external quantum efficiency, the full color pixel made of three primary color sub-pixels is 10 times more efficient than that made of white emitter coupled with color filters.     

A CMOS differential buffer amplifier with accurate gain andclipping control

A CMOS fully differential buffer amplifier with accurate gain and clipping control is presented. The gain is made variable by controlling the amount of the feedback around the power amplifier by means of an additional gain control loop. A new clipping technique is used to control the clipping level of the amplifier. The amplifier is realized in a 1.2 μm CMOS process with a single 5 V power supply. Measurements confirm the presented techniques     

A constant-g_m and high-slew-rate operational amplifier for an LCD driver

To drive the backplane of a liquid crystal display device and achieve different kinds of grey levels, a high-slew-rate operational amplifier with constant-gin input stage is presented. A Zener-diode structure is inserted between the tails of the complementary input pairs to keep the gm of the input stage constant. A novel slew rate enhancement circuit is implemented to achieve a very high slew rate. The chip has been implemented in a 0.5μm CMOS process and the chip area of the operational amplifier circuit is 0.11 mm~2. The testing results indicate that in the 5-8 V input range, the maximum gm fluctuation is only 4.2%. The result exhibits a high slew rate of 111 V/μsand 102 V/μs for the rising and falling edges under a 20 pF capacitance load, and the low frequency gain is up to109 dB with a phase margin of 70 ℃.     

Low-power CMOS distributed amplifier using new cascade gain cell for high and low gain modes

A CMOS distributed amplifier (DA) with low-power and flat and high power gain (S₂₁) is presented. In order to decrease noise figure (NF) an RL terminating network used for the gate transmission line instead of single resistance. Besides, a flat and high S₂₁ is achieved by using the proposed cascade gain cell consist of a cascode-stage with bandwidth extension capacitor. In the high-gain mode, under operation condition of V _dd  = 1.2 V and the overall current consumption of 7.8 mA, simulation result shown that the DA consumed 9.4 mW and achieved a flat and high S₂₁ of 20.5 ± 0.5 dB with an average NF of 6.5 dB over the 11 GHz band of interest, one of the best reported flat gain performances for a CMOS UWB DA. In the low-gain mode, the DA achieved average S₂₁ of 15.5 ± 0.25 dB and an average NF of 6.6 dB with low power consumption (P_DC) of 3.6 mW, the lowest P_DC ever reported for a CMOS DA or LNA with an average gain better than 10 dB.     

A compact rail-to-rail CMOS buffer amplifier with very low quiescent current

In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystal display (LCD) applications is proposed. Compared to other buffer amplifiers, the proposed circuit has a very simple architecture, occupies a small number of transistors and also has a large driving capacity with very low quiescent current. It is composed of two complementary differential input stages to provide rail-to-rail driving capacity. The push–pull transistors are directly connected to the differential input stage, and the output is taken from an inverter. The proposed buffer circuit is laid out using Mentor Graphics IC Station layout editor using AMS 0.35 μm process parameters. It is shown by post-layout simulations that the proposed buffer can drive a 1 nF capacitive load within a small settling time under a full voltage swing, while drawing only 1.6 μA quiescent current from a 3.3 V power supply.     

A liquid-crystal display panel using an MOS array with gate-bus drivers

A 220- × 240-element liquid-crystal 2-in television display panel, using an MOSFET/capacitor array with gate-bus drivers integrated onto the same silicon substrate, has been developed. A gold-nickel alloy and polyimide resin have been applied as reflective display electrodes and insulating interlayer, respectively. In this panel, considerable reduction in the number of interconnections and good display contrast have been attained. MOS array construction and fabrication, gate-bus driver circuit configuration, and panel performance are described in this paper.     

Low-power CMOS current conveyor

A novel second-generation CMOS current conveyor based on a new adaptive biasing technique is proposed. It is shown that the use of this circuit offers an excellent performance and leads to a significant reduction in the standby power dissipation. PSPICE simulation results, assuming 0.5 μm CMOS process, are also given