Power losses and efficiency of class-E power amplifier at any duty ratio

This paper presents an analysis of the effect of duty ratio on power loss and efficiency of the Class-E amplifier. Conduction loss for each Class-E circuit component is derived and total amplifier losses and efficiency are expressed as functions of duty ratio. Two identical 300-W Class-E amplifiers operating at 7.29 MHz are designed, constructed, and tested in the laboratory. Dependence of total efficiency upon duty ratio when using real components is derived and verified experimentally. Derived loss and efficiency equations demonstrate rapid drop in efficiency for low duty ratio (below approximately 30%). Experimental results very closely matched calculated power loss and efficiency.     

WPT中高效E类功率放大器的研究

作为无线电能传输(WPT)系统的核心部件之一,E类功率放大器的理论效率可达100%,具有很好的研究前景。本文对E类功率放大器进行理论分析与设计建模,运用电磁仿真软件ADS进行仿真,通过源牵引和负载牵引进行最佳阻抗匹配以优化效率,基于仿真结果进行了硬件电路设计制作。结果表明,设计制作的E类功放在27~29MHz输出的最大功率附加效率(PAE)为91.3%,同时获得17.5 d B的功率增益,验证了设计的正确性与可行性。     

Tuning analysis for the high-Q class-E power amplifier

The effects of component variations on a high-Q class-E amplifier are simulated and measured. Design equations are provided for the case of a 50% duty cycle with B at its optimum value for a given R. Six distinct operating points are analyzed for the output network. The problem of tuning a high-Q class-E amplifier is addressed. Normally, it cannot be tuned for maximum output power without degrading efficiency. An auxiliary circuit is added to the design so that it can be tuned for maximum output power in order to achieve optimum efficiency. Measured data are obtained at low frequencies for an amplifier with a loaded Q of 340     

A high-efficiency class-E GaN HEMT power amplifier at 1.9 GHz

A single stage class-E power amplifier in GaN high electron mobility transistor (HEMT) technology is reported. The circuit operates at 1.9 GHz. At 30-V drain bias, a power-added-efficiency (PAE) of 57% and a maximum output power of over 37dBm was achieved, corresponding to a power density of 5.25W/mm. At 40-V drain bias, an output power of 38.7dBm is achieved at 50% PAE corresponding to a power density of 7.4W/mm.     

Analysis and design of continuous class-E power amplifier at sub-nominal condition

The continuous class-E power amplifier at sub-nominal condition is proposed in this paper. The class-E power amplifier at continuous mode means it can be high efficient on a series matching networks while at sub-nominal condition means it only requires the zero-voltage-switching condition. Comparing with the classical class-E power amplifier, the proposed design method releases two additional design freedoms, which increase the class-E power amplifier’s design flexibility. Also, the proposed continuous class-E power amplifier at sub-nominal condition can perform high efficiency over a broad bandwidth. The performance study of the continuous class-E power amplifier at sub-nominal condition is derived and the design procedure is summarised. The normalised switch voltage and current waveforms are investigated. Furthermore, the influences of different sub-nominal conditions on the power losses of the switch-on resistor and the output power capability are also discussed. A broadband continuous class-E power amplifier based on a Gallium Nitride (GaN) transistor is designed and testified to verify the proposed design methodology. The measurement results show, it can deliver 10–15 W output power with 64–73% power-added efficiency over 1.4–2.8 GHz.     

A class-E power amplifier for wireless biomedical systems

This letter presents the design, implementation and experimental results of a class-E power amplifier (PA) suitable for wireless biomedical sensor nodes (WBSNs) integrated into a wireless body area network (WBAN). A self-biased inverter is used as a preamplifier stage to provide a 50 %-duty-cycle square wave to drive the class-E PA. The design (PA with the preamplifier), which is fabricated in a 0.18-μm CMOS technology, achieves 40.2 % drain efficiency while output power is 14.7 dBm at 433 MHz under 1.2-V supply, as demonstrated by the experimental results.     

A cascode modulated class-E power amplifier for wireless communications

A cascode modulated CMOS class-E power amplifier (PA) is presented in this paper. It is shown that by applying a modulated signal to the gate of the cascode transistor the output power is modulated. The main advantage of the proposed technique is a high 35 dB output power dynamic range. The peak power added efficiency (PAE) is 35%. The concept of the cascode power control of class-E RF PA operating at 2.2 GHz with 18 dBm output power was implemented in a CMOS technology and the performance has been verified by measurements. The prototype CMOS PA is tested by single tone excitation and by enhanced data rates for GSM evolution (EDGE) modulated signal. Digital predistortion is used to linearize the transfer characteristic. The EDGE spectrum mask is met and the rms error vector magnitude (EVM) is less than 4° in the entire output power range.     

A power-efficient injection-locked class-E power amplifier for wireless sensor network

In this letter, we present an injection-locked Class-E power amplifier (Class-E ILPA) suitable for 2.4-GHz wireless sensor network applications where the maximum transmit-power is typically about 10dBm. In such a low transmit-power application, it is a great challenge to achieve a high transmit efficiency because the driving power and dc power consumption in the previous stage are no more negligible compared with the transmitted signal power. The proposed Class-E ILPA, which is fully integrated in 0.18-/spl mu/m CMOS technology, achieves the power added efficiency of 44.5% while delivering the output power of 11dBm with drain efficiency of 49.3% at 1.2-V supply voltage. The measured locking range reaches 300MHz with the input driving power of -6dBm.     

Design of inverse class-E amplifier with finite D.C. feed inductance

This paper reports on a design of inverse class-E amplifier with finite D.C. feed inductance. The finite D.C. feed inductance is resonated by the parallel capacitance at the fundamental frequency. The direct design equations required to determine the optimum operations are derived in detail. Comparing with the classic inverse class-E amplifier, numerical results show that improvements in minimizing size, cost, and complexity of the circuit can be obtained by the inverse class-E topology with finite D.C. feed inductance. Comparing with the sub-harmonic and parallel-circuit class-E amplifiers, the inverse class-E topology with finite D.C. feed offers advantages for MMIC realization. Theoretical analysis is validated by numerical simulation and measurement. Excellent agreement between theory and simulation results is achieved. Comparison between simulations and measurements of an experimental circuit validate the feasibility of the design. A measured output power of 40.01 dBm, with a drain efficiency of 80.16% and power-added efficiency of 78.93% were obtained at 250 MHz with a 22-dBm input power.     

An optimal design methodology for inductive power link with class-E amplifier

This paper presents a design methodology of a highly efficient power link based on Class-E driven, inductively coupled coil pair. An optimal power link design for retinal prosthesis and/or other implants must take into consideration the allowable safety limits of magnetic fields, which in turn govern the inductances of the primary and secondary coils. In retinal prosthesis, the optimal coil inductances have to deal with the constraints of the coil sizes, the tradeoffs between the losses, H-field limitation and dc supply voltage required by the Class-E driver. Our design procedure starts with the formation of equivalent circuits, followed by the analysis of the loss of the rectifier and coils and the H-field for induced voltage and current. Both linear and nonlinear models for the analysis are presented. Based on the procedure, an experimental power link is implemented with an overall efficiency of 67% at the optimal distance of 7 mm between the coils. In addition to the coil design methodology, we are also presenting a closed-loop control of Class-E amplifier for any duty cycle and any value of the systemQ.     

A common-gate switched 0.9-W class-E power amplifier with 41% PAEin 0.25-μm CMOS

A power amplifier for wireless applications has been implemented in a standard 0.25-μm CMOS technology. The power amplifier employs class-E topology to exploit its soft-switching property for high efficiency. The finite dc-feed inductance in the class-E load network allows the load resistance to be larger for the same output power and supply voltage than that for an RF choke. The common-gate switching scheme increases the maximum allowable supply voltage by almost twice from the value for a simple switching scheme. By employing these design techniques, the power amplifier can deliver 0.9-W output power to 50-Ω load at 900 MHz with 41% power-added efficiency (PAE) from a 1.8-V supply without stressing the active devices     

A 1.9-GHz, 1-W CMOS class-E power amplifier for wirelesscommunications

This paper presents a 1-W, class-E power amplifier that is implemented in a 0.35-μm CMOS technology and suitable for operations up to 2 GHz. The concept of mode locking is used in the design, in which the amplifier acts as an oscillator whose output is forced to run at the input frequency. A compact off-chip microstrip balun is also proposed for output differential-to-single-ended conversion. At 2-V supply and at 1.98 GHz, the power amplifier achieves 48% power-added efficiency (41% combined with the balun)     

System-level evaluation of dynamic effects in a GaN-based class-E power amplifier

Gallium Nitride shows huge potential in power electronics applications thanks to the superior intrinsic material properties which result in improved performance both at device level and system level. Great effort has been taken in recent years to industrialize GaN technology and to solve some of the major drawbacks like reliability issues and dynamic effects. The goal of this work is to propose a novel methodology to analyse the role of these phenomena on the end application efficiency. These insights can thus lead to a system-level driven optimization of GaN technology. We propose a method based on T-CAD mixed-mode simulation and we give an example of its implementation in the analysis of a class-E power amplifier for wireless power transfer. Efficiency curve is extracted for different load resistance values. This is carried out for the device both in relaxed and in stressed conditions to evaluate the impact of buffer traps. It is demonstrated how the main degradation resides in the increased dynamic resistance while threshold voltage shift and output capacitance variations both play a minor role. A method to calculate the dynamic resistance evolution during the switching cycles is then outlined. At the design point the resistance is expected to fully recover to the nominal value.     

Demonstration of 13.56-MHz class-E amplifier using a high-Voltage GaN power-HEMT

A 13.56-MHz class-E amplifier with a high-voltage GaN HEMT as the main switching device is demonstrated to show the possibility of using GaN HEMTs in high-frequency switching power applications such as RF power-supply applications. The 380-V/1.9-A GaN power HEMT was designed and fabricated for high-voltage power-electronics applications. The demonstrated circuit achieved the output power of 13.4 W and the power efficiency of 91% under a drain-peak voltage as high as 330 V. This result shows that high-voltage GaN devices are suitable for high-frequency switching applications under high dc input voltages of over 100 V.     

Design of a divide-by-N asynchronous odd-number counter with 50/50 duty cycle

Methods of designing an asynchronous divide-by-N odd-number counter with 50/50 duty-cycle output are presented. The counter can be implemented by an EXCLUSIVE OR gate associated with a divide-by-(N + 1)/2 counter and a flip-flop, or by the combination of EXCLUSIVE OR gates and flip-flops.     

Study on RZ-4PAM downstream signals with duty cycles of 33% and 50% for optical access system application

4-ary pulse amplitude modulation (4PAM) signals with 33% and 50% return-to-zero (RZ) clocks are generated for passive optical network (PON). We demonstrate that RZ-4PAM signals with duty cycles of 33% and 50% after transmission over 20-km-long single mode fiber (SMF) at 10 Gbit/s can be directly detected by using one photo detector, and the original data can also be restored by one M-ary threshold detector and one 4PAM sequence decoder. The optical spectra of 33% and 50% RZ-4PAM signals are measured, and their eye-diagrams before and after transmission are also analyzed. Simulation results show that 33% and 50% RZ-4PAM downlink signals can be received effectively, and the received power values are ?15.1 dBm and ?13.8 dBm when the bit error rate (BER) is 10-6. Moreover, 33% RZ-4PAM optical signals have better reception performance than 50% RZ-4PAM optical signals.     

Design and operation of a floating gate amplifier

A unique amplifier configuration is examined that fully exploits the intrinsically high signal-to-noise performance of charge-coupled devices (CCD's). In this amplifier, the signal charge is detected with a conducting `floating gate' embedded in the oxide between a bias electrode and the silicon substrate. The change of voltage on the floating gate produced by the signal charge in the CCD channel is then used to modulate the current flow in a metal-oxide-semiconductor (MOS) transistor. The signal charge remains isolated and can be moved downstream in the CCD channel; thus, it can be detected again by other similar structures. Computer analysis, test structure design, and experimental results of a floating gate amplifier (FGA) are presented.     

纯数字时钟50%占空比调节电路设计

利用数控延迟线原理和脉冲电路特性设计实现了一种纯数字方式的高性能时钟50%占空比调节电路FD-DCC (Full-Digital Duty-Cycle Corrector ),不包括任何反馈环路,可产生无偏时钟.经0.13 μm工艺版图实现后的SPICE模拟表明,该电路在200～400 MHz频率范围内工作稳定,对占空比在10%～90%范围内的畸变时钟能进行高精度的调节,输出时钟占空比为50%±2%,且输出时钟和原始时钟间相位偏差较小.     

A design procedure for monolithic matrix amplifier

A procedure for the design of monolithic matrix amplifier is proposed. A simplified expression for small signal gain based on unilateral field-effect transistor (FET) model is derived. In particular, the Design-Oriented FET model previously published is adopted. The introduction of a set of design charts allows the designer a fast and accurate prediction of low frequency gain and 3-dB cutoff frequency of a given matrix amplifier. Good agreement with experimental data and simulations confirms the validity of the proposed design method