基于深度学习的航空对地小目标检测

针对航拍图像中对地小目标识别率低、定位效果差的问题,提出了一种基于深度学习的目标检测算法。该算法利用VGG16网络作为微调网络,并添加部分深层网络,通过提取目标浅层特征与深层特征进行联合训练,克服检测过程中定位与识别相互矛盾的问题。提出把奇异值分解技术应用于卷积特征压缩处理,降低模型的计算与存储需求,并且采用多尺度训练方法以适应航空目标尺度的变化。实验结果表明,在通用数据集PASCAL上可以实现0.76mAP,检测速度达16fps,在专用航空目标数据集UCAS-AOD上可以实现0.63mAP,检测速度达18fps。基本满足对小目标检测精确度的要求,并且检测速度可以接近实时检测效果。     

基于深度学习的目标检测算法研究进展

目标检测是指在视频或图片序列中把感兴趣的目标与背景区分,是在图像中确定目标是否存在且确定目标位置的过程,是计算机视觉领域中的主要研究方向.目标检测主要应用于人脸识别、无人驾驶、指控和安防等领域,起到人工智能赋能传统应用的作用.目标检测的核心是算法.目前,目标检测算法主要分为两大类,第一类是基于手工设计特征的传统算法,第...     

基于深度学习的目标检测研究综述

目标检测是计算机视觉领域内的热点研究课题,在医疗、监控及航空等领域都有广泛应用。先对目标检测技术的背景进行了介绍,然后从基于锚框的两阶段目标检测算法、基于锚框的单阶段目标检测算法、基于Anchor Free的目标检测算法三个阶段分别进行介绍,同时还介绍了主流的数据集以及主要的性能评价指标。最后叙述了当前目标检测领域存在的挑战,展望了目标检测技术在未来的发展方向。     

基于深度学习的通用目标检测研究综述

目标检测是计算机视觉领域中最基础且最重要的任务之一,是行为识别与人机交互等高层视觉任务的基础.随着深度学习技术的发展,目标检测模型的准确率和效率得到了大幅提升.与传统的目标检测算法相比,深度学习利用强大的分层特征提取和学习能力使得目标检测算法性能取得了突破性进展.与此同时,大规模数据集的出现及显卡计算能力的极大提高也促...     

基于计算机视觉的无人机目标检测算法综述

随着人工智能的发展浪潮,计算机视觉得到了飞速发展,利用基于深度学习的卷积神经网络可以较为快速的实现目标检测.本文基于无人机领域目标检测现状的难点,通过对目标检测相关算法研究发展进行概优缺点分析,最后阐述了近期无人机对已存在问题的相关前沿研究.综合来看,目标检测相关算法对于自然图像的处理完全契合了无人机发展的基本要求.     

基于CNN分类器和卷积的目标检测

随着机器视觉领域的研究进展和多媒体技术的迅猛发展,目标检测成了机器视觉研究方向的一个热门领域。在一张图片中,如何寻找某类特定的目标是一个十分值得研究的课题,并且具有优秀性能的算法可以用在十分广阔的领域中,比如视频中的行人、车辆检测等。文中提出了一个基于卷积神经网络的深度学习分类器和卷积的方法,该方法性能优良,漏报率较低,可以快速检测出图片中的某类目标。并且通过以行人检测为例的实验证明,甚至与传统的检测相比鲁棒性更好,速度更快,可以更好地确定标的位置。     

基于双目视觉的三维目标检测算法研究

随着无人驾驶技术的革新与发展,三维目标检测技术进入了大众的视野,相比于传统的基于激光雷达和基于单目的三维目标检测算法,基于双目视觉的检测技术具有更高的性价比,但是其检测效果仍待提高.因此,本文提出一种基于改进立体区域卷积神经网络(Stereo Region Convolutional Neural Network,St...     

A high speed programmable focal-plane SIMD vision chip

A high speed analog VLSI image acquisition and low-level image processing system is presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Each pixel include a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A 64 × 64 pixel proof-of-concept chip was fabricated in a 0.35 μm standard CMOS process, with a pixel size of 35 μm × 35 μm. The chip can capture raw images up to 10,000 fps and runs low-level image processing at a framerate of 2,000–5,000 fps.     

A machine vision system for high speed object tracking using a moments algorithm

A system has been developed for tracking the motion of objects in two dimensions in real-time. The system consists of a conventional CCD camera linked to a transputer-based frame grabber and an array of nine transputers. A parallel moments algorithm is used to extract the co-ordinates of the object's centre of gravity and orientation at field rate, i.e. 60 Hz. Since the position data are made available in real-time—with a small time delay—the system has the potential for inclusion in a feedback loop. Results are presented for tracking the trajectory of a chocolate bar diverted by an air jet. The potential of the system for higher sampling rates—up to 200 Hz—is discussed.     

硬件检索机芯片

在当前飞速发展的信息时代,随着信息量不断爆炸性增长,对信息的快速检索也提出了更高的要求。现在,单片半导体存储器的容量已达到了G位,单个硬盘的容量已超过了百G字节,基本保证了对大数据量信息存储的要求。但如何从海量存储器中快速地检索到需要的信息,这也就成为了一个严峻的课题。     

一种实时多尺度目标检测识别算法

无人机目标检测与识别任务中,目标随着飞行高度的改变尺寸发生显著变化。常规目标检测模型中,获取的小目标细节信息有限,检测精度较低;而适用于小目标的实时检测模型往往容易丢失大目标的背景信息,降低大目标的检测精度。针对以上多尺度目标检测识别任务难点,提出一种基于改进特征金字塔网络(Feature Pyramid Network, FPN)结构的实时多尺度目标检测识别模型。该模型通过增加特征金字塔层级覆盖更广的目标尺度,获取更为丰富的目标信息;同时,利用跨连接增加不同尺度特征融合的多样性,降低特征传导距离,保留更加完整的尺度特征来提高模型检测识别多尺度目标的性能。通过实验发现,相比于原始网络结构和相同特征层级的四层特征金字塔结构,加入改进特征金字塔结构的多尺度目标检测模型识别性能得到了提升。     

Mixed signal SIMD processor array vision chip for real-time image processing

A prototype vision chip has been designed that incorporates a 20 × 64 array of processing elements on a 31 μm pitch. Each processor element includes 14 bits of digital memory in addition to seven analogue registers. Digital operands include NOR and NOT with operations of diffusion, subtraction, inversion and squaring available in the analogue domain. The cells of the array can be configured as an asynchronous propagation network allowing operations such as flood filling to occur with times of ~1 μs across the array. Exploiting this feature allows the chip to recognise the difference between closed and open shapes at 30,000 frames per second. The chip is fabricated in 0.18 μm CMOS technology.     

A programmable CORDIC chip for digital signal processingapplications

A chip implementing the coordinate rotation digital computer (CORDIC) algorithm is described. It contains a 10-MHz 16-b fixed-point CORDIC arithmetic unit, 2-kb RAM, a controller, and input/output (I/O) registers. A modified data-path architecture allows cross-wire free data flow. The chip design involved development of optimized carry-select adders and a modified programmable-logic-array (PLA) cell layout, which allows speed increase in single-layer metal technology. The authors designed, fabricated, and tested a general-purpose fully parallel programmable CORDIC chip in CMOS technology and developed optimal iteration sequences     

A programmable analog neural network chip

A generic chip is implemented in CMOS to facilitate studying networks by building them in analog VLSI. By utilizing the well-known properties of charge storage and charge injection in a novel way, the authors have achieved a high enough level of complexity (>10³ weights and 10 bits of analog depth) to be interesting, in spite of the limitation of a modest 6.00×3.5-mm² die size required by a multiproject fabrication run. If the cell were optimized to represent fixed-weight networks by eliminating weight decay and bidirectional weight changes, the density could easily be increased by a factor of 2 with no loss in resolution. Once a weight change vector has been written to the RAM cells, charge transfers can be clocked at a rate of 2 MHz, corresponding to peak learning rates of 2×10⁹ weight changes/second and exceeding the throughput of `neural network accelerators' by two orders of magnitude     

A real-time programmable switched-capacitor filter

Four independent real-time programmable switched-capacitor filters have been fabricated on a single NMOS chip. The filters are second-order sections with digitally programmable Q and center frequency. Either low-pass or bandpass functions are available by selecting the appropriate input. The device is microprocessor compatible and includes permanent programming capability as well as an on-chip oscillator. The circuit implementation, programming capability, and operation are described.     

A new semi-flat architecture for high speed and reduced area CORDIC chip

In this contribution we present a new CORDIC architecture called ‘semi-flat’ which reduces considerably the latency time and the amount of hardware. In our semi-flat architecture the first rotations are executed with an unfolded scheme but the remaining iterations are flattened using a fast redundant addition tree. Detailed comparisons with other major contributions show that our semi-flat redundant CORDIC is 30% faster and occupy 39% less silicon area.     

A programmable microsystem using system-on-chip for real-time biotelemetry

A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm x 5 mm silicon chip using a 0.6 microm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm x 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10(-3) using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power.