Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors

Using a fluorinated high-k/metal gate stack combined with a stress relieved preoxide (SRPO) pretreatment before high-k deposition, we show significant device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem, and performance degradation for high-fc is a concern. The novel fluorinated Ta_infinC_y/HfZrO_infin/SRPO gate stack device exceeds the positive-bias-temperature-instability and negative-bias-temperature-instability targets with sufficient margin and has electron mobility at 1 MV/cm comparable to the industrial high-quality polySi/SiON device on bulk silicon.     

Negative Bias Temperature Instability Dominated Degradation of Metal-Induced Laterally Crystallized p-Type Polycrystalline Silicon Thin-Film Transistors

Device degradation of solution-based metal-induced laterally crystallized p-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) is studied under dc bias stresses. While typical negative bias temperature instability (NBTI) or electron injection (EI) is observed under $-V_{g}$ or $-V_{d}$ only stress, respectively, no typical hot carrier (HC) degradation can be identified under high $-V_{d}$ stress combined with either low or high $-V_{g}$ stress. Instead, mixed NBTI and EI degradation is observed under combined low $-V_{g}$ and $-V_{d}$ stresses; and combined degradation of NBTI and HC occurs under high $-V_{d}$ and moderate $-V_{g}$ stresses. NBTI is the dominant mechanism in both cases. Grain boundary (GB) trap generation is found to correlate with the NBTI degradation with the same time exponent, suggesting the key role of GB trap generation in poly-Si TFTs' degradation.      

低温金属诱导横向晶化多晶硅材料和器件技术

使用金属镍诱导非晶硅晶化(MIC:metal-induced crystallization)技术,获得了低温(＜550℃)多晶硅.通常在镍覆盖区以外的晶化硅更加有用,这一技术被称为金属诱导横向晶化(MILC:metal-induced lateral crystallization)技术.通过对结晶动力学过程和材料特性的研究,提出了可同时适用于镍覆盖区和相连非覆盖区金属诱导结晶的同一晶化机制.虽然MILC多晶硅的材料特性明显优于固相晶化多晶硅的材料特性,薄膜晶体管沟道中存在MIC/MILC 的界面所形成的横向晶界会明显的降低其性能.若将这些界面从沟道中去除掉,即可获得可满足液晶和有机发光二极管等显示器进行系统集成所需的高性能器件.     

金属单向诱导横向晶化激光修饰多晶硅薄膜晶体管

对采用金属诱导单一方向横向晶化(metal induced unilaterally crystallization,MIUC)并结合激光后退火技术,以提高多晶硅薄膜晶体管的性能,进行了深入研究.MIUC薄膜晶体管已具有良好的器件性能和均匀性,再加以三倍频YAG激光退火后的MIUC薄膜晶体管,其场效应迁移率则可提高近一倍.器件的多种性能和参数的均匀性与所用修饰性的激光处理条件密切相关,具有规律性,故而是可控的,这为工业化技术的掌控提供了基础.     

Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

The authors have proved that negative bias temperature instability (NBTI) is an important reliability issue in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The measurements revealed that the threshold-voltage shift is highly correlated to the generation of grain-boundary trap states. Both these two physical quantities follow almost the same power law dependence on the stress time; that is, the same exponential dependence on the stress voltage and the reciprocal of the ambient temperature. In addition, the threshold-voltage shift is closely associated with the subthreshold-swing degradation, which originates from dangling bond formation. By expanding the model proposed for bulk-Si MOSFETs, a new model to explain the NBTI-degradation mechanism for LTPS TFTs is introduced     

The Electrical Properties of Unidirectional Metal-Induced Lateral Crystallized Polycrystalline-Silicon Thin-Film Transistors

It has been known that adjacent Pd enhances the crystallization rate in Ni metal-induced lateral crystallization (Ni-MILC) and this knowledge has been used to fabricate the unidirectional MILC thin-film transistors (TFTs), which eliminate the boundary formed at the center of TFT channel in a normal MILC TFTs. It is discovered that the MILC/MILC boundary (MMB) is responsible for the high leakage current and low field- effect mobility. The electrical properties of unidirectional MILC TFTs (Width/Length = 10/10 mum) improved considerably comparing to those of MILC TFTs containing the MMB. The leakage current and field-effect mobility, which have been regarded as obstacles for industrialization of the MILC process, measure to be 2.1 X 10-11 A and 83 cm²/ V ldr s, respectively.     

Plasma Damage-Enhanced Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

In this letter, a mechanism that will make negative bias temperature instability (NBTI) be accelerated by plasma damage in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is presented. The experimental results confirm that the mechanism, traditionally found in the thin gate-oxide devices, does exist also in LTPS TFTs. That is, when performing the NBTI measurement, the LTPS TFTs with a larger antenna ratio will have a higher degree in degradation of the threshold voltage, effective mobility, and drive current under NBTI stress. By extracting the related device parameters, it was demonstrated that the enhancement is mainly attributed to the plasma-damage-modulated creating of interfacial states, grain boundary trap states, and fixed oxide charges. It could be concluded that plasma damage will speed up the NBTI and should be avoided for the LTPS TFT circuitry design     

Analysis of Negative Bias Temperature Instability in Body-Tied Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Negative bias temperature instability (NBTI) degradation mechanism in body-tied low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is analyzed by the charge-pumping (CP) technique. The properties of bulk trap states (including interface and grain boundary trap states) are directly characterized from the CP current. The increase of the fixed oxide charges is also extracted, which has not been quantified in previous studies of NBTI degradation in LTPS TFTs. The experimental results confirm that the NBTI degradation in LTPS TFTs is caused by the generation of bulk trap states and oxide trap states.     

The Characteristics of New n-Type Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n⁺ amorphous silicon (n⁺ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (V_TH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm²/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P⁺ ions) in the channel reduced the V_TH and increased the S value.     

Stress-Induced Hump Effects of p-Channel Polycrystalline Silicon Thin-Film Transistors

Positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated. The stress-induced hump in the subthreshold region is observed and is attributed to the edge transistor along the channel width direction. The electric field at the corner is higher than that at the channel due to thinner gate insulator and larger electric flux density at the corner. The current of edge transistor is independent of the channel width. The electron trapping in the gate insulator via the Fowler–Nordheim tunneling yields the positive voltage shift. As compared to the channel transistor, more trapped electrons at the edge lead to more positive voltage shift and create the hump. The hump is less significant at high temperature due to the thermal excitation of trapped elections via the Frenkel–Poole emission.      

A Reliability Model for Low-Temperature Polycrystalline Silicon Thin-Film Transistors

We proposed here a reliability model that successfully introduces both the physical mechanisms of negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed model is highly matched with the experimental results, in which the NBTI dominates the device reliability at small negative drain bias while the HCS dominates the degradation at large negative drain bias. In summary, the proposed model provides a comprehensive way to predict the lifetime of the p-channel LTPS TFTs, which is especially necessary for the system-on-panel circuitry design.      

Dynamic Negative Bias Temperature Instability (NBTI) of Low-Temperature Polycrystalline Silicon (LTPS) Thin-Film Transistors

The dynamic negative bias temperature instability (NBTI) on low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) was investigated in detail. Experimental results revealed the threshold voltage shift of LTPS TFTs after the NBTI stress decreases with increasing frequency, which is different from the frequency-independence of conventional CMOSFET. Under a low frequency stress, the capacitance-voltage measurement with various frequencies implied that a larger quantity of inversion holes was trapped in the grain boundary. Thus, the difference of the transit time between the grain boundary and interface dominates the LTPS TFTs dynamic NBTI behaviors and results in the dependence of frequency.     

Stability of Amorphous-Silicon and Nanocrystalline Silicon Thin-Film Transistors Under DC and AC Stress

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated using hydrogenated amorphous-silicon (a-Si:H)/ nanocrystalline silicon (nc-Si:H) bilayers as channel materials, which are deposited by plasma-enhanced chemical vapor deposition at low temperatures. The stability of these devices is investigated under static and dynamic bias stress conditions. For comparison, the stability of a-Si:H and nc-Si:H single-layer TFTs is investigated under similar bias stress conditions. The overall results demonstrate that the a-Si:H/nc-Si:H bilayer TFTs are superior compared with their counterparts of a-Si:H and nc-Si:H TFTs regarding device performance and stability.     

高性能金属诱导单向横向晶化多晶硅薄膜晶体管技术和应用

低温金属单向诱导横向晶化多晶硅薄膜晶体管技术与常规的固相晶化多晶硅薄膜晶体管相比，制作工艺简单，而且提高了场效应迁移率和漏极击穿电压，降低了漏电电流，改进了器件参数空间分布的均匀性。我们使用金属单向诱导横向晶化多晶硅薄膜晶体管技术，成功地制作了有源矩阵液晶显示器和有源矩阵有机发光二极管显示器。     

High-Performance Metal-Induced Laterally Crystallized Polycrystalline Silicon P-Channel Thin-Film Transistor With $hbox{TaN/HfO}_{2}$ Gate Stack Structure

In this letter, high-performance low-temperature poly-Si p-channel thin-film transistor with metal-induced lateral- crystallization (MILC) channel layer and TaN/HfO₂ gate stack is demonstrated for the first time. The devices of low threshold voltage V_TH ~ 0.095 V, excellent subthreshold swing S.S. ~83 mV/dec, and high field-effect mobility mu_FE ~ 240 cm²/V ldr s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate-capacitance density provided by HfO₂ gate dielectric with the effective oxide thickness of 5.12 nm.     

Performances of a Capacitorless 1T-DRAM Using Polycrystalline Silicon Thin-Film Transistors With Trenched Body

Polycrystalline silicon thin-film transistors (TFTs) can be improved by integrating DRAM on chip. However, the TFT's poor capacitance means that traditional DRAMs are infeasible, because they require a capacitor. An alternative, the one-transistor DRAM (1T-DRAM), is promising because it avoids the capacitor by instead storing the logical value as holes trapped in the body region. This letter proposes the use of a trenched body in a TFT to construct a 1T-DRAM. Previously, we have shown that a trenched body reduces the leakage current of a TFT. In this letter, we now show that the trenched-body TFT also works well as a 1T-DRAM device. It has a strong back-gating effect and a programming window that is more than twice as large as that of the conventional TFT.      

A Reduced Mask-Count Technology for Complementary Polycrystalline Silicon Thin-Film Transistors With Self-Aligned Metal Electrodes

The inexpensive glass substrate for building conventional low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) imposes a ceiling on the TFT processing temperature. This results in a reduced efficiency of dopant activation and a high source/drain series resistance. A technique based on aluminum-induced crystallization of amorphous silicon has been applied to fabricate TFTs with low-resistance self-aligned metal electrodes (SAMEs). While at least two masked implantation steps are typically used for constructing the doped source and drain regions of conventional n- and p-channel TFTs in a complementary metal–oxide–semiconductor circuit technology, it is currently demonstrated that complementary SAME poly-Si TFTs can be constructed using a combination of a masked and a blanket source and drain implantation steps. The decrease in mask count reduces process complexity and cost. Control of ion channeling is the enabling factor behind the successful demonstration of the technology.      

基于溶液法的金属诱导碟型晶畴多晶硅薄膜和薄膜晶体管的研究

以非晶硅为晶化前驱物,采用镍盐溶液浸沾的方法可以得到超大尺寸碟型晶畴结构的低温多晶硅薄膜.所得多晶硅薄膜的平均晶畴尺寸大约为50 μm,空穴的最高霍尔迁移率为30.8 cm~2/V·s,电子的最高霍尔迁移率为45.6 cm~2/V·s.用这种多晶硅薄膜为有源层,所得多晶硅TFT的场效应迁移率典型值为70～80 cm~2 /V·s,亚阈值斜摆幅为1.5 V/decade,开关电流比为1.01×10~7,开启电压为-8.3 V.另外,P型的TFT在高栅偏压和热载流子偏压下具有良好的器件稳定性.     

Thermal Degradation Under Pulse Operation in Low-Temperature p-Channel Poly-Si Thin-Film Transistors

We analyzed the heat generation of a low-temperature polycrystalline thin-film transistor in pulse operation and proposed a technique for accurately measuring its thermal temperature in high-frequency operation. From this measurement, we were able to calculate the time constants for heating and radiation for the first time. At a low frequency, the temperature difference between when the pulse was on and off was remarkable. As the frequency was increased, the maximum and minimum temperatures approached each other and became equal at a frequency of approximately 1 kHz. We also measured the degradation in pulse operation and discussed the relationship between the thermal temperature and the degradation in the pulse operation