一种高压集成电路工艺的抗辐射加固

承接了一项对AT&T公司现有的功率集成电路工艺(BCDMOS)从总剂量、γ剂量率、SEU和中子四方面进行核加固的研究课题。研究工作的重点是加固和优化我们的CMOS、DMOS和npn器件。初步的结果表明,抗核强度比我们原有的商品化产品工艺大大提高。     

基于全集成自提取结终端隔离BCD新工艺的场致发光高压驱动芯片

本文提出可集成自提取结终端的0.35μm 150V-BCD （双极-互补金属氧化物半导体-双重扩散金属氧化物半导体）全套新型高压工艺．利用此工艺研制出100V场致发光用高低侧驱动芯片,并提出了基于双极器件BC （双极集电极）结短路自提取结终端新工艺与新结构,既可满足场致发光高压驱动芯片应用,又能取代传统采用氧化扩散工艺的P-ISO （P型隔离结构）传统隔离结构,显著简化了工艺和提高了芯片的高集成度,确保片内集成的低电阻率VDN-MOS/LDPMOS （N型垂直双扩散金属氧化物半导体场效应晶体管/P型横向扩散金属氧化物半导体场效应晶体管）高压驱动模块与低压逻辑控制模块在100V高压脉冲交替工作状况下无负电位、EMMI （微光显微镜）等寄生现象出现．     

一种高线性度CMOS混频器的设计

采用线性化技术改进的混频器结构提高了线性度.采用TSMC 0.18 μm RF CMOS模型进行了电路仿真.仿真结果:在电源电压为1.8 V时,输入三阶截断点(IIP3)为10.3 dBm,输入1dB压缩点(P-1dB)为-3.5 dBm,增益为9.2 dB,单边带噪声系数为17 dB.     

一种抗辐射加固RS485驱动器的设计

RS485通信协议要求：RS485驱动器输出短路至-7~12 V时,短路电流应小于250 mA。常规短路保护电路采用高压MOS实现,由于高压MOS栅极氧化层厚度很大,无法满足抗总剂量辐射加固的要求。提出了一种新型的驱动器输出短路保护电路,该电路利用5 V低压MOS管实现,通过合理设计线路、版图,实现了良好的短路保护效果和抗总剂量辐射能力。电路采用0.8 μm SOI CMOS工艺设计实现,常规及辐照测试结果证明了设计的正确性。     

一种PDP扫描驱动芯片的HV-PMOS的研究和实现

对一种适用于106.68cm PDP扫描驱动IC的HV-PMOS器件进行了分析研究。通过使用TCAD软件对HV-PMOS进行了综合仿真,得到了器件性能最优时的结构参数及工艺参数。HV-PMOS器件及整体扫描驱动IC在杭州士兰集成电路公司完成流片。PCM(Process control module)片上的HV-PMOS击穿电压达到了185V,阈值为6.5V。整体扫描驱动芯片的击穿电压达到了180V,满足了设计要求。     

一种BiCMOS高速、低压、低功耗全摆幅单元电路技术

提出了一种具有高速全摆幅输出的BiCMOS缓冲器逻辑单元.该单元可以工作于1.5V,并且易于实现多输入扩展.     

一种抗辐射LVDS驱动电路IP设计

低压差分信号(Low Voltage Differential Signaling,LVDS)在航天通讯领域有着广泛的应用,为解决LVDS驱动器电路在宇宙辐射环境中的单粒子闩锁和总剂量问题,给出了低成本抗辐射解决方案,提出了一种改进结构的抗辐射加固技术,不仅解决了现有工艺下带隙基准电路的温漂问题,而且还可以利用设计的抗辐射单元库来满足抗辐射加固要求,简化了电路设计。基于0.18μm CMOS工艺模型库,利用Hspice进行仿真,该电路传输速率达到400 Mb/s,具有抗单粒子特性,满足航空航天领域对抗辐射LVDS驱动电路的使用要求。     

研诺推出同类中阻抗最低的半桥MOSFET驱动器

研诺逻辑科技最新推出的AAT4910支持电压高达28V，其半桥双金属氧化物半导体场效应管（MOSFET）驱动器可提供业界同类多相DC—DC转换器中的最低阻抗。     

一种新型的神经元激活函数及其导数的可编程发生器

在神经网络的片上学习中 ,需要将神经元激活函数及其导数都映射为硬件。为满足这种需求 ,利用前向差分的原理 ,提出了一种新型的神经元激活函数及其导数的可编程发生器。该发生器采用模拟电路 ,具有结构简单、速度快、功耗小的优点。它产生的函数不仅与理想函数的拟合程度很好 ,而且可对阈值和增益因子进行编程 ,从而克服了一般模拟电路可编程性差、适用范围窄的缺点。采用标准 1 .2μm CMOS工艺的第 47级模型 ,对电路进行的 HSPICE模拟结果表明该发生器性能优越     

基于130nm PD-SOI工艺存储单元电路的抗辐射加固设计

基于130 nm部分耗尽绝缘体上硅(SOI) CMOS工艺,设计并开发了一款标准单元库.研究了单粒子效应并对标准单元库中存储单元电路进行了抗单粒子辐射的加固设计.提出了一种基于三模冗余(TMR)的改进的抗辐射加固技术,可以同时验证非加固与加固单元的翻转情况并定位翻转单元位置.对双互锁存储单元(DICE)加固、非加固存储单元电路进行了性能及抗辐射能力的测试对比.测试结果显示,应用DICE加固的存储单元电路在99.8 MeV ·cm2 ·mg_1的线性能量转移(LET)阈值下未发生翻转,非加固存储单元电路在37.6 MeV·cm2·mg_1和99.8 MeV·cm2·mg_1两个LET阈值下测试均发生了翻转,试验中两个版本的基本单元均未发生闩锁.结果证明,基于SOI CMOS工艺的抗辐射加固设计(RHBD)可以显著提升存储单元电路的抗单粒子翻转能力.     

A dual high-current high-voltage driver

A high-current driver which can control two independent 1.6-A, 20-V loads is described. Inductively-induced flyback voltage transients are clamped internally to safe voltages, for inductance values up to 80 mH. Short-circuit load conditions are tolerated and controlled     

A 475-V high-voltage 6H-SiC lateral MOSFET

High-voltage lateral MOSFET's on 6H- and 4H-SiC have been fabricated with 400-475 V breakdown voltage using the RESURF principle. An MOS electron inversion layer mobility of about 50 cm²/V-s is obtained on 6H-SiC wafers. This mobility is high enough such that the specific on-resistance of the 6H-SiC MOSFET's (~0.29-0.77 Ω-cm²) is limited by the resistance of the drift layer, as desired. However, the implanted drift layer resistance is about ten times higher than expected for the implant dose used. Design and process changes are described to decrease the on-resistance and increase the breakdown voltage. For 4H-SiC, extremely low mobility was obtained, which prevents satisfactory device operation     

A monolithic low-power high-voltage driver for bistable LCDs

A complete low-power high-voltage driver for a 80×104 passive-matrix bistable LCD is integrated in a 0.7 μm CMOS smart-power technology. It features 100 V driving capability on all row and column outputs and comprises all necessary digitally programmable high-voltage generators and multiplexers to synthesize the required complex high-voltage waveforms from a 3 V battery. An original level-shifter design for the high-voltage multiplexers and a dedicated architecture for the programmable high-voltage generators yield an extremely low internal power consumption below 10 mW for the entire driver chip.     

A resonant MOSFET gate driver with efficient energy recovery

High frequency pulse-width modulation (PWM) converters generally suffer from excessive gate drive loss. This paper presents a resonant gate drive circuit that features efficient energy recovery at both charging and discharging transitions. Following a brief introduction of metal oxide semiconductor field effect transistor (MOSFET) gate drive loss, this paper discusses the gate drive requirements for high frequency PWM applications and common shortcomings of existing resonant gate drive techniques. To overcome the apparent disparity, a new resonant MOSFET gate drive circuit is then presented. The new circuit produces low gate drive loss, fast switching speed, clamped gate voltages, immunity to false trigger and has no limitation on the duty cycle. Experimental results further verify its functionality.     

A novel high-performance asymmetric hetero-doped S/D high-voltage MOSFET

A novel high-voltage MOSFET structure, using a simple yet effective concept of an asymmetric hetero-doped source/drain (S/D) is proposed. The asymmetric hetero-doped S/D reduces the on-state resistance of the transistor due to the high doping used for device drain drift, provides excellent ruggedness for parasitic NPN turned-on due to a minimized n/sup +/ source spacer, and also raises the device breakdown voltage due to charge compensation in the composite drain drift region. Therefore, the asymmetric hetero-doped S/D structure allows the high voltage MOSFET to have a high current handling capability with a small device size. This in turn causes the R (sp, on) to be low, leading to high performance for the power device when used in a power integrated circuit. Measured results show that a 24-V breakdown voltage new device with a low-cost two-layer metal (Al) back-end achieves very low R (sp, on) of 0.166 m/spl Omega//spl middot/cm/sup 2/. Furthermore, the new device with a 65-V high-side capability achieves good isolation performance even when switching S/D to -20 V and also gets a cutoff frequency of 13 GHz at a gate voltage of 5.5 V.     

用作超快速离子偏转板驱动器的MOSFET

图1所示的电路可在实验仪器中的一组大容量离子偏转板上提供20MHz方波。为了获得所需的偏转量,偏转板电压必须达到20～30V,远大于普通逻辑电路系列或驱动器系列所能提供的电压。为了减小人为寄生信号,上升时间和下降时间必须极短,过冲和波动最小。驱动偏转板的是两个相位相差180°的相同电路。这一驱动器使用Directed Energy公     

混合信号微控制器提升车用嵌入式系统

通过网络连接不同系统以分享信息、进行监控及增加安全性,汽车相关应用正日益精进.随着复杂度的提高,车用系统需采用更有效的电子元器件来节省空间,这也意味着印刷电路板(PCB)上的元器件势必越来越少,半导体厂商必须提供整合性与性能都更强的产品,尤其是各种微控制器(MCU).     

Precise macromodel applied to high-voltage power MOSFET

A macromodel for precise simulations of high-voltage power MOSFET is presented. The macromodel takes into account basic features of these devices as higher value of the resistance between channel and drain and lower current level though the body diode compared to low-voltage power MOSFET. It also considers that high-voltage power MOSFET work mostly in saturation regime. All required parameters are extracted from direct electrical measurements. Simulations using this and previous macromodels are compared with experimental DC and AC characteristics to demonstrate a much better correspondence with experiment of the macromodel presented.     

具有宽占空因子范围的隔离式MOSFET驱动器

图1所示电路主要用途是用于驱动频率范围为1 Hz至300 kHz、占空因子为0～100%的功率MOSFET.使用一个无铁芯的印制电路板变压器就可以实现这一目标.大多数功率电子电路的开关频率都在数赫至几百千赫的范围内.为了设计一个开关频率低于300kHZ的无铁芯隔离式变压器的栅极驱动电路,你可以用一个低频控制信号调制一个高频载波.初级的能量可通过使用3 MHz高频载波信号来传送.     

FAN3XXX系列高速低端MOSFET驱动器概述

FAN3XXX系列是飞兆公司 (FAIRCHILD)2007年10月推出的新产品,是一种高速低端MOSFET驱动器系列.该系列各种驱动器与PWM控制器及功率MOSFET组合可设计出各种高频、大功率开关电源.