突发性业务环境下周期性信元流通过ATM复接器的时延抖动

在输入ATM网络的业务源中,周期性信元流是很重要的一种.本文精确地分析了一个有限缓存的ATM复接器,其输入业务源由一路周期性信元流、多路随机性贝努利(Bernoulli)信元流和突发性两状态马尔科夫调制贝努利(MMBP)信元流构成.得出了该路周期性信元流的排队时延分布、时延抖动的自相关函数和功率谱.揭示了突发性业务环境下周期性信元流通过ATM复接器的时延抖动行为.计算机模拟验证了分析结果的正确性.     

PERFORMANCE ANALYSIS OF HETEROGENEOUS TRAFFIC ON AN INTEGRATED NETWORK LINK WITH FINITE WAITING ROOM AND ANTICIPATED-RELEASE RESERVATION POLICY

We consider a system where the superposition of two heterogeneous Poisson traffic streams is offered to an integrated network link in synchronous transfer mode, where one stream follows the blocked-and-cleared mode (‘loss’ mode) and the other can wait (finitely) if bandwidth is not available for connection at the time of arrival (‘hold’ mode). We assume that each stream has different bandwidth requirements per call. A reservation scheme, called anticipated-release policy, is introduced where an arrival is accepted into a waiting room only if the amount of time this customer is expected to wait is within acceptable limits. For such a loss/hold system, we provide analytical performance models for exponential service time distributions for both streams as well as for the non-exponential service time distribution case for the traffic stream in ‘hold’ mode. We also present a method on how to model the waiting time distribution of the traffic stream with ‘hold’ mode. From numerical studies, we observe that blocking can be reduced considerably for both services just by introducing a small waiting room for one traffic class compared to ‘loss’ mode for both traffic classes. Furthermore, this holds true for the case when a maximum tolerable time limit is imposed on the waiting. Finally, our results indicate that this loss/hold scenario with limited waiting room appears to be virtually insensitive to the service time distribution of the ‘hold’ mode traffic.     

含优先级机制的ATM Mux中的信元丢失率分析

含丢失优先级机制的ATM Mux中的信元丢失率分析是ATM网络流量控制研究中的一个重要问题.本文用两状态的MMDP近似实际输入过程,并采用流体流技术对不同优先级信元在ATM Mux中的丢失率进行了分析,得到了各类信元的丢失率与缓冲容量之间关系的解析式.模拟文验表明该方法足够精确,完全可以满足实际应用的需要.     

PERFORMANCE EVALUATION OF NON-BLOCKING ATM SWITCHES UNDER VARIOUS TRAFFIC AND BUFFERING SCHEMES

Broadband integrated services digital networks (BISDN) are designed to offer a variety of services with bit rates ranging from several kb/s (e.g. teleactions) to hundreds of Mb/s (e.g. HDTV), and in some cases approaching Gb/s (e.g. in interconnections of high-speed LANs). A multiplicity of rates and the burstiness of traffic sources lead naturally to systems based on the fast packet switching (or asynchronous transfer mode) concept. The requirements of data buffering and high-speed processing of packet headers have resulted in a plethora of proposals for ATM switching nodes and an equal number of ways for evaluating them. In particular, the class of non-blocking architectures of ATM switches has received the most attention from the research community. This paper reviews this class of architecture with emphasis on contention resolution methods and communication traffic performance. The contention resolution methods are divided into four categories: input buffering, output buffering, shared buffering, and hybrid buffering. The communication traffic characteristics are divided into two categories: uniform traffic and bursty traffic.     

ATM网络中漏桶算法在突发业务输入时的性能分析

本文首先引入了描述分组图像业务的突发业务模型;分析了漏桶算法在突发业务输入时的性能;研究了各参数对业务服务质量的影响。研究结果表明,增大缓冲器容量可以降低信元丢失率,但会增大时延和时延抖动。     

Reducing cell loss in banyan based ATM switching fabrics

In this paper, we propose a new technique for reducing cell loss in multi‐banyan‐based ATM switching fabrics. We propose a switch architecture that uses incremental path reservation based on previously established connections. Path reservation is carried out sequentially within each banyan but multiple banyan planes can be concurrently reserved. We use a conflict resolution approach according to which banyans make concurrent reservation offers of conflict‐free paths to head of the line cells waiting in input buffers. A reservation offer from a given banyan is allocated to the cell whose source‐to‐destination path uses the largest number of partially allocated switching elements which are shared with previously reserved paths. Paths are incrementally clustered within each banyan. This approach leaves the largest number of free switching elements for subsequent reservations which has the effect of reducing the potential of future conflicts and improves throughput. We present a pipelined switch architecture based on the above concept of path‐clustering which we call path‐clustering banyan switching fabric (PCBSF). An efficient hardware that implements PCBSF is presented together with its theoretical basis. The performance and robustness of PCBSF are evaluated under simulated uniform traffic and ATM traffic. We also compare the cell loss rate of PCBSF to that of other pipelined banyan switches by varying the switch size, input buffer size, and traffic pattern. Copyright © 2001 John Wiley & Sons, Ltd.