电子设备的电磁屏蔽研究

依照电磁屏蔽理论，给出几种电磁屏蔽效能的计算方法，同时分析影响电子设备电磁屏蔽效能的主要因素，对实践中一般可能出现的问题给出特殊的屏蔽方法。     

电子设备的屏蔽设计

本文首先介绍了屏蔽的基本原理和分类以及屏蔽效果的表示和计算方法，接着介绍了几种常用的屏蔽结构及屏蔽体开口的影响，进而给出了屏蔽体结构设计原则，最后给出了屏蔽体的安装方法。     

电子设备的电磁屏蔽技术

本文详细讨论了电子设备的电磁屏蔽技术。系统地分析了电子设备电磁屏蔽的技术原理,屏蔽效能的计算方法,各种屏蔽材料的性能和应用场合,屏蔽的各种注意事项,孔眼的屏蔽效能的计算,屏蔽效能的检测以及特殊部位的特殊屏蔽措施。我们应不断地总结经验,以便逐步提高电子设备的电磁屏蔽能力。     

电磁屏蔽玻璃在电磁屏蔽方舱上的应用

文章介绍了电磁屏蔽玻璃国内生产现状、屏蔽效能理论计算方法、几种屏蔽玻璃屏蔽效能的实测值,指出了屏蔽玻璃在电磁屏蔽方舱上的应用原则.     

丝网型衬垫的屏蔽特性研究

屏蔽衬垫已广泛地用于抑制机箱装配面处缝隙所产生的电磁泄漏。从而大大提高了机箱的电磁屏蔽性能。本文利用传输线理论建立了最为常用的丝网型衬垫屏效能的计算方法，分析、研究了影响丝网衬垫屏效的各种因素，所得计算结果与试验结果吻合较好，表明本文所提出的方法是正确的。     

遥控终端的电磁屏蔽设计

本文介绍了遥控终端结构设计中所采用的电磁屏蔽设计方法,其结果满足GJB367A-2001及GJB151A-1997标准对设备电磁兼容性能的要求.     

电磁屏蔽材料的研究进展与展望

针对日益严重的电磁辐射污染,介绍了材料对电磁波的屏蔽实现方式,以及纤维类电磁屏蔽材料、非晶态电磁屏蔽材料和复合屏蔽材料的研究现状和进展,指出目前电磁屏蔽材料的主要存在问题,并展望了未来电磁屏蔽材料的研究前景。     

电子仪器中敏感元器件的屏蔽

电磁屏蔽是电磁兼容技术的主要措施之一,对于电子仪器中的一些敏感元器件或敏感电路,必须采取必要的屏蔽措施进行保护,以提高元器件的抗干扰性和整机的可靠性.本文介绍了电子设备电磁兼容设计中电场屏蔽、磁场屏蔽、电磁屏蔽的机理,着重介绍在电子仪器中对敏感元器件进行有效屏蔽的措施,对屏蔽效能进行了理论分析,并举例说明屏蔽效能的计算方法,最后提出进行此类屏蔽设计的一般方法.     

屏蔽服屏蔽性能测试探讨

从电磁防护用品屏蔽性能影响因素及当前的测试现状出发,提出了屏蔽服屏蔽效能的测试方法。根据源的特性,将测试分为电场屏蔽测试、磁场屏蔽测试和电磁屏蔽测试,并对每种测试的关键点及注意事项进行了分析。     

电子设备的电磁屏蔽技术

本文详细讨论了电子设备的电磁屏蔽技术 ,系统地分析了电子设备电磁屏蔽的技术原理 ,屏蔽效能的计算方法 ,各种屏蔽材料的性能和应用场合 ,屏蔽的各种注意事项 ,孔眼的屏蔽效能的计算 ,屏蔽效能的检测以及特殊部位的特殊屏蔽措施。我们应不断地总结经验 ,以便逐步提高电子设备的电磁屏蔽能力。     

Fully embedded board-level guided-wave optoelectronic interconnects

A fully embedded board-level guided-wave optical interconnection is presented to solve the packaging compatibility problem. All elements involved in providing high-speed optical communications within one board are demonstrated. Experimental results on a 12-channel linear array of thin-film polyimide waveguides, vertical-cavity surface-emitting lasers (VCSELs) (42 μm), and silicon MSM photodetectors (10 μm) suitable for a fully embedded implementation are provided. Two types of waveguide couplers, titled gratings and 45° total internal reflection mirrors, are fabricated within the polyimide waveguides. Thirty-five to near 100% coupling efficiencies are experimentally confirmed. By doing so, all the real estate of the PC board surface are occupied by electronics, and therefore one only observes the performance enhancement due to the employment of optical interconnection but does not worry about the interface problem between electronic and optoelectronic components unlike conventional approaches. A high speed 1-48 optical clock signal distribution network for Cray T-90 super computer is demonstrated. A waveguide propagation loss of 0.21 dB/cm at 850 nm was experimentally confirmed for the 1-48 clock signal distribution and for point-to-point interconnects. The feasibility of using polyimide as the interlayer dielectric material to form hybrid three-dimensional interconnects is also demonstrated. Finally, a waveguide bus architecture is presented, which provides a realistic bidirectional broadcasting transmission of optical signals. Such a structure is equivalent to such IEEE standard bus protocols as VME bus and FutureBus     

Modal analysis of board-level electronic package

The reliability of board-level electronic package subjected to drop impact is one of the most concerned issues. After drop impact, the Printed Circuit Board (PCB) experiences free vibration which leads to the deformation of PCB, hence the failure of solder joints. The free vibration is dependent on the inherent parameters of PCB. So it is necessary to study the inherent parameters of board-level package. Modal analysis is a common way to characterize the inherent dynamic parameters of a system. By modal analysis, we can understand the inherent vibration features of board-level package system. In this paper, the theoretical vibration model of the JEDEC standard PCB assembled with three Chip Size Packages (CSPs) is performed. Then the results of theoretical analysis are validated by that of finite element analysis (FEA) and modal test. A series of modal parameters are obtained during the modal analysis such as the mode shapes, the natural frequencies and the damping ratios. These parameters are useful for studying the dynamic response of PCB and the strain rate of solder joints during drop test. The Modal Assurance Criterion (MAC) value is used to validate the correlation between two modal shapes obtained from two different modal parameters estimation methods during modal analysis. The MAC value is computed for the first two order mode shapes, indicating the high correlation between the experimental and predicted (including theoretical and FE results) mode shapes.     

Novel reworkable fluxing underfill for board-level assembly

Underfills are traditionally applied for flip-chip applications. Recently, there has been increasing use of underfill for board-level assembly including ball grid arrays (BGAs) and chip scale packages (CSPs) to enhance reliability in harsh environments and impact resistance to mechanical shocks. The no-flow underfill process eliminates the need for capillary flow and combines fluxing and underfilling into one process step, which simplifies the assembly of underfilled BGAs and CSPs for SMT applications. However, the lack of reworkability decreases the final yield of assembled systems. In this paper, no-flow underfill formulations are developed to provide fluxing capability, reworkability, high impact resistance, and good reliability for the board-level components. The designed underfill materials are characterized with the differential scanning calorimeter (DSC), the thermal mechanical analyzer (TMA), and the dynamic mechanical analyzer (DMA). The potential reworkability of the underfills is evaluated using the die shear test at elevated temperatures. The 3-point bending test and the DMA frequency sweep indicate that the developed materials have high fracture toughness and good damping properties. CSP components are assembled on the board using developed underfill. High interconnect yield is achieved. Reworkability of the underfills is demonstrated. The reliability of the components is evaluated in air-to-air thermal shock (AATS). The developed formulations have potentially high reliability for board-level components.     

一种面向板级电路的故障注入系统设计

在装备测试性验证过程中,故障注入是一项关键技术。针对于装甲装备测试性设计不足的情况,利用已有实验条件,通过对电路中故障进行分类,设计实现了对应的模拟故障板,对某型坦克炮控系统中的电路板进行了故障注入,用故障检测设备检测到故障的存在,通过分析测试性验证数据,为装备BIT研究以及测试性设计的提高提供了依据。     

Mapping the failure envelope of board-level solder joints

Single solder interconnects were subjected to a series of combined tension-shear and compression-shear tests to determine their failure load. The failure envelope of these interconnects was obtained by plotting the normal component against the shear component of the failure load. The interconnect failure force map was found to be elliptical like the failure envelopes of many materials. The failure map can be described by a simple mathematical expression to give a simple force-based criterion for combine loading of solder joints. Post mortem analyses were conducted on the solder joint specimens to identify the failure mechanisms associated with various segments of the failure map. Computational simulations of actual board tests show that the failure map obtained for joint tests provides good predictions of board-level interconnect failures and hence suggest that such failure maps are useful in the design and analysis of board assemblies subjected to mechanical loads. The industry could adopt the methodology to obtain failure envelopes for solder joints of different alloys, bump size and reflow profiles which they could later use to aid in board-level and system-level designs of their products for mechanical reliability.     

多总线兼容的板级测试系统设计

由于不同板卡的总线接口不同,对板卡的测试也需要多种测试系统,因此成本较高。针对以上问题,设计了一种能兼容多种总线的板级自动化测试系统。介绍了系统的硬件构建方法和工作原理,重点论述了多种总线接口兼容和不同种类信号切换的实现途径。实际应用表明,该系统具有通用性强、速度快、可靠性高等优点。     

Distributed matched bypassing for board-level power distribution networks

Power-distribution networks need to provide impedance response with specified shape/value over a wide frequency band. Bypass capacitors with different values, and capacitors and planes may create resonance peaks, unless the capacitor parameters are selected properly. Distributed matched bypassing (DMB) is suggested to create a smooth impedance profile. DMB requires components with Q/spl Lt/1, which in turn requires user-defined ESR. Different options are shown to set (increase) the ESR of bypass capacitors. The concepts of bypass quality factor (BQF) and bypass resistor (BR) are introduced.     

Evaluation of board-level reliability of electronic packages under consecutive drops

In general, the drop reliability of a board-level electronic package is characterized by the number of drops to failure according to a certain failure criterion. This implies that damage of solder joints evolves during each drop and eventually leads to failure. Development of a numerical method capable of obtaining accumulated stresses and strains under consecutive drop conditions is therefore in need because without these damage factors, accurate predictions for the board-level drop reliability of electronic packages are unattainable. We implement in this paper the support excitation scheme incorporated with the implicit time integration scheme to study transient structural responses of a board-level chip-scale package subjected to consecutive drops. Accumulated stresses, plastic strains, and plastic strain energy densities on the solder joints under repetitive drop impacts are investigated.     

RF interconnect for multi-gbit/s board-level clock distribution

With clock distribution of over 1 GHz, problems associated with clock skew, power consumption, and timing jitter are becoming critical for determining the processing speed of high-performance digital systems, especially for multi-processor systems. Conventional digital clock distribution interconnection has a severe power consumption problem for GHz clock distribution because of the transmission line losses, as well as exhibiting difficult signal integrity problems due to clock skew, clerk jitter and signal reflection. To overcome conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, the optical clock distribution is found to be bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. In this paper, a multi-Gbit/s clock distribution scheme to minimize power consumption, skew, and jitter, based on RF interconnect technology, especially for the medium clock frequency region from 200 MHz to 10 GHz, and interconnection line lengths of from 10 cm to 3 m, is proposed. A quantitative comparison is made between the guided optical, the free-space optical, the conventional digital, and the proposed RF interconnections for board-level clock distribution relative to power consumption and speed. The proposed board-level clock distribution with 32-fan-outs has successfully demonstrated less than 22-ps skew and less than 3-ps jitter at 2 GHz. The estimated power consumption of the clock link for the proposed clock distribution has been shown to be about 320 mW. Furthermore, the proposed clock receiver using the RF clock distribution scheme has demonstrated less than 2-ps dead time and 3-ps skew time     

基于边界扫描技术的板级测试分析

随着支持IEEE1149.1标准的边界扫描芯片的广泛应用,传统的电路板测试方法如使用万用表、示波器"探针",已不能满足板级测试的需求,相反一种基于板级测试的边界扫描技术得到了迅速发展。对边界扫描测试技术的原理进行了剖析,根据边界扫描测试系统的使用规则对板级测试方法进行了分析、提出了整体测试流程,最后在通用测试的基础上进行了二次开发,提出了提高电路板测试覆盖率的方法。