相变存储器失效机理的研究进展

相变存储器由于具有非易失性、高速度、低功耗等优点被认为是最有可能成为下一代存储器的主流产品之一。然而存储器芯片的良率、密度和操作速度受制于性能最差的单元,因此研究相变存储器的失效机理对于存储器芯片成本的降低以及性能的提升至关重要。文章综述了相变存储器失效机理的研究进展,主要讨论和归纳了电性操作和工艺制程所导致的相变存储器失效模型和失效机理,包括电迁移、热动力学效应、相变应力和热应力、电压极性、结晶引发的偏析、浓度梯度、电极材料以及制造工艺引起的失效。     

高压双扩散漏端MOS晶体管双峰衬底电流的形成机理及其影响

利用0.15μm标准CMOS工艺制造出了工作电压为30V的双扩散漏端MOS晶体管(double diffused drain MOS, DDDMOS).观察到DDDMOS的衬底电流-栅压曲线(I_b-V_g曲线)有两个峰.通过实验和TCAD模拟揭示了DDDMOS衬底电流的形成机理,发现衬底电流第一个峰的成因与传统MOS器件相同;第二个峰来自于发生在漂移区远离沟道一侧高场区的碰撞离化电流.通过求解泊松方程和电流连续性方程,分析了器件的物理和几何参数对导致衬底电流重新上升的漂移区电场的影响.在分析了DDDMOS衬底电流的第二个峰形成机理的基础上,考察了其对器件的可靠性的影响. 关键词： 高压器件 衬底电流 可靠性     

微氮直拉硅单晶中氧化诱生层错透射电镜研究

利用透射电镜研究了热氧化过程中含氮（NCZ）和不含氮（CZ）直拉硅单晶的氧化诱生缺陷.研究表明，NCZ中的氧化诱生层错的尺寸随着湿氧氧化时间的延长而减小，并有冲出型位错产生.而在CZ中，生成了大量的多面体氧沉淀，并且随着热氧化时间的延长，层错的尺寸逐渐增大. 关键词： 直拉硅 透射电镜 氧化诱生层错     

铁电薄膜漏电流的应变调控

基于密度泛函理论的第一性原理并结合非平衡格林函数, 探讨了应变对 BaTiO₃ 铁电薄膜漏电流的影响规律.研究表明,压应变能有效地抑制BaTiO₃ 铁电薄膜漏电流, 特别是当压应变为4%时,其漏电流相对无应变状态降低了近10 倍.通过考察体系的透射系数和电子态密度发现: 一方面压应变状态下铁电隧道结的透射几率要比张应变时小,特别是在费米面附近;另一方面随着张应变过渡至压应变时,价带的位置逐渐向低能区移动而导带向高能区移动,导致了其带隙的增大, 从而有效抑制了漏电流. 本研究为寻找抑制铁电薄膜漏电流,提高铁电薄膜及铁电存储器的性能提供合适的方法. 关键词： 铁电薄膜 双轴应变 漏电流 第一性原理     

磁随机存储器中垂直电流驱动的磁性隧道结自由层的磁化翻转

在基于磁性隧道结(Magnetic Tunneling Junction，MTJ)的磁随机存储器(Magnetoresistantive Random Access Memory，MRAM)中利用通过MTJ的垂直电流，实现信息写入的新方法，同时给出了基于此新方法的一种新的MRAM结构和驱动原理图，并分析了它的读和写操作的可行性具体过程. 关键词： 垂直电流 磁性隧道结 磁随机存储器     

通孔尺寸对铜互连应力迁移失效的影响

在200℃温度下进行了700h双层铜互连(M1/M2)的应力迁移加速老化试验, 结合有限元分析和聚焦离子束(focused-ion-beam,简称FIB)技术研究了通孔直径分别为500和350nm的铜互连应力诱生空洞失效现象, 探讨了应力诱生空洞的形成机理, 并分析了通孔尺寸对铜互连应力迁移的影响. 结果表明,M1互连应力和应力梯度在通孔底部边缘处达到极大值. 应力梯度在应力诱生空洞成核过程中起主导作用, 由张应力产生的过剩空位在应力梯度作用下沿Cu M1/SiN界面作扩散运动并在应力梯度极大值处成核生长成空洞. 由于M1互连应力沿横向方向变化较快, 因此应力诱生空洞的横向生长速率较大. 当通孔直径增大时,互连应力和应力梯度值增大, 并导致应力诱生空洞的生长速率上升. 关键词： 铜互连 应力迁移 应力诱生空洞 失效     

介观电路中电流的量子特性

基于介观电路中电荷的量子化特性和介观电容中存在弱耦合效应的物理事实,对介观LC电路进行了量子力学处理,并讨论了电路中的类超导电流的量子特性。结果表明:无源情形时介观LC电路中类超导电流随时间变化具有周期性,其平均值为零;在直流稳压电源的作用下类超导电流存在直流分量,总电流平均值存在shapiro台阶;在交流电源的作用下类超导电流也可以存在直流分量,但总电流平均值不存在Shapiro台阶。     

基于三维场路耦合方法的超导变压器绕组漏磁场和电流分布研究

超导带材的零电阻特性使得绕组限制环流的能力大大降低。此文利用有限元仿真软件,采用三维场路耦合方法,在330k VA高温超导变压器低压侧绕组间气隙采用4种不同排列方式的情况下,分别分析了绕组漏磁场和电流分布。研究表明,两端的双饼绕组漏磁场和电流高于其它双饼绕组;采用ISOB气隙方式排列的中部双饼绕组电流低于平均额定电流而采用IBOS气隙方式排列的中部双饼绕组电流高于平均额定电流;在4种排列方式中,采用ISOB气隙方式排列可以降低电流分布的不均匀程度,而采用IBOS气隙方式排列可以降低漏磁场的大小。研究综合表明,采用双饼绕组气隙由中间以定值向两边递增的排列方式不仅可以减小环流,而且可以改善磁场分布。     

磁场对聚合物光电池中电流的影响

制备了结构为 ITO/PEDOT:PSS/P3HT:PCBM/Ca/Al的聚合物光电池器件,并在不同偏压下,分别测量了器件的光电流和暗电流随外加磁场的变化. 发现随外加磁场增加,光电流增强,暗电流减弱. 从聚合物光电池中光电流和暗电流的产生机制出发,对该现象进行了解释,认为外加磁场可以有效改变单重态极化子对和三重态极化子对之间的相对比例,进而使自由载流子浓度增加. 光生自由载流子浓度增加是光生电流增强的原因,而自由载流子与三重态激子的相互作用导致了暗电流减弱. 开路电压附近,光电流随磁场增加而增强可以近似 关键词： 聚合物光电池 磁场效应 光生电流 极化子对     

应力调制的自旋转矩临界电流

自旋转矩临界电流过大的问题长期以来一直为人们所关注.本文提出,可以通过引入面外应力即引入应力各向异性场来降低退磁场,从而降低自旋转矩的临界电流.本文采用四分量分布式自旋电路模型计算了横向自旋阀由注入端输运到探测端(自由层)的极化电流大小.利用Landau-Lifshitz-Gilbert-Slonczewski方程数值研究了存在应力时,横向自旋阀中自旋转矩引起的自由层磁矩翻转的性质.结果表明,适当选择应力方向可使面外退磁场得到有效补偿,从而显著降低自旋转矩临界电流.另外,随着应力提高和退磁场的减小,磁矩翻转时间也大大减小.     

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.     

Effect of STI-induced mechanical stress on leakage current in deep submicron CMOS devices

The shallow trench isolation (STI) induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper, we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage ($I_{\rm sub})$, gate-induced-drain-leakage ($I_{\rm GIDL})$, gate edge-direct-tunnelling leakage ($I_{\rm EDT})$ and band-to-band-tunnelling leakage ($I_{\rm BTBT})$ were analysed. For NMOS, $I_{\rm sub}$ can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.     

AlGaN/GaN 高电子迁移率晶体管漏电流退化机理研究

本文首先制备了与AlGaN/GaN高电子迁移率晶体管 (HEMT) 结构与特性等效的AlGaN/GaN异质结肖特基二极管, 采用步进应力测试比较了不同栅压下器件漏电流的变化情况, 然后基于电流-电压和电容-电压测试验证了退化前后漏电流的传输机理, 并使用失效分析技术光发射显微镜 (EMMI) 观测器件表面的光发射, 研究了漏电流的时间依赖退化机理. 实验结果表明: 在栅压高于某临界值后, 器件漏电流随时间开始增加, 同时伴有较大的噪声. 将极化电场引入电流与电场的依赖关系后, 器件退化前后的 log(I_FT/E)与√E 都遵循良好的线性关系, 表明漏电流均由电子Frenkel-Poole (FP) 发射主导. 退化后 log(I_FT/E)与√E 曲线斜率的减小, 以及利用EMMI在栅边缘直接观察到了与缺陷存在对应关系的“热点”, 证明了漏电流退化的机理是: 高电场在AlGaN层中诱发了新的缺陷, 而缺陷密度的增加导致了FP发射电流I_FT的增加. 关键词： AlGaN/GaN 高电子迁移率晶体管 漏电流 退化机理     

电器设备泄漏电流测试仪的设计

采用先进的数字集成电路及目前较流行的单片机控制技术，研制出测量精度高、体积小、数字显示、带自诊断功能、操作简便的智能型电器设备泄漏电流测试仪器。     

Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and V_h degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.     

Random telegraph noise on the threshold voltage of multi-level flash memory

We investigate the impact of random telegraph noise (RTN) on the threshold voltage of multi-level NOR flash memory. It is found that the threshold voltage variation (ΔV_th) and the distribution due to RTN increase with the programmed level (V_th) of flash cells. The gate voltage dependence of RTN amplitude and the variability of RTN time constants suggest that the large RTN amplitude and distribution at the high program level is attributed to the charge trapping in the tunneling oxide layer induced by the high programming voltages. A three-dimensional TCAD simulation based on a percolation path model further reveals the contribution of those trapped charges to the threshold voltage variation and distribution in flash memory.     

Transport mechanism of reverse surface leakage current in AlGaN/GaN high-electron mobility transistor with SiN passivation

The transport mechanism of reverse surface leakage current in the AlGaN/GaN high-electron mobility transistor(HEMT) becomes one of the most important reliability issues with the downscaling of feature size.In this paper,the research results show that the reverse surface leakage current in AlGaN/GaN HEMT with SiN passivation increases with the enhancement of temperature in the range from 298 K to 423 K.Three possible transport mechanisms are proposed and examined to explain the generation of reverse surface leakage current.By comparing the experimental data with the numerical transport models,it is found that neither Fowler-Nordheim tunneling nor Frenkel-Poole emission can describe the transport of reverse surface leakage current.However,good agreement is found between the experimental data and the two-dimensional variable range hopping(2D-VRH) model.Therefore,it is concluded that the reverse surface leakage current is dominated by the electron hopping through the surface states at the barrier layer.Moreover,the activation energy of surface leakage current is extracted,which is around 0.083 eV.Finally,the SiN passivated HEMT with a high Al composition and a thin AlGaN barrier layer is also studied.It is observed that 2D-VRH still dominates the reverse surface leakage current and the activation energy is around 0.10 eV,which demonstrates that the alteration of the AlGaN barrier layer does not affect the transport mechanism of reverse surface leakage current in this paper.     

Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation

The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10¹⁸ cm^-3 and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.     

GaN基异质结缓冲层漏电分析

通过对GaN基异质结材料C-V特性中耗尽电容的比较,得出AlGaN/GaN异质结缓冲层漏电与成核层的关系.实验结果表明,基于蓝宝石衬底低温GaN成核层和SiC衬底高温AlN成核层的异质结材料比基于蓝宝石衬底低温AlN成核层异质结材料漏电小、背景载流子浓度低.深入分析发现,基于薄成核层的异质结材料在近衬底的GaN缓冲层中具有高浓度的n型GaN导电层,而基于厚成核层的异质结材料的GaN缓冲层则呈高阻特性.GaN缓冲层中的n型导电层是导致器件漏电主要因素之一,适当提高成核层的质量和厚度可有效降低GaN缓冲层的背景载流子浓度,提高GaN缓冲层的高阻特性,抑制缓冲层漏电. 关键词： AlGaN/GaN异质结 GaN缓冲层 漏电 成核层     

穿透型V形坑对GaN基p-i-n结构紫外探测器反向漏电的影响

研究了GaN基p-i-n（p-AlGaN/i-GaN/n-GaN）结构紫外探测器的漏电机理．实验发现,在位错密度几乎相同的情况下,基于表面有较高密度的V形坑缺陷材料制备的器件表现出较高的反向漏电．进一步的SEM测试发现,这种V形坑穿透到有源区i-GaN、甚至n-GaN层．在制备p-AlGaN电极时,许多金属会落在V形坑中,从而与i-GaN形成了肖特基接触,有些甚至直接和n-GaN形成欧姆接触．正是由于并联的肖特基接触和欧姆接触的存在导致了漏电的增加． 关键词： GaN 紫外探测器 V形坑 反向漏电