低工作电压聚噻吩薄膜晶体管

以高掺杂Si单晶片作为衬底且充当栅电极,采用磁控溅射法在硅片上沉积HfTiO薄膜作为栅介质层,聚三己基噻吩(P3HT)薄膜作为半导体活性层,金属Au作为源、漏电极,并采用十八烷基三氯硅烷(OTS)对栅介质层表面修饰,在空气环境下成功地制备出聚合物薄膜晶体管(PTFT).PTFT器件测试结果表明,该晶体管在低的驱动电压(<-1 V)下仍呈现出良好的饱和行为,其阈值电压和有效场效应迁移率分别为0.4 V和2.2×10^-2 cm²/V ·s.通过对金属-聚合物-氧化物 关键词： 聚合物薄膜晶体管 聚三己基噻吩 场效应迁移率 k栅介质')" href="#">高k栅介质     

基于聚(4-乙烯基苯酚)衬底修饰层喷墨打印的小分子有机半导体薄膜制备和表征

采用旋涂法预先在SiO₂衬底表面形成一层聚（4-乙烯基苯酚）（PVP）作为表面修饰层,以喷墨打印的6,13-双（三异丙基甲硅烷基乙炔基）并五苯（TIPS并五苯）作为有源层制作有机薄膜晶体管,有效改善了有机半导体薄膜的形貌。采用真空热蒸镀工艺制备源漏电极,形成底栅顶接触结构的有机薄膜晶体管（OTFT）器件。作为对比,在未经过表面修饰的SiO₂衬底上采用相同条件打印TIPS并五苯薄膜晶体管,发现在经过PVP修饰的SiO₂衬底上打印的单点厚度更均匀,咖啡环效应被抑制或被消除;而通过多点交叠打印形成的矩形薄膜的晶粒尺寸更大,相应的OTFT器件具有更高的场效应迁移率。在有PVP修饰层的衬底上制作的OTFT,器件在饱和区的平均场效应迁移率达到了0.065 cm²·V^-1·s^-1;而直接在SiO₂衬底上制作的器件,相应的平均场效应迁移率仅为0.02 cm²·V^-1·s^-1。     

基于蛋清栅介质的超低压双电层薄膜晶体管

新一代环保、生物兼容性电子功能器件受到了广泛关注.本文采用具有高质子导电特性的天然鸡蛋清作为耦合电解质膜制备双电层薄膜晶体管,该薄膜晶体管以氧化铟锡导电玻璃为衬底和底电极,以旋涂法制备的鸡蛋清为栅介质,以磁控溅射沉积的氧化铟锌为沟道和源漏电极.实验结果表明,这种基于鸡蛋清的栅介质具有良好的绝缘性,并能在其与沟道界面处形成巨大的双电层电容,从而使得该类晶体管具有超低工作电压（1.5 V）、低亚阈值（164 mV/dec）、大电流开关比（2.4×10⁶）和较高的饱和区场效应迁移率（38.01 cm²/（V· s））.这种以天然鸡蛋清为栅介质的超低压双电层TFTs有望应用于新型生物电子器件及低能耗便携式电子产品.     

基于聚噻吩/聚己内酯共混物的有机薄膜晶体管

选择聚3-己基噻吩(P3HT)/聚己内酯(PCL)双晶共混体系制备了不同配比的共混物有机薄膜晶体管。电学性能研究发现,随着共混物中P3HT含量降低,薄膜晶体管的场效应迁移率、开关电流比和阈值电压等性能缓慢降低。当P3HT质量分数为40%时,共混物薄膜仍具有较好的场效应性能,迁移率为0.008 cm²·V^-1·s^-1,开关电流比为5×10³,阈值电压为45.5 V。原子力显微镜测试结果表明:共混物成膜时发生明显的垂直相分离,在界面处形成连续的半导体层,有利于载流子传输。     

低栅极电压控制下带有phenyltrimethoxysilane单分子自组装层的有机薄膜晶体管场效应特性研究

制作了底栅极顶接触有机薄膜晶体管器件,60 nm的pentacene被用作有源层,120 nm热生长的SiO₂作为栅极绝缘层.通过采用不同自组装修饰材料对器件的有源层与栅极绝缘层之间的界面进行修饰,如octadecyltrichlorosilane （OTS）,phenyltrimethoxysilane （PhTMS）,来比较界面修饰层对器件性能的影响.同时对带有PhTMS修饰层的OTFTs器件低栅极电压调制下的场效应行为及其载流子的传输机理进行研究.结果得到,当|V 关键词： 有机薄膜晶体管 自组装单分子层 场效应迁移率 低栅极调制电压     

氧化锌锡薄膜晶体管的研究

在ITO玻璃基底上用射频磁控溅射技术生长氧化锌锡(ZnSnO)沟道有源层、用PECVD生长SiO₂薄膜作为薄膜晶体管的栅绝缘层研制了薄膜晶体管(TFT), 器件的场效应迁移率最高达到μ_n=9.1 cm²/(V ·s),阈值电压-2 V,电流开关比为10⁴. 关键词： 氧化锌锡 薄膜晶体管 场效应迁移率     

基于聚(4-乙烯基苯酚)衬底修饰层喷墨打印的小分子有机半导体薄膜制备和表征

采用旋涂法预先在SiO2衬底表面形成一层聚(4-乙烯基苯酚)(PVP)作为表面修饰层,以喷墨打印的6,13-双(三异丙基甲硅烷基乙炔基)并五苯(TIPS并五苯)作为有源层制作有机薄膜晶体管,有效改善了有机半导体薄膜的形貌。采用真空热蒸镀工艺制备源漏电极,形成底栅顶接触结构的有机薄膜晶体管(OTFT)器件。作为对比,在未经过表面修饰的SiO2衬底上采用相同条件打印TIPS并五苯薄膜晶体管,发现在经过PVP修饰的SiO2衬底上打印的单点厚度更均匀,咖啡环效应被抑制或被消除;而通过多点交叠打印形成的矩形薄膜的晶粒尺寸更大,相应的OTFT器件具有更高的场效应迁移率。在有PVP修饰层的衬底上制作的OTFT,器件在饱和区的平均场效应迁移率达到了0.065 cm2·V-1·s-1;而直接在SiO2衬底上制作的器件,相应的平均场效应迁移率仅为0.02 cm2·V-1·s-1。     

有机薄膜晶体管中接触效应的研究

研究了接触效应对有机薄膜晶体管性能的影响.首先在n型重掺杂Si片上制备了以M_OO₃修饰的Al电极为源漏电极的Pentacene基OTFTs(organic thin film transistors),器件场效应迁移率μ_ef达到0.42 cm²/V ·s,阈值电压V_T为-9.16 V,开关比4.7×10³.通过中间探针法,对器件电势分布做了定性判断 关键词： 有机薄膜晶体管 场效应迁移率 接触效应 电荷漂移     

非晶铟镓锌氧薄膜晶体管钼/铜源漏电极的研究

针对非晶铟镓锌氧薄膜晶体管（a-IGZO TFT）的钼/铜源漏电极开展研究。实验证明,单层Mo源漏电极与栅绝缘层之间的粘附性好、表面粗糙度较小、电阻率较大,而单层Cu源漏电极与栅绝缘层之间的结合性差且Cu原子扩散问题严重、表面粗糙度较大、电阻率较小。为了实现优势互补,我们设计了双层Mo（20 nm）/Cu（80 nm）源漏电极,并采用优化工艺制备了包含该电极结构的a-IGZO TFT。器件具有良好的电学特性,场效应迁移率为 8.33 cm²·V^-1·s^-1, 阈值电压为6.0 V,亚阈值摆幅为2.0 V/dec,开关比为 1.3×10⁷,证明了双层Mo/Cu源漏电极的可行性和实用性。     

沟道层厚度对室温制备的In2O3薄膜晶体管器件性能的影响

在室温下采用直流磁控溅射以SiO₂/Si为衬底制备了不同沟道层厚度的底栅式In₂O₃薄膜晶体管,讨论了沟道层厚度对底栅In₂O₃薄膜晶体管的电学性能的影响。实验结果表明:器件的特性与沟道层厚度有关,最优沟道层厚度的In₂O₃薄膜晶体管为增强型,其阈值电压为2.5 V,开关电流比约为10⁶,场效应迁移率为6.2 cm²·V^-1·s^-1。     

Polymer thin-film transistor based on a high dielectric constant gate insulator

In this paper full polymer thin-film transistors (PTFTs) based on Poly (acrylonitrile) (PAN) as the gate dielectric and poly (2-methoxy-5-(2'-ethyl-hexyloxy)-1,4-phenylene-vinylene) (MEH-PPV) as the semiconductor layer were investigated by using different channel width/length ratios. Relatively high dielectric constant of the polymer dielectric layer (6.27) can remarkably reduce the threshold voltage of the transistors to below -3V. Hole field-effect mobility of MEH-PPV of the PTFTs was about 4.8×10^-4cm²/Vs, and on/off current ratio was larger than 10², which was comparable with that of transistors with widely used Poly (4-vinyl phenol) (PVP) or SiO₂ as gate dielectrics.     

High-photosensitivity polymer thin-film transistors based on poly（3-hexylthiophene）

Polymer thin-film transistors(PTFTs) based on poly(3-hexylthiophene) are fabricated by the spin-coating process,and their photo-sensing characteristics are investigated under steady-state visible-light illumination.The photosensitivity of the device is strongly modulated by gate voltage under various illuminations.When the device is in the subthreshold operating mode,a significant increase in its drain current is observed with a maximum photosensitivity of 1.7×10 3 at an illumination intensity of 1200 lx,and even with a relatively high photosensitivity of 611 at a low illumination intensity of 100 lx.However,when the device is in the on-state operating mode,the photosensitivity is very low:only 1.88 at an illumination intensity of 1200 lx for a gate voltage of-20 V and a drain voltage of -20 V.The results indicate that the devices could be used as photo-detectors or sensors in the range of visible light.The modulation mechanism of the photosensitivity in the PTFT is discussed in detail.     

Physics of fluctuation processes in downscaled silicon MOSFETs

Physical mechanics of fluctuation processes in advanced submicron and decananometer MOSFETs (metal-oxide-semiconductor field-effect transistors) including the ultra-thin film SOI (siliconon-insulator) devices using strained silicon films are reviewed. The review is substantially based on the results obtained by the authors. It is shown that the following drastic changes occur in the nature and parameters of noise in such devices as a result of their downscaling when the gate oxide thickness and the channel length and width are decreased, the SOI substrates are used, the silicon film thickness is reduced, the film doping level is varied, the strained silicon films are employed, etc. Firstly, the Lorentzian components can appear in the current noise spectra. Those components are due to (i) electron tunneling from the valence band through the gate oxide in the SOI MOSFETs of a sufficiently thin gate oxide (LKE-Lorentzians); (ii) Nyquist fluctuations generated in the source and drain regions near the back Si/SiO₂ interface in the SOI MOSFETs (BGI Lorentzians); (iii) electron exchange between the channel and some single trap in the gate oxide of the transistors with sufficiently small length and width of the channel (RTS Lorentzians). Secondly, the 1/f-noise level can increase due to (i) the appearance of recombination processes near the Si/SiO₂ interface activated by the currents of electron tunneling from the valence band; (ii) an increase in the trap density in the gate oxide of the devices fabricated on the biaxially tensile-strained silicon films; (iii) the contribution of the 1/f fluctuations of the current flowing through the gate oxide as a result of electron tunneling from the conduction band. At the same time, the 1/f-noise level may decrease due to a decrease in the trap density in the gate oxide of the transistors fabricated on the uniaxially tensile-strained silicon films. Moreover, a 1/f ^1.7 component may appear in the noise spectra for the transistors of a sufficiently thin gate oxide, whose component is due to charge fluctuations on the defects located near the interface between the gate polysilicon and the gate oxide.     

The effect ofγ-irradiation on amorphous silicon field effect transistors

The paper deals with the effect ofγ-radiation from a Co⁶⁰ source on the electronic properties of amorphous silicon field effect transistors. These thin film devices, deposited by the glow discharge technique, are being developed for addressable liquid crystal displays, logic circuits and other applications. 1 Mrad (Si) and 5 Mrad (Si) doses were used and the transistors were held at gate voltages between ?8V and +8V during irradiation. Measurements on irradiated specimens showed shifts in threshold voltage of less than 3 V and a change in transconductance below 10%, both of which could be removed by annealing above 130 °C. These results are compared with presently available “radiation hardened” crystalline silicon device structures and it is concluded that in spite of the thicker gate insulation layer (0.3 μm of silicon nitride) of the amorphous devices, the latter are remarkably radiation tolerant, with little degradation in performance. Measurements on irradiatedα-Si films deposited on glass show pronounced conductivity changes, not observed in the transistors. It is suggested that these effects arise at the Si/glass interface, and are prevented by the presence of the silicon nitride film in the devices.     

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO7340Q, 7325http://cpb.iphy.ac.cn/CN/10.1088/1674-1056/19/5/057302https://cpb.iphy.ac.cn/CN/article/downloadArticleFile.do?attachType=PDF&id=111774Ge substrate, transistor, HfSiON, hole mobilityProject supported by the National Basic Research Program of China (Grant No.~2006CB302704).Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO$_{x}$ ($1Ge;substrate;transistor;HfSiON;hole;mobilityGe and Si p-channel metal-oxide-semiconductor field-effect-transistors(p-MOSFETs) with hafnium silicon oxynitride(HfSiON) gate dielectric and tantalum nitride(TaN) metal gate are fabricated.Self-isolated ring-type transistor structures with two masks are employed.W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately.Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor(MOS) capacitors may be caused by charge trapping centres in GeOx(1 < x < 2).Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method.The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V.s) and 81.0 cm2/(V.s),respectively.Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.     

Stability of polymer thin-film transistors based on poly(2-methoxy-5-(2′-ethyl-hexyloxy)-1,4-phenylene vinylene)

Polymer thin-film transistors (PTFTs) based on poly(2-methoxy-5-(2′-ethyl-hexyloxy)-1,4-phenylene vinylene) (MEH-PPV) semiconductor are fabricated by spin-coating process and characterized. In the experiments, solution preparation, deposition and device measurements are all performed in air for large-area applications. Hysteresis effect and gate-bias stress effect are observed for the devices at room temperature. The saturation current decreases and the threshold voltage shifts toward the negative direction upon gate-bias stress, but carrier mobility hardly changes. By using quasi-static C-V analysis for MOS capacitor structure, it can be deduced that the origin of threshold-voltage shift upon negative gate-bias stress is predominantly associated with hole trapping within the SiO₂ gate dielectric near the SiO₂/MEH-PPV interface due to hot-carrier emission.     

Tin – an unlikely ally for silicon field effect transistors?

We explore the effectiveness of tin (Sn), by alloying it with silicon, to use SiSn as a channel material to extend the performance of silicon based complementary metal oxide semiconductors. Our density functional theory based simulation shows that incorporation of tin reduces the band gap of Si(Sn). We fabricated our device with SiSn channel material using a low cost and scalable thermal diffusion process of tin into silicon. Our high‐κ/metal gate based multi‐gate‐field‐effect‐transistors using SiSn as channel material show performance enhancement, which is in accordance with the theoretical analysis. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Analytical threshold voltage model for strained silicon GAA-TFET

Tunnel field effect transistors(TFETs) are promising devices for low power applications.An analytical threshold voltage model,based on the channel surface potential and electric field obtained by solving the 2D Poisson's equation,for strained silicon gate all around TFETs is proposed.The variation of the threshold voltage with device parameters,such as the strain(Ge mole fraction x),gate oxide thickness,gate oxide permittivity,and channel length has also been investigated.The threshold voltage model is extracted using the peak transconductance method and is verified by good agreement with the results obtained from the TCAD simulation.     

Composition influence of SiNx gate insulator fabricated by radio frequency (RF) Magnetron sputtering on characteristics of organic thin-film transistors

To investigate the effect of composition of SiNx on the properties of organic thin-film transistors (OTFTs), we fabricated bottom gate top contact OTFTs devices with different composition SiNx gate insulator. Pentacene based OTFTs with SiNx insulator, prepared using an interface modification process of UV-ozone treatment, exhibited effective mobility of 0.63 cm2/Vs and on/off current ratio of 10⁵. Overall improvement in field-effect mobility, threshold voltage was observed as silicon content in SiNx increases. The results demonstrate that the viability of using SiNx for OTFTs and of UV-ozone treatment could be used to improve the properties of organic thin-film transistors. The dependence of the contact angle on the SiNx film composition is evident for the untreated samples, the contact angle increases as the silicon content in the untreated nitride film increases. In contrast, the rise in contact angle across all samples after surface treatment signifies effective surface modification to promote hydrophobicity of the nitride surface. The hydrophobic surface is needed for the organic semiconductor.