Influence of Si/SiO2 interface properties on electrical performance and breakdown characteristics of ultrathin stacked oxide/nitride dielectric films

In this work, the influence of Si/SiO₂ interface properties, interface nitridation and remote-plasma-assisted oxidation (RPAO) thickness (<1 nm), on electrical performance and TDDB characteristics of sub-2 nm stacked oxide/nitride gate dielectrics has been investigated using a constant voltage stress (CVS). It is demonstrated that interfacial plasma nitridation improves the breakdown and electrical characteristics. In the case of PMOSFETs stressed in accumulation, interface nitridation suppresses the hole traps at the Si/SiO₂ interface evidenced by less negative V_t shifts. Interface nitridation also retards hole tunneling between the gate and drain, resulting in reduced off-state drain leakage. In addition, the RPAO thickness of stacked gate dielectrics shows a profound effect in device performance and TDDB reliability. Also, it is demonstrated that TDDB characteristics are improved for both PMOS and NMOS devices with the 0.6 nm-RPAO layer using Weibull analysis. The maximum operating voltage is projected to be improved by 0.3 V difference for a 10-year lifetime. However, physical breakdown mechanism and effective defect radius during stress appear to be independent of RPAO thickness from the observation of the Weibull slopes. A correlation between trap generation and dielectric thickness changes based on the C-V distortion and oxide thinning model is presented to clarify the trapping behavior in the RPAO and bulk nitride layer during CVS stress.     

基于原位等离子体氮化及低压化学气相沉积-Si_3N_4栅介质的高性能AlGaN/GaN MIS-HEMTs器件的研究

通过对低压化学气相沉积(LPCVD)系统进行改造,实现在沉积Si_3N_4薄膜前的原位等离子体氮化处理,氮等离子体可以有效地降低器件界面处的氧含量和悬挂键,从而获得了较低的LPCVD-Si_3N_4/GaN界面态,通过这种技术制作的MIS-HEMTs器件,在扫描栅压范围V_(G-sweep)=(-30 V,+24 V)时,阈值回滞为186 mV,据我们所知为目前高扫描栅压V_(G+)(20 V)下的最好结果.动态测试表明,在400 V关态应力下,器件的导通电阻仅仅上升1.36倍(关态到开态的时间间隔为100μs).     

高k介质在新型半导体器件中的应用

当CMOS器件特征尺寸缩小到45 nm以下, SiO₂作为栅介质材料已经无法满足性能和功耗的需要, 用高 k材料替代SiO₂是必然选择. 然而, 由于高 k材料自身存在局限性, 且与器件其他部分的兼容性差, 产生了很多新的问题如界面特性差、 阈值电压增大、 迁移率降低等. 本文简要回顾了高 k栅介质在平面型硅基器件中应用存在的问题以及从材料、 结构和工艺等方面采取的解决措施, 重点介绍了高k材料在新型半导体器件中的应用, 并展望了未来的发展趋势.     

Physics of fluctuation processes in downscaled silicon MOSFETs

Physical mechanics of fluctuation processes in advanced submicron and decananometer MOSFETs (metal-oxide-semiconductor field-effect transistors) including the ultra-thin film SOI (siliconon-insulator) devices using strained silicon films are reviewed. The review is substantially based on the results obtained by the authors. It is shown that the following drastic changes occur in the nature and parameters of noise in such devices as a result of their downscaling when the gate oxide thickness and the channel length and width are decreased, the SOI substrates are used, the silicon film thickness is reduced, the film doping level is varied, the strained silicon films are employed, etc. Firstly, the Lorentzian components can appear in the current noise spectra. Those components are due to (i) electron tunneling from the valence band through the gate oxide in the SOI MOSFETs of a sufficiently thin gate oxide (LKE-Lorentzians); (ii) Nyquist fluctuations generated in the source and drain regions near the back Si/SiO₂ interface in the SOI MOSFETs (BGI Lorentzians); (iii) electron exchange between the channel and some single trap in the gate oxide of the transistors with sufficiently small length and width of the channel (RTS Lorentzians). Secondly, the 1/f-noise level can increase due to (i) the appearance of recombination processes near the Si/SiO₂ interface activated by the currents of electron tunneling from the valence band; (ii) an increase in the trap density in the gate oxide of the devices fabricated on the biaxially tensile-strained silicon films; (iii) the contribution of the 1/f fluctuations of the current flowing through the gate oxide as a result of electron tunneling from the conduction band. At the same time, the 1/f-noise level may decrease due to a decrease in the trap density in the gate oxide of the transistors fabricated on the uniaxially tensile-strained silicon films. Moreover, a 1/f ^1.7 component may appear in the noise spectra for the transistors of a sufficiently thin gate oxide, whose component is due to charge fluctuations on the defects located near the interface between the gate polysilicon and the gate oxide.     

Si-based materials and devices for light emission in silicon

We report on the fabrication and performances of extremely efficient Si-based light sources. The devices consist of MOS structures with erbium (Er) implanted in the thin gate oxide. The devices exhibit strong 1.54 μm electroluminescence (EL) at 300 K with a 10% external quantum efficiency, comparable to that of standard light-emitting diodes using III–V semiconductors. Er excitation is caused by hot electrons impact and oxide wearout limits the reliability of the devices. Much more stable light-emitting MOS devices have been fabricated using Er-doped silicon rich oxide (SRO) films as gate dielectric. These devices show a high stability, with an external quantum efficiency reduced to 1%. In these devices, Er pumping occurs by energy transfer from the Si nanostructures to the rare-earth ions. Finally, we have also fabricated MOS structures with Tb- and Yb-doped SiO₂ which show room temperature EL at 540 nm (Tb) and 980 nm (Yb) with an external quantum efficiency of a 10% and 0.1%, respectively.     

0.18μm CMOS工艺栅极氧化膜可靠性的衬底和工艺依存性

用斜坡电压法(Voltage Ramp, V-ramp)评价了0.18μm双栅极 CMOS工艺栅极氧化膜击穿电量(Charge to Breakdown, Q_bd)和击穿电压(Voltage to Breakdown, V_bd). 研究结果表明，低压器件(1.8V)的栅极氧化膜(薄氧)p型衬底MOS电容和N型衬底电容的击穿电量值相差较小，而高压器件(3.3V)栅极氧化膜(厚氧)p衬底MOS电容和n衬底MOS电容的击穿电量值相差较大，击穿电压测试值也发现与击穿电量 关键词： 薄氧 可靠性 击穿电压 击穿电量     

DLTS characterization of silicon nitride passivated AlGaN/GaN heterostructures

Passivating the ungated surface of AlGaN/GaN HEMTs with silicon nitride (SiN) is effective in improving the microwave output power performances of these devices. However, very little information is available about surface states in GaN-based HEMTs after SiN passivation. In this work we investigate AlGaN/GaN HEMTs structures having either metal–semiconductor or metal–SiN–semiconductor gate contacts. In short gate devices conductance DLTS measurements point out a hole-like peak that shows an anomalous behaviour and can be ascribed to surface states in the access regions of the device. In insulated gate HEMTs a band of levels is detected and ascribed to surface states, whose energy ranges from 0.14 to 0.43 eV. Capacitance–voltage measurements allow us to point out the existence of a second band of interface states deeper in energy than the former one. This band is responsible for slow transients observed in the characteristics of the insulated gate FAT-HEMT.     

高迁移率Ge沟道器件研究进展

高迁移率Ge沟道器件由于其较高而且更对称的载流子迁移率, 成为未来互补型金属-氧化物-半导体(CMOS) 器件极有潜力的候选材料. 然而, 对于Ge基MOS器件, 其栅、源漏方面面临的挑战严重影响了Ge基MOS 器件性能的提升, 尤其是Ge NMOS器件. 本文重点分析了Ge基器件在栅、源漏方面面临的问题, 综述了国内外研究者们提出的不同解决方案, 在此基础上提出了新的技术方案. 研究结果为Ge基MOS 器件性能的进一步提升奠定了基础.     

Interface engineering with an MOCVD grown ZnO interface passivation layer for ZrO2-GaAs metal-oxide-semiconductor devices

This work deals with the fabrication of a GaAs metal-oxide-semiconductor device with an unpinned interface environment. An ultrathin (∼2 nm) interface passivation layer (IPL) of ZnO on GaAs was grown by metal organic chemical vapor deposition to control the interface trap densities and to prevent the Fermi level pinning before high-k deposition. X-ray photoelectron spectroscopy and high resolution transmission electron microscopy results show that an ultra thin layer of ZnO IPL can effectively suppress the oxides formation and minimize the Fermi level pinning at the interface between the GaAs and ZrO₂. By incorporating ZnO IPL, GaAs MOS devices with improved capacitance-voltage and reduced gate leakage current were achieved. The charge trapping behavior of the ZrO₂/ZnO gate stack under constant voltage stressing exhibits an improved interface quality and high dielectric reliability.     

电压应力下超薄栅氧化层n-MOSFET的击穿特性

研究了90nm工艺下栅氧化层厚度为1.4nm的n-MOSFET的击穿特性，包括V-ramp(斜坡电压)应力下器件栅电流模型和CVS(恒定电压应力)下的TDDB(经时击穿)特性，分析了电压应力下器件的失效和退化机理.发现器件的栅电流不是由单一的隧穿引起，同时还有电子的翻越和渗透.在电压应力下，SiO₂中形成的缺陷不仅降低了SiO₂的势垒高度，而且等效减小了SiO₂的厚度(势垒宽度).另外，每一个缺陷都会形成一个导电通道，这些导电通道的形成增大了栅电流，导致器件性能的退化，同时栅击穿时间变长. 关键词： 超薄栅氧化层 斜坡电压 经时击穿 渗透     

氧空位迁移造成的氧化物介质层时变击穿的蒙特卡罗模拟

基于氧空位在金属氧化物内部迁移的微观机理,利用蒙特卡罗方法建立了一种新型的可模拟金属氧化物介质时变击穿的模拟工具.利用建立的模拟工具研究了界面形成氧空位迁移功函数对介质层击穿行为的影响.该工具可应用于金属氧化物半导体晶体管栅介质击穿研究并准确评估其可靠性.     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

Elimination of GeO2 and Ge3N4 interfacial transition regions and defects at n-type Ge interfaces: A pathway for formation of n-MOS devices on Ge substrates

The contribution from relatively low-K SiON interfacial transition regions (ITRs) between Si and transition metal (TM) gate dielectrics places a significant limitation on equivalent oxide thickness (EOT) scaling for Si complementary metal-oxide-semiconductor (CMOS) devices. This limitation is equally significant and limiting for Ge CMOS devices. Low-K Ge-based ITRs in Ge devices have also been shown to limit performance and reliability, particular for n-MOS field effect transistors. This article identifies the source of significant electron trapping at interfaces between n-Ge or inverted p-Ge, and Ge oxide, nitride and oxynitride ITRs. This is shown to be an interfacial band alignment issue in which native Ge ITRs have conduction band offset energies smaller than those of TM dielectrics, and trap electrons for negative Ge substrate bias. This article also describes a novel remote plasma processing approach for effectively eliminating any significant native Ge ITRs and using a plasma-processing/annealing process sequence for bonding TM gate dielectrics directly to the Ge substrate surface.     

Improved interfacial and electrical properties of GaSb metal oxide semiconductor devices passivated with acidic （NH4）2S solution

Surface passivation with acidic(NH4)2S solution is shown to be effective in improving the interfacial and electrical properties of HfO2/GaSb metal oxide semiconductor devices. Compared with control samples, the samples treated with acidic(NH4)2S solution show great improvements in gate leakage current, frequency dispersion, border trap density, and interface trap density. These improvements are attributed to the enhancing passivation of the substrates, according to analysis from the perspective of chemical mechanism, X-ray photoelectron spectroscopy, and high-resolution cross-sectional transmission electron microscopy.     

非晶铟锌氧化物薄膜晶体管的低频噪声特性与分析

本文针对底栅结构非晶铟锌氧化物薄膜晶体管的低频噪声特性开展实验与理论研究.由实验结果可知:受铟锌氧化物与二氧化硅界面处缺陷态俘获与释放载流子效应的影响,器件沟道电流噪声功率谱密度随频率的变化遵循1/fγ(γ≈0.75)的变化规律;此外,器件沟道电流归一化噪声功率谱密度随沟道长度与沟道宽度的增加而减小,证明器件低频噪声来源于沟道的闪烁噪声,可忽略源漏结接触及寄生电阻对器件低频噪声的影响.最后,基于载流子数涨落及迁移率涨落模型,提取γ因子与平均Hooge因子,为评价材料及器件特性奠定基础.     

Temperature dependence of the noise amplitude in graphene and graphene oxide

Graphene and related materials such as carbon nanotubes and graphene oxide are promising materials for future applications in chemical sensing and electronics. Electronic noise in these materials is typically very high due to the low number of carriers and the inverse dependence of 1/f noise on the number of carriers. We have investigated the changes in 1/f noise amplitude with temperature in exfoliated graphene and reduced graphene oxide devices. We show that using reduced graphene oxide results in an intriguing environmental coupling to noise amplitude. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Two-dimensional phosphorus diffusion for soft drains in silicon MOS transistors

Phosphorus has a considerably less steep concentration profile than arsenic. Therefore phosphorus is considered as an alternative dopand for soft drain concepts in future MOS devices. In-diffusion of phosphorus starting from a high surface concentration generatesexcess point defects which diffuse into the depth of the crystal and lead to a tail in the phosphorus concentration profile by considerably enhancing the phosphorus diffusion in this region. It is also well known that the interface between silicon and a non growing oxide acts as a sink for excess point defects. Since source/drain areas of MOS transistors are surrounded by gate and isolation oxides, the question arises how the resulting excess point defect distribution may influence the lateral and vertical diffusion profile of phosphorus and hence the channel length and the junction depth of the source/drain region in a MOS device. We extended the one-dimensional Fair-Tsai model of phosphorus diffusion into two dimensions and incorporated that the interface between silicon and a gate oxide acts as a sink for excess point defects and modifies their distribution. The appropriate code was implemented in the two-dimensional process simulation program LADIS. Based on this extended model two-dimensional simulations of phosphorus drains have been performed and compared to experimental results and to results from other numerical models. It turns out that the presence of the gate oxide reduces the tail in the phosphorus concentration profile, considerably in lateral direction and less pronounced in vertical direction. Limitations of the model will be discussed in detail.     

Metal-oxide-semiconductor field effect transistor using ‘oxidizedμc-Si/ultrathin oxide’ gate structure

The metal-oxide-semiconductor (MOS) field effect transistor (FET) using ‘oxidized μ c-Si/ultrathin oxide’ gate structure was studied. It was found that this structure shows negative differential resistance behavior, which can be explained by the Coulomb blockade effect of trapped carriers and immediate tunneling into and tunneling out with gate bias variation. The requirements for the device with this structure showing negative differential resistance behavior are based on very weak resistive coupling between floating gate and channel. They are the thinness of the tunnel oxide film, the thickness ratio of the upper oxidized film and the tunnel oxide, and the channel threshold voltage. MOSFET with this gate structure is proposed as a new negative differential resistance device.     

Research on total-dose hardening for H-gate PD NMOSFET/SIMOX by ion implanting into buried oxide

In this work,we investigate the back-gate I-V characteristics for two kinds of NMOSFET/SIMOX transistors with H gate structure fabricated on two different SOI wafers.A transistors are made on the wafer implanted with Si+ and then annealed in N2,and B transistors are made on the wafer without implantation and annealing.It is demonstrated experimentally that A transistors have much less back-gate threshold voltage shift AVth than B transistors under X-ray total dose irradiation.Subthreshold charge separation technique is employed to estimate the build-up of oxide charge and interface traps during irradiation,showing that the reduced △Vth for A transistors is mainly due to its less build-up of oxide charge than B transistors.Photoluminescence (PL) research indicates that Si implantation results in the formation of silicon nanocrystalline (nanocluster) whose size increases with the implant dose.This structure can trap electrons to compensate the positive charge build-up in the buried oxide during irradiation,and thus reduce the threshold voltage negative shift.     

Impact of post-nitridation annealing on ultra-thin gate oxide performance

Decoupled-Plasma Nitridation (DPN) process with high level of nitrogen incorporation is widely used in the state-of-the-art technology, in order to reduce gate leakage current and boron penetration. However, due to the low temperature DPN process, the post-nitridation annealing treatment is required to improve the ultra-thin gate oxide integrity. In this paper, the effect of post-nitridation annealing on DPN ultra-thin gate oxide was investigated. The device performance and reliability were evaluated in three different post-nitridation annealing ambient (N₂/O₂, He, and NO).