低栅极电压控制下带有phenyltrimethoxysilane单分子自组装层的有机薄膜晶体管场效应特性研究

制作了底栅极顶接触有机薄膜晶体管器件,60 nm的pentacene被用作有源层,120 nm热生长的SiO₂作为栅极绝缘层.通过采用不同自组装修饰材料对器件的有源层与栅极绝缘层之间的界面进行修饰,如octadecyltrichlorosilane （OTS）,phenyltrimethoxysilane （PhTMS）,来比较界面修饰层对器件性能的影响.同时对带有PhTMS修饰层的OTFTs器件低栅极电压调制下的场效应行为及其载流子的传输机理进行研究.结果得到,当|V 关键词： 有机薄膜晶体管 自组装单分子层 场效应迁移率 低栅极调制电压     

InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operating and standby power application below supply voltage of 0.5 V

An In_0.53Ga_0.47As/InP heterojunction-channel tunneling field-effect transistor (TFET) with enhanced subthreshold swing (S) and on/off current ratio (I_on/I_off) is studied. The proposed TFET achieves remarkable characteristics including S of 16.5 mV/dec, on-state current (I_on) of 421 μA/μm, I_on/I_off of 1.2 × 10¹² by design optimization in doping type of In_0.53Ga_0.47As channel at low gate (V_GS) and drain voltages (V_DS) of 0.5 V. Comparable performances are maintained at V_DS below 0.5 V. Moreover, an extremely fast switching below 100 fs is accomplished by the device. It is confirmed that the proposed TFET has strong potentials for the ultra-low operating power and high-speed electron device.     

Investigation of photo-induced change of electro-optical performance in a liquid crystal-organic field effect transistor (LC-OFET)

This study aimed to improve the electrical characteristics of poly(3-hexylthiophene) (P3HT) and liquid crystal-organic field effect transistors (LC-OFETs) under UV illumination. Consequently, a novel LC-OFET was fabricated using a nematic liquid crystal (E63) and a P3HT mixture in an OFET cell. Cell thickness was determined through field emission scanning electron microscopy. For assessment of the electrical characteristics, the LC-OFET device was exposed to various UV light intensities in total darkness for the purpose of obtaining the output- and transfer-current voltage. The capacitance–frequency plot of the capacitor cell was then measured to determine the main parameters including the threshold voltage (V_Th), field effect mobility (μ_FET) and current on/off ratio (I_on/off) of the device. Thus, the full characterisation and UV light response of the electronic parameters were determined for this new class of transistors. Results showed that the new LC-OFET exhibited good performance in the form of low V_Th, high μ_FET, and high I_on/off.     

Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors

In this work, the effects of underlapping drain junction on the performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) have been studied in terms of direct-current (DC) characteristics including on-current (I_on), off-current (I_off), subthreshold swing (S), and I_on/I_off ratio. In addition, the dependences of intrinsic delay time (τ) and radio-frequency (RF) performances including cut-off frequency (f_T) and maximum oscillation frequency (f_max) on gate–drain capacitance (C_gd) with the underlapping were investigated as the gate length (L_gate) is scaled. A GAA TFET with asymmetric junctions, with an underlap at the drain side, demonstrated DC and RF performances superior to those of a device with symmetric junctions.     

Chemical bath deposition of CdS channel layer for fabrication of low temperature-processed thin-film-transistors

～66 nm thick CdS film with a hexagonal structure was uniformly generated via a low temperature-processed chemical bath deposition at 80 °C using a complexing agent of ethylenediaminetetraacetic acid and its crystal structure, surface morphology, optical transmittance, and Raman scattering property were measured. Grown CdS film was used as a channel layer for the fabrication of bottom-gate, top-contact thin-film-transistor (TFT). The TFT device with 60 °C-dried channel layer exhibited a poor electrical performance of on-to-off drain current ratio (I_on/I_off) of 5.1 × 10³ and saturated channel mobility (μ_sat) of 0.10 cm²/Vs. However, upon annealing at 350 °C, substantially improved electrical characteristics resulted, showing I_on/I_off of 5.9 × 10⁷ and μ_sat of 5.07 cm²/Vs. Furthermore, CdS channel layer was chemically deposited in an identical way on a transparent substrate of SiN_x/ITO/glass as part of transparent TFT fabrication, resulting in I_on/I_off of 5.8 × 10⁷ and μ_sat of 2.50 cm²/Vs.     

Low voltage organic field effect transistors with a poly(hexylthiophene)–ZnO nanoparticles composite as channel material

We report on solution processable organic field effect transistors prepared using a poly(3‐hexylthiophene)–ZnO nanoparticles composite as channel semiconductor material and cross‐linked polyvinyl alcohol as gate insulator. Our transistors show a field effect mobility of 0.35 ± 0.06 cm²/V s, threshold voltage of –1.30 ± 0.11 V, and I_on/I_off ratio of (1.0 ± 0.1) × 10³. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics

Recently, a number of semiconductor devices have been widely researched in order to make breakthroughs from the short-channel effects (SCEs) and high standby power dissipation of the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, a design optimization for the silicon nanowire tunneling field-effect transistor (SNW TFET) based on PNPN multi-junction structure and its radio frequency (RF) performances are presented by using technology computer-aided design (TCAD) simulations. The design optimization was carried out in terms of primary direct-current (DC) parameters such as on-current (I_on), off-current (I_off), current ratio (I_on/I_off), and subthreshold swing (SS). Based on the parameters from optimized DC characteristics, basic radio frequency (RF) performances such as cut-off frequency (f_T) and maximum oscillation frequency (f_max) were analyzed. The simulated device had a channel length of 60 nm and a SNW radius of 10 nm. The design variable was width of the n-doped layer. For an optimally designed PNPN SNW TFET, SS of 34 mV/dec and I_on of 35 μA/μm were obtained. For this device, f_T and f_max were 80 GHz and 800 GHz, respectively.     

Impact of work function variation for enhanced electrostatic control with suppressed ambipolar behavior for dual gate L-TFET

The favorable electrostatic potential and tunneling underneath the overall gate region, which prevents legitimate source to drain tunneling, controllability over the gate is assisted in vertical TFET configurations. An L-TFET (L-shaped Tunneling Field-Effect Transistor) has a larger tunneling length than a veritable TFET. As a consequence, the current in the on-state (I_on) has gotten better. The increased ambipolar current and low I_on/I_off ratio of L-TFET will need to be tuned for low-power and high-frequency functionality. On the other hand, significantly worse switching performance and distortions may lead to a weak robust device. By establishing a high-k gate oxide-based drain underlap region with dual gate, this study is dedicated to ameliorating the I_on/I_off by subverting ambipolar behavior. To investigate the impact of height of second gate (H_gate2) and work-function of this (WF_gate2), EBD (Energy Band Diagram), electric field distribution in X and Y direction, potential and recombination rate are examined under various conditions. Which leads to enhanced DC/RF and linearity performance. Along with this, Current-Voltage characteristics, DC/RF, and linearity performance Figure of Merits (FOMs) also investigated the assessment of variation of H_gate2 and WF_gate2, and it is optimized for the better suppression of I_ambi (ambipolar current) with a steep slope in transfer characteristics. In addition to that, Current-voltage statistics (I_ds − V_gs), DC/RF, and linearity efficiency FOMs were being used to assess the influence of changing the H_gate2 and WF_gate2, which was modulated for greater I_ambi suppression (ambipolar current) with improved SS and V_th for the proposed device.     

Surface-modified lead–zirconium-titanate system for solution-processed ferroelectric-gate thin-film transistors

We propose the use of a La₂O₃ (LO) film as the capping layer for improvement of a semiconductor/insulator interface in a solution-processed indium–tin–oxide (ITO) ferroelectric-gate thin-film transistor (FGT) device. It is demonstrated that the LO layer acts as a good barrier film not only for preventing the interdiffusion between the ITO semiconductor and lead–zirconium-titanate (PZT) insulator layers, but also for stabilizing the PZT surface structure. The fabricated FGT device exhibited high I _on/I _off, large M _w, high μ _FE and improved retention time of about 10⁹, 3.5 V, 7.94 cm²?V^?1?s^?1 and 1 day, respectively, which are comparable to or better than those obtained with FGTs fabricated by means of conventional vacuum processes. We also point out that the key origin of the interface improvement is likely due to the incorporation of La into the PZT system, forming a La surface-modified PZT system which is more stable than the pure PZT in terms of Pb volatility and formation of oxygen vacancies.     

Research on the electrical characteristics of an organic thin-film field-effect transistor based on alternating-current resistance

In this article, an organic thin-film field-effect transistor (OTFFET) with top-gate and bottom-contact geometry based on pentacene as the active layer is fabricated. The experimental data of the I-V are obtained from the OTFFET device. The alternating-current (AC) resistance value of the OTFFET device is calculated using the derivation method from the experimental data, and the AC resistance trend curves of the OTFFET device are obtained with the region fitting method. We analyse the characteristics of the OTFFET device with an AC resistance trend curve. To discover whether it has a high resistance, it is proposed to judge the region of the source/drain voltage (V_DS) less than the transition voltage, thereby determining whether the contact between the metal electrode and the organic semiconductor layer of the OTFFET device is Ohmic or non-Ohmic. The theoretical analysis shows that the field-effect mobility and the AC resistance are in reverse proportion. Therefore, we point out that reducing AC resistance is necessary if field-effect mobility is to be improved.     

The fabrication and characterization of 4H SiC power UMOSFETs

The fabrication of 4H-SiC vertical trench-gate metal-oxide-semiconductor field-effect transistors(UMOSFETs) is reported in this paper.The device has a 15-μm thick drift layer with 3×1015 cm-3 N-type doping concentration and a 3.1μm channel length.The measured on-state source-drain current density is 65.4 A/cm2 at Vg = 40 V and VDS = 15 V.The measured threshold voltage(Vth) is 5.5 V by linear extrapolation from the transfer characteristics.A specific on-resistance(Rsp-on) is 181 mΩ·cm2 at Vg = 40 V and a blocking voltage(BV) is 880 V(IDS = 100 μA@880V) at Vg = 0 V.     

Organic insulator layer influence on the electrical properties of N,N’-di (2-ethylhexyl) - 3, 4, 9, 10-perylene diimide organic thin-film transistors: Experiment and modeling

In this work, n- type organic thin film transistors (OTFTs) based on different kinds of organic dielectrics were fabricated, characterized and theoretically investigated. Three kinds of organic insulators were applied as dielectric gate which are: divinyl tetramethyl disiloxane-bis (benzo-cyclobutene) (BCB), poly(vinylalcohol) (PVA) and poly (4-vinyl phenol) (PVP). Analytical model was applied to describe the electrical behavior of the fabricated OTFTs and to explain the absence of saturation of the drain current for the device based on PVA dielectric. In addition, Meyer–Neldel rule-grain boundary model was applied for the calculation of total resistance of OTFTs based on different dielectrics materials. The theoretical results of output characteristics and total resistance showed an excellent agreement with the experimental measurements. The experimental and theoretical calculations revealed that the n-channel OTFTs based on BCB as an insulator layer exhibited superior electrical characteristics in terms of threshold voltage, mobility and drain current compared with the devices based on PVA and PVP as a gate insulator layer. The device based on BCB organic insulator layer has the largest mobility of 4?×?10^?3 cm² V^?1 s^?1, the smallest leakage current relative to the devices based on PVA and PVP. While, the device fabricated with PVP organic insulator gate has a large trap density on the PVP-EHPDI interface which causes a pronounced decrease in field effect mobility and consequently drain current.     

Characteristics of pentacene organic thin film transistor with top gate and bottom contact

High performance pentacene organic thin film transistors (OTFT) were designed and fabricated using SiO₂ deposited by electron beam evaporation as gate dielectric material. Pentacene thin films were prepared on glass substrate with S--D electrode pattern made from ITO by means of thermal evaporation through self-organized process. The threshold voltage V_TH was --2.75± 0.1V in 0---50V range, and that subthreshold slopes were 0.42± 0.05V/dec. The field-effect mobility (μ_EF) of OTFT device increased with the increase of V_DS, but the μ_EF of OTFT device increased and then decreased with increased V_GS when V_DS was kept constant. When V_DS was --50V, on/off current ratio was 0.48× 10⁵ and subthreshold slope was 0.44V/dec. The μ_EF was 1.10cm²/(V.s), threshold voltage was --2.71V for the OTFT device.     

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage( 600 V) integrable silicon-on-insulator(SOI) trench-type lateral insulated gate bipolar transistor(LIGBT) with a reduced cell-pitch is proposed.The LIGBT features multiple trenches(MTs):two oxide trenches in the drift region and a trench gate extended to the buried oxide(BOX).Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field(RESURF) effect.Both increase the breakdown voltage(BV).Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop(Von).The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss(Eoff).The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10?3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.     

Photo-curable epoxy functionalized cyclotetrasiloxane as a gate dielectric for organic thin film transistors

We synthesized a new photo-curable organic/inorganic hybrid material, cyclotetrasiloxane (CTS) derivative containing cyclohexene-1,2-epoxide functional groups (CTS-EPOXY), and its characteristics are compared with a prototypical organic gate insulator of poly(4-vinylphenol) (PVP) in the organic thin film transistors (OTFTs) using pentacene as an active p-type organic semiconductor. Compared with PVP, CTS-EPOXY shows better insulating characteristics and surface smoothness. A metal/insulator/metal (MIM) device with the 300-nm-thick CTS-EPOXY film shows more than two orders of magnitude lower current (less than 40 nA/cm² over the voltage range up to 60 V) compared with PVP. In addition, the pentacene TFT with CTS-EPOXY as a gate dielectric layer shows slightly higher field-effect mobility of μ_FET = 0.20 cm²/V s compared to that with PVP.     

Gadolinium scandate as an alternative gate dielectric in field effect transistors on conventional and strained silicon

Long channel n-type metal oxide semiconductor field effect transistors on thin conventional and strained silicon on insulator substrates have been prepared by integrating gadolinium scandate as high-κ gate dielectric in a gate last process. The GdScO₃ films were deposited by electron beam evaporation and subsequently annealed in oxygen atmosphere. Electrical characterization of readily processed devices reveals well behaved output and transfer characteristics with high I _on/I _off ratios of 10⁶–10⁸, and steep inverse subthreshold slopes down to 66 mV/dec. Carrier mobilities of 155 cm²/Vs for the conventional and 366 cm²/Vs for the strained silicon substrates were determined.     

Investigation of black phosphorus field-effect transistors and its stability

In this paper, the electrical properties of black phosphorus(BP) are investigated. Back-gated field-effect transistors (FETs) array with different channel length are fabricated on the same BP nanoflake. The device exhibits high current on/off ratio (5 × 10³), high field-effect mobility (130 cm² V^?1 s^?1) and low contact resistance (917 Ω μm). In addition, the stability of BP device is also explored. Results show that the 10 nm Al₂O₃ dielectric layer can effectively depress the exposure of BP flakes with air and then protect the BP devices from ambient degradation. There is no noticeable degradation in device performance for the devices with 10 nm Al₂O₃ passivating layer even after being exposed in air for 2 weeks.     

Improvement of electrical properties of silicon-based thin-film transistors by modifying technological fabrication processes

This paper is a review of technological process evolution associated to electrical performance improvement of silicon-based thin-film transistors (TFTs) that were performed mainly in the GM/IETR laboratory. The main objective in agreement with the fields of applications is to fabricate TFTs at a temperature low enough to be compatible with the substrates, glass substrates in a first place and flexible substrates in a second one, which implies several approaches. In fact, the electrical properties of the TFTs, mainly field-effect mobility of carriers in the channel, I _on/I _off drain current ratio, and subthreshold slope, are strongly dependent on the quality and the nature of the channel material, on the material quality and thus on the density of states at the interface with the gate insulator, and on the quality of the gate insulator itself. All the improvements are directly linked to all these aspects, which means an actual combination of the efforts. For the glass substrate, compatible technology processes such as deposition techniques, or solid phase, or laser crystallizations of active layers were studied and compared. The paper details all these approaches and electrical performances. In addition, some results about the use of a silicon–germanium compound as channel active layer and airgap transistors for which the insulator is released, complete the presentation of the evolution of the silicon-based TFTs during the last twenty years.     

Laser printing of polythiophene for organic electronics

We report on the development of hybrid organic/inorganic thin-film transistors using regioregular poly-3-hexylthiophene (P3HT) semiconductor material deposited by means of the solid-phase Laser Induced Forward Transfer (LIFT) technique. P3HT pixels were LIFT-printed onto Au/Ti source and drain electrodes formed on silicon dioxide/p⁺-type Si substrate. Deposition of the P3HT pixels was investigated as a function of the laser fluence using donor substrates with and without a dynamic release layer. Device electrical characterization reveals efficient field-effect action of the bottom gate on the organic channel. The transfer I_DS-V_GS characteristics exhibit well-defined sub-threshold, linear and saturation regimes designating LIFT as a promising technique for hybrid organic/inorganic transistor technology.     

Mössbauer and XRD study of pulse plated Fe–P and Fe–Ni thin layers

⁵⁷Fe conversion electron Mössbauer spectroscopy, X-ray diffraction, electrochemical and magnetic measurements were used to study pulse electroplated Fe–P and Ni–Fe coatings. XRD and ⁵⁷Fe CEMS measurements revealed the amorphous character of the novel pulse plated Fe–P alloys. CEM spectra indicated significant differences in the short range order and in the magnetic anisotropy between the Fe–P deposits pulse plated at medium long deposition time (t _on?=?2 ms), with short relaxation time (t _off?=?9 ms) and low current density (I _p?=?0.05 Acm^?2) or at short deposition time (t _on?=?1 ms) with long relaxation time (t _off?=?250 ms) and high current density (I _p?=?1.0 Acm^?2). The broad peaks centred around the fcc reflections in XRD of the pulse plated Ni-22 wt.% Fe deposit reflected a microcrystalline Ni–Fe alloy with a very fine, 5–8 nm, grain size. The CEM spectrum of the pulse plated Ni-22 wt.% Fe coating corresponded to a highly disordered solid solution alloy containing a minute amount of ferrihydrite. Extreme favourable soft magnetic properties were observed with these Ni–Fe and Fe–P pulse plated thin layers.