Electronic properties of Z-shaped graphene nanoribbon under uniaxial strain

Based on tight-binding approximation and a generalized Green's function method, the effect of uniaxial strain on the electron transport properties of Z-shaped graphene nanoribbon (GNR) composed of an armchair GNR sandwiched between two semi-infinite metallic armchair GNR electrodes is numerically investigated. Our results show that the increase of uniaxial strain enhances the band gap and leads to a metal-to-semiconductor transition for Z-shaped GNR. Furthermore, in the Landauer–Büttiker formalism, the current–voltage characteristics, the noise power resulting from the current fluctuations and Fano factor of strained Z-shaped GNR are explored. It is found the threshold voltage for the current and the noise power increased so that with reinforcement of the uniaxial strain parameter strength, the noise power goes from the Poisson limit to sub-Poisson region at higher bias voltages.     

Manipulating edge current spin polarization in zigzag MoS2 nanoribbons

The electronic structure and quantum transport of a zigzag monolayer molybdenum disulfide (MoS₂) nanoribbon are investigated using a six-band tight-binding model. For metallic edge modes, considering both an intrinsic spin–orbit coupling and local exchange field effects, spin degeneracy and spin inversion symmetry are broken and spin selective transport is possible. Our model is a three-terminal field effect transistor with a circular-shaped gate voltage in the middle of scattering region. One terminal measures the top edge current and the other measures the bottom edge current separately. By controlling the circular gate voltage, each terminal can detect a totally spin-polarized edge current. The radius of the circular gate and the strength of the exchange field are important, because the former determines the size of the channel in both S-terminated (top) and Mo-terminated (bottom) edges and the latter is strongly related to unbalancing of the density of spin states. The results presented here suggest that it should be possible to construct spin filters using implanted MoS₂ nanoribbons.     

High-frequency single-electron transport in a quasi-one-dimensional GaAs channel induced by surface acoustic waves

We report on an experimental investigation of the direct current induced by transmitting a surface acoustic wave (SAW) with frequency 2.7 GHz through a quasi-one-dimensional (1D) channel defined in a GaAs - AlGaAs heterostructure by a split gate, when the SAW wavelength was approximately equal to the channel length. At low SAW power levels the current reveals oscillatory behaviour as a function of the gate voltage with maxima between the plateaux of quantized 1D conductance. At high SAW power levels, an acoustoelectric current was observed at gate voltages beyond pinch-off. In this region the current displays a step-like behaviour as a function of the gate voltage (or of the SAW power) with the magnitude corresponding to the transfer of one electron per SAW cycle. We interpret this as due to trapping of electrons in the moving SAW-induced potential minima with the number of electrons in each minimum being controlled by the electron - electron interactions. As the number of electrons is reduced, the classical Coulomb charging energy becomes the Mott - Hubbard gap between two electrons and finally the system becomes a sliding Mott insulator with one electron in each well.     

The effects of source/drain and gate overlap on the performance of carbon nanotube field effect transistors

At nanometer regime, fabricating the structures with non-overlapped channel and abrupt doping profile is very complicated and sometimes impossible. So, the resultant device experiences some non-ideal effects which have to be predicted and well addressed by simulation before fabrication. In this paper the effects of overlap between gate and source/drain regions on the performance of carbon nanotube field effect transistors have been investigated. The overlapped structure has been simulated with various doping profiles at drain/source and gate region junction tip. The device performance has been investigated in terms of ON current, Off current, ON/Off current ratio, subthreshold swing, delay, and power delay product (PDP). Simulations show that depending on the variations in the effective channel length, the overlap deteriorates some device characteristics and enhances the others. Where the effective channel length decreases (increases), the overlap deteriorates (enhances) the current ratio and subthreshold swing but enhances (deteriorates) the delay and PDP compared to non-overlapped structure. Furthermore, the overlapped structure with graded profile results in lower current ratio and higher subthreshold swing compared to overlapped structure with abrupt profile. At a fixed current ratio, the delay and PDP of overlapped structure with graded profile are more than overlapped structure with abrupt profile but at a fixed channel length, both profiles have approximately equal delay and PDP.     

Quantum-interference-controlled three-terminal molecular transistors based on a single ring-shaped molecule connected to graphene nanoribbon electrodes

We study molecular transistors where graphene nanoribbons act as three metallic electrodes connected to a ring-shaped 18-annulene molecule. Using the nonequilibrium Green function formalism combined with density functional theory, recently extended to multiterminal devices, we show that these nanostructures exhibit exponentially small transmission when the source and drain electrodes are attached in a configuration with destructive interference of electron paths around the ring. The third electrode, functioning either as an attached infinite-impedance voltage probe or as an "air-bridge" top gate covering half of molecular ring, introduces dephasing that brings the transistor into the "on" state with its transmission in the latter case approaching the maximum limit for a single conducting channel device. The current through the latter device can also be controlled in the far-from-equilibrium regime by applying a gate voltage.     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

部分耗尽结构绝缘体上硅器件的低频噪声特性

针对部分耗尽结构绝缘体上硅(silicon-on-insulator, SOI)器件低频噪声特性展开实验与理论研究. 实验结果表明, 器件低频噪声主要来源于SiO₂-Si界面附近缺陷态对载流子的俘获与释放过程; 基于此理论可提取前栅和背栅氧化层界面附近缺陷态密度分别为8×10¹⁷ eV^-1·cm^-3和2.76×10¹⁷ eV^-1·cm^-3. 基于电荷隧穿机理, 在考虑隧穿削弱因子、隧穿距离与时间常数之间关系的基础上, 提取了前、背栅氧化层内缺陷态密度随空间的分布情况. 此外, SOI器件沟道电流归一化噪声功率谱密度随沟道长度的增加而线性减小, 这表明器件低频噪声主要来源于沟道的闪烁噪声. 最后, 基于电荷耦合效应, 分析了背栅电压对前栅阈值电压、沟道电流以及沟道电流噪声功率谱密度的影响.     

非对称Halo异质栅应变Si SOI MOSFET的二维解析模型

为了进一步提高深亚微米SOI (Silicon-On-Insulator) MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) 的电流驱动能力, 抑制短沟道效应和漏致势垒降低效应, 提出了非对称Halo异质栅应变Si SOI MOSFET. 在沟道源端一侧引入高掺杂Halo结构, 栅极由不同功函数的两种材料组成. 考虑新器件结构特点和应变的影响, 修正了平带电压和内建电势. 为新结构器件建立了全耗尽条件下的表面势和阈值电压二维解析模型. 模型详细分析了应变对表面势、表面场强、阈值电压的影响, 考虑了金属栅长度及功函数差变化的影响. 研究结果表明,提出的新器件结构能进一步提高电流驱动能力, 抑制短沟道效应和抑制漏致势垒降低效应, 为新器件物理参数设计提供了重要参考. 关键词： 非对称Halo 异质栅 应变Si 短沟道效应     

多层石墨烯纳米带光电探测器理论与性能分析

多层石墨烯具有超宽的光谱吸收范围及独特的光电性能,是制作下一代光电探测器件的理想材料。以石墨烯的带间隧穿理论为基础,提出了一个多层石墨烯纳米带结构的光电探测器模型,纳米带的两端与源极和漏极相连,夹在半导体基质和上下栅极之间。利用这个模型,建立了多层石墨烯纳米带探测器的光电转换机制,讨论了上栅极电压不同时探测器的工作原理,研究了源-漏极间光电流及暗电流与入射光能量的关系,探讨了探测器的偏置电压,耗尽层长度以及带隙取值对暗电流的影响,并分析了不同参数下探测器响应率以及探测率随入射光能量的变化关系。结果表明,探测器的响应率随纳米带层数的增加而增加,受带隙,耗尽层长度和偏置电压的影响,最大的响应率约为103 A·W-1; 通过限制上栅压,带隙等变量可以控制系统暗电流,增大探测器的探测率,最高探测率约为109 cm·Hz1/2·W-1。多层石墨烯纳米带结构可以增强探测器对入射光的吸收,提高探测器的灵敏度以及对弱光的探测能力,实现对太赫兹到远红外波段入射光的有效探测,探测性能远高于许多量子结构和窄带半导体结构的光电探测器。     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

An analytical study of substrate current in submicron MOS devices

In the present communication we have tried to study the substrate current behavior in the sub-micron devices after solving the second order differential equation using appropriate boundary conditions. Simple and accurate models for maximum lateral field, drain saturation voltage and for ionization length have been developed. The simulation result of ionization length shows a good match with the known result. Analysis also shows that dominant contributor to the error in the ionization length is not only because of the excess saturated voltage but also due to the channel length and the gate to source voltage. For sub-micron devices the saturation region shifts towards the source for higher drain voltage and larger gate oxide thickness.Received: 27 September 2004, Published online: 26 November 2004PACS: 85.30.De Semiconductor-device characterization, design, and modeling - 85.30.Tv Field effect devices     

The role of metal contacts in the stability of n-type organic field effect transistors

We are presenting a long-time bias stress stability of C₆₀-based n-type organic field effect transistors (OFETs), in bottom gate, top contacts configuration, with aluminium (Al), silver (Ag) and gold (Au) source–drain contacts. The results clearly shows that the bias stress effects in C₆₀-based n-type OFETs is similar to p-type OFETs and it can be reduced by using an appropriate metal for the source–drain contacts. During the bias stress time, the threshold voltage shift and an increase in the contacts resistance have also been measured. On the basis of the stability of the device parameters, it is proposed that the Al source–drain contact-based devices gives better stability as compared to the devices with Ag and Au source–drain contacts. Our results show that the bias stress-induced threshold voltage shift is due to the trapping of charges in the channel region and in the vicinity of the source–drain contacts.     

A scheme for a topological insulator field effect transistor

We propose a scheme for a topological insulator field effect transistor. The idea is based on the gate voltage control of the Dirac fermions in a ferromagnetic topological insulator channel with perpendicular magnetization connecting to two metallic topological insulator leads. Our theoretical analysis shows that the proposed device displays a switching effect with high on/off current ratio and a negative differential conductance with a good peak to valley ratio.     

Electronic transport properties of metallic single-walled carbon nanotubes

We have calculated the differential conductance of metallic carbon nanotubes by the scatter matrix methon.It is found that the differential conductance of metallic nanotube-based devices oscillates as a function of the bias voltage between the two leads and the gate voltage.Oscillation period T is directly proportional to the reciprocal of nanotube length.In addition,we found that electronic transport properties are sensitive to variation of the length of the nanotube.     

Super tiny nanoscale graphene nanoribbon field-effect transistor

Carbon material, especially the graphene nanoribbon (GNR), is well-known for its exceptional transmission properties. Graphene has become one of the most promising alternative materials for solving problems of the density scaling determined by Moore’ law. Instead of designing the structure into Schottky contacts, our transistor controls the drain current on the atomic scale by doping B/N atoms. By a regular geometric doping atoms, a good transmission performance has been achieved on a small dimension for the first time. The footprint of our transistor is 2.55 nm, including a 1.7 nm channel length and 0.425 nm contact length, the size of the footprint is 16 times smaller than the most recent work. Furthermore, the transistor also shows acceptable properties in transmission. The drain current has a good linearity with the variation of V_gs, especially in the range of 0.8 V to 1.2 V and the range of 1.8 V to 2.1 V. The on/off current ratio is 0.64 × 10² and the on-stage current density is 9.87 mA/µm.     

Shrinking limits of silicon MOSFETs: numerical study of 10 nm scale devices

We have performed numerical modeling of dual-gate ballistic n-MOSFETs with channel length of the order of 10 nm, including the effects of quantum tunneling along the channel and through the gate oxide. Our analysis includes a self-consistent solution of the full (two-dimensional) electrostatic problem, with account of electric field penetration into the heavily doped electrodes. The results show that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4000 mS mm ^− 1or gate modulation of current by more than 8 orders of magnitude, depending on the gate oxide thickness. These characteristics make the devices satisfactory for logic and memory applications, respectively, although their gate threshold voltage is rather sensitive to nanometer-scale variations in the channel length.     

Channel length scaling and the impact of metal gate work function on the performance of double gate-metal oxide semiconductor field-effect transistors

In this paper, we study the effects of short channel on double gate MOSFETs. We evaluate the variation of the threshold voltage, the subthreshold slope, the leakage current and the drain-induced barrier lowering when channel length L _CH decreases. Furthermore, quantum effects on the performance of DG-MOSFETs are addressed and discussed. We also study the influence of metal gate work function on the performance of nanoscale MOSFETs. We use a self-consistent Poisson-Schrödinger solver in two dimensions over the entire device. A good agreement with numerical simulation results is obtained.     

60Co γ射线辐射对AlGaN/GaN HEMT器件的影响

采用⁶⁰Co γ射线辐射源对非钝化保护的AlGaN/GaN高电子迁移率晶体管(HEMT)器件进行了1 Mrad(Si)的总剂量辐射,实验发现辐射累积剂量越大,器件尺寸越小,器件饱和漏电流和跨导下降越明显,同时辐射后器件栅泄漏电流明显增大,而阈值电压变化很小. 对辐射前后器件的沟道串联电阻和阈值电压变化的分析表明,辐射感生表面态负电荷的产生是造成AlGaN/GaN HEMT器件电特性退化的主要原因之一. 关键词： AlGaN/GaN HEMT器件 γ射线辐射 表面态     

单晶金刚石氢终端场效应晶体管特性

基于微波等离子体化学气相淀积生长的单晶金刚石制作了栅长为2μm的耗尽型氢终端金刚石场效应晶体管,并对器件特性进行了分析.器件的饱和漏电流在栅压为-6 V时达到了96 mA/mm,但是在-6 V时栅泄漏电流过大.在-3.5 V的安全工作栅压下,饱和漏电流达到了77 mA/mm.在器件的饱和区,宽5.9 V的栅电压范围内,跨导随着栅电压的增加而近线性增大到30 mS/mm.通过对器件导通电阻和电容-电压特性的分析,氢终端单晶金刚石的二维空穴气浓度达到了1.99×10~(13)cm~(-2),并且迁移率和载流子浓度均随着栅压向正偏方向的移动而逐渐增大.分析认为,沟道中高密度的载流子、大的栅电容以及迁移率的逐渐增加是引起跨导在很大的栅压范围内近线性增加的原因.