一种应用于串行链路的5Gb/s低功耗电流模预加重发送器

A multi-standard compatible transmitter with pre-emphasis for high speed serial links is presented. Based on the comparison between voltage mode(VM) and current mode(CM) output driver architectures,a low power CM output driver with reverse scaling and bias current filtering technique is proposed.A 2-tap pre-emphasis filter is used to reduce the intersymbol interference caused by the low-pass channel,and a high speed,low power combined serializer is implemented to convert 10 bit parallel data into a serial data stream.The whole transmitter is fabricated in 65 nm 1.2 V/2.5 V CMOS technology.It provides an eye height greater than 800 mV for data rates of both 2.5 Gb/s and 5 Gb/s.The output root mean square jitter of the transmitter at 5 Gb/s is only 9.94 ps without pre-emphasis.The transmitter consumes 41.2 mA at 5 Gb/s and occupies only 240×140μm~2.     

Dual-time resolution time-based transceiver for low-power serial interfaces

This paper presents the design and analysis of a CMOS power amplifier (PA) with active 2nd harmonic injection at the input. In this circuit, the main amplifier operates in class-A to provide a high linearity performance, and the auxiliary one is a class-C high efficiency amplifier, which injects the 2nd harmonic into the main amplifier. Theoretical analysis and simulations show that the proposed technique improves the PA linearity, power added efficiency (PAE), and the output power. The auxiliary amplifier, also referred as injection amplifier, injects the 2nd harmonic to the main (core) amplifier in order to compensate the gain compression phenomena at the main amplifier output node. Moreover, waveform shaping is employed to decrease the overlap of voltage and current waveforms, resulting in PAE improvement. The fully integrated PA with 2nd harmonic injection was designed and simulated in 0.18 µm CMOS technology, with a center frequency of 2.6 GHz. Post-layout simulation of PA exhibits 31.25% PAE in maximum linearity point (1 dBC point), illustrating 12.3% improvement at this power level. The 1 dBC point of PA is improved by 3.2 dB, and the PA output power is 20.2 dBm using 3.3 V supply voltage.     

Precoded two-dimensional coding method for low-power serial bus

A precoded two-dimensional coding method is proposed for a low-power serial bus, which reduces the transition activity in time as well as in space without causing error propagation. In the conventional limited-weight codes for low-power I/O exploiting transition signalling, once single-bit random errors occur in noisy bus channels, they are propagated to subsequent signals (because the present signal level is dependent on the preceding signal level in time). The proposed method avoids this phenomenon by producing a precoded bit matrix. Furthermore it eliminates the need for additional hardware for the transition signalling     

Design techniques and test methodology for low-power TCAMs

Ternary content addressable memories (TCAMs) are gaining importance in high-speed lookup-intensive applications. However, the high cost and power consumption are limiting their popularity and versatility. TCAM testing is also time consuming due to the complex integration of logic and memory. In this paper, we present a comprehensive review of the design techniques for low-power TCAMs. We also propose a novel test methodology for various TCAM components. The proposed test algorithms show significant improvement over the existing algorithms both in test complexity and fault coverage.     

Circuit techniques for CMOS low-power high-performance multipliers

In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-μm CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMOS implementation. Although the circuits were optimized for (16×16)-b multiplier using the Booth algorithm, a (6×6)-b implementation was used as a test vehicle in order to reduce simulation time. For the (6×6)-b case, implementation based on CPL-TG resulted in 18% power savings and 30% speed improvement over conventional CMOS     

Dual-threshold voltage techniques for low-power digital circuits

Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation. This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks. MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented. A dual-V_t domino logic style that provides the performance equivalent of a purely low-V _t design with the standby leakage characteristic of a purely high-V_t implementation is also proposed     

An area-power efficient CMOS 4-PAM class AB current-mode pre-emphasis serial link transmitter

This paper presents an area-power efficient CMOS 4-PAM class AB current-mode pre-emphasis transmitter for multi-Gb/s serial links. The proposed transmitter minimizes both chip area and power consumption by constructing pre-emphasis symbols directly from the current symbol, eliminating the need for complex FIR filters and digital-to-analog converters. The differential output current obtained from a class AB pre-amplifier and the push-pull operation of both the current-symbol and pre-emphasis drivers minimizes the electromagnetic interference exerted by channels to neighboring devices. The use of latches at both the multiplexer and pre-amplifier minimizes the effect of power fluctuation and ground bouncing on the output current of the transmitter. The proposed transmitter has been implemented in both UMC-0.13 μm 1.2 V and TSMC-0.18 μm 1.8V CMOS technologies and analyzed using SpectreRF from Cadence Design Systems with BSIM3.3v device models. The effectiveness of the proposed transmitter architecture is validated from the simulation results of both designs.     

Class-AB techniques for high-dynamic-range microwave-photonic links

Class-AB techniques are analyzed as a means to minimize the noise associated with the residual carrier in analog optical links. A bound for shot and intensity noise is derived and compared to previously reported measurements. It is found that for an ideal modulator transfer function (Class B), a substantial improvement in shot-noise limited spur-free dynamic range (e.g., 11.7 dB at 10% modulation) can be realized.     

Phase assignment for synthesis of low-power domino circuits

High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs but domino logic comes at a heavy cost in terms of total power dissipation. A set of results related to automated phase assignment for the synthesis of low-power domino circuits is presented: (1) it is demonstrated that the choice of phase assignment at the primary outputs of a circuit can significantly impact lower dissipation in the domino block, and (2) a method to determine a phase assignment that minimises power consumption in the final circuit implementation is proposed. Preliminary experimental results on a mixture of public domain benchmarks and real industry circuits show potential power savings as high as 34% over the minimum area realisation of the logic. Furthermore, the low-power synthesised circuits still meet timing constraints     

A new power-efficient CDMA-based transmitter for high-speed serial links

Conventional CDMA serial links suffer from the drawback that the number of transmitters is limited to only two in practical implementations due to the reduced voltage spacing between adjacent logic states of the transmitted data. In this letter, we propose a new CDMA serial link architect that allows an arbitrary number of transmitters to transmit data over the same channel while keeping the voltage spacing between adjacent logic states of the transmitted data to be the same as that of 4 pulse-amplitude-modulation serial link transmmitters. The effectiveness of the proposed architect is validated using the simulation results of a serial link with four transmitters designed in an IBM 130 nm 1.2 V CMOS technology.     

Achievable rates in low-power relay links over fading channels

Relayed transmissions enable low-power communications among nodes (possibly separated by a large distance) in wireless networks. Since the capacity of general relay channels is unknown, we investigate the achievable rates of relayed transmissions over fading channels for two transmission schemes: the block Markov coded and the time-division multiplexed (TDM) transmissions. The normalized achievable minimum energy per bit required for reliable communications is derived, which also enables optimal power allocation between the source and the relay. The time-sharing factor in TDM transmissions is optimized to improve achievable rates. The region where relayed transmission can provide a lower minimum energy per bit than direct transmission, as well as the optimal relay placement for these two transmission schemes, are also investigated. Numerical results delineate the advantages of relayed, relative to direct, transmissions.     

A modified Park-Kim voltage-controlled ring oscillator for multi-Gbps serial links

This paper proposes a new multi-stage CMOS voltage-controlled ring VCO called modified Park-Kim ring VCO for multi-Gbps serial links. An in-depth comparative study of pros and cons of Park-Kim VCO and the modified Park-Kim VCO with both single and dual delay paths is given. We show that the modified Park-Kim VCO offers an improved oscillation frequency, large output voltage swing, comparable frequency tuning range and phase noise as compared with Park-Kim VCO proposed in [1, 2]. We further show that although the modified Park-Kim VCO with single delay path and that with dual delay path offer comparable oscillation frequencies when the number of stages of the VCOs is high, the former provides a large frequency tuning range and reduced circuit complexity. To verify performance improvement, both Park-Kim VCOs and the modified Park-Kim VCOs are implemented in TSMC’s-0.18 μm, 1.8 V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3.3 device models. Simulation results are presented.     

An area-power efficient 4-PAM full-clock 10-Gb/s CMOS pre-emphasis serial link transmitter

This paper presents a new area-power efficient 4-PAM full-clock CMOS pre-emphasis transmitter for 10-Gb/s serial links. The proposed transmitter reduces the chip area and power consumption by minimizing the number of digital-to-analog converters for 4-PAM signaling and pre-emphasis. In addition, a new full-clock scheme is proposed to double the data rate without increasing the sampling clock frequency. To assess the effectiveness of the proposed transmitter, a 8-to-1 serial link consisting of the proposed transmitter and a pair of terminated microstrip lines with a FR4 substrate has been implemented in TSMC 0.18 μm 1.8 V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3.3V transistor models that count for both device parasitics and second-order effects. Simulation results are presented.     

Design techniques of low-power embedded EEPROM for passive RFID tag

This paper presents an optimized embedded EEPROM design approach which has reduced the power significantly in a short-range passive RFID tag. The proposed array control circuit employs an improved structure to minimize the leakage of memory bit cells. With the proposed array circuit design, the passive RFID tag can operate drawing a low quiescent current. The RFID tag with the proposed EEPROM was fabricated in a standard 0.35-μm four-metal two-poly CMOS process. Measurement results show that the erasing/writing current is 45 μA, and reading current consumption is 3 μA with a supply voltage of 3.3 V. The data read time is 300 ns/bit.     

An edge-based dual adaptive decision feedback equalizer for Gbps serial links

This paper presents an adaptive edge-DFE for 2PAM Gbps serial links. The optimal tap coefficients of the DFE are obtained by minimizing the jitter of received data. Reference voltage for generating DFE error signal is also obtained iteratively using an edge-DFE like algorithm. Issues critical to the proposed adaptive edge-DFE are examined in detail. The effectiveness of the proposed adaptive edge-DFE has been validated using a 5 Gbps serial link designed in a 65 nm 1.2 V CMOS technology. The effect of PVT (process, voltage, and temperature) variations on the performance of the proposed DFE has also been investigated. Simulation results demonstrate that the DFE is capable of opening completely closed data eyes when the DFE is absent. Equalized data have 55 % vertical-opening and 86.5 % horizontal eye-opening with 25 ns adaption time.     

A low power 3.125 Gbps CMOS analog equalizer for serial links

A CMOS analog equalizer is designed to meet the different high speed communication specifications,such as USB 2.0,PCI-E and rapid IO.The proposed circuit architecture could facilitate the wide frequency scale ranging from 1 to 3.125 Gbps by adjusting the locations of pole and zero,so that the circuit can change its response accordingly as the channel characteristic alters.In order to balance the parasitic capacitors in the internal point,symmetric switches are addressed to generate the equal load for dif...     

一种用于3.125Gbps高速互连的低功耗模拟均衡器

设计了适用于多种高速通信指标(USB2.0, PCI-E,Rapid IO)的CMOS模拟均衡器. 提出的电路结构可以覆盖1Gbps到3.125Gbps的频率范围,频率的调节是通过调整均衡器的零极点位置而获得的,所以这个电路可以根据信道特性的不同来相应的调整系统的频率响应。为了平衡内部结点的寄生电容,对称开关分别用在了两个差分信号路径上以保持两个差分信号有相同的负载。该芯片采用0.13um CMOS 1P8M工艺,实际的面积为0.49 × 0.5 mm2。测试表明,该芯片经过3m RG-58同轴线缆和50cm 印制电路板走线之后,可以稳定的传输3.125Gbps的伪随机码流。芯片的整体功耗大约为14.4mW.     

A power-efficient 2-dimensional on-chip eye-opening monitor for Gbps serial links

This paper investigates the drawbacks of widely used rectangular eye-opening monitors (EOMs) and proposes a new power-efficient half hexagon EOM for Gbps serial links. The proposed EOM outperforms rectangular EOMs by providing a better control of data jitter at the edge of data eyes and by eliminating unnecessary errors flagged by rectangular EOMs. The effectiveness of the proposed EOM is evaluated using a serial link implemented in IBM 130 nm 1.2 V CMOS technology. For purpose of comparison, rectangular EOMs with the same data link are also designed and evaluated. The data links are analyzed using Spectre from Cadence Design Systems with BSIM 4 device models. Simulation results demonstrate that the proposed EOM provides a better detection of the violation of the minimum eye-opening mask over temperature range ?20 to 80 °C and at all process corners as compared with rectangular EOM, with 50 % reduction in power and silicon consumption.     

Design of low-power fast VCSEL drivers for high-density links in 90-nm SOI CMOS

The continuous decrease of the supply voltage to 1 V and below in CMOS makes the design of laser drivers a challenging task. Hence, a detailed comparison of three basic driver architectures, namely, common source (CS), CS with source degeneration, and source follower (SF) is presented using transistor models including short channel effects. Based on this comparison, two power-optimized driver topologies are implemented in a 90-nm silicon-on-insulator CMOS technology. The SF driver features a bandwidth of 18 GHz on a 50-/spl Omega/ load. The required chip area is only 140 /spl mu/m/spl times/140 /spl mu/m, which is very beneficial for high-density short-distance optical interconnects. This allows a data rate of 12.5 Gb/s at a bit error ratio of less than 10/sup -12/ to be achieved even with a 10-Gb/s oxide confined vertical-cavity surface-emitting laser (VCSEL). The power consumption is 27 mW. The drivers were optimized for maximal eye opening by applying a fast and accurate VCSEL model.