New multirate bandpass sigma-delta modulators

A new architecture for fourth- and sixth-order bandpass sigma-delta (BP-SD) modulators is proposed here. The basic BP-SD modulator is obtained from its low-pass (LP) counterpart by means of the standard transformation z/sup -1/ /spl rarr/ -z/sup -2/, which transforms the integrators in the LP modulator into resonators in the BP modulator, and places the input signal band at the frequency f/sub s//4, where f/sub s/ is the sampling rate. In the proposed architecture, the second resonator (and the third one for the sixth-order case) is implemented using a two-path strategy, by means of two high-pass filters (whose poles are located at f/sub s//2) operating in a time-interleaved mode. However, unlike other BP-SD modulators using the two-path strategy, in our approach, the effective sampling frequency in the second resonator (and in the third one for the sixth-order case) is increased to 2/spl middot/f/sub s/ by maintaining the clock rate of the high-pass filters to f/sub s/ which, in turn, places their poles at f/sub s//2. The signal band in the input of the second resonator is moved from the center frequency f/sub s//4 to f/sub s//2 by a modulation process that separates the signal into their in-phase and quadrature components. Another demodulation process in the digital domain reverses this frequency translation of the signal band before the output signal is converted to the analog domain and fed back to the modulator input. A detailed theoretical analysis of the architecture is done in the paper. Owing to the multirate nature of the proposed modulators, simulation results show an improvement of approximately 12 dB in the input dynamic range (fourth-order case) when compared to conventional modulators of the same order clocked at the same frequency rate (in the first resonator).     

Robust dual-quantisation multibit sigma-delta modulator

A new dual-quantisation sigma-delta modulator is proposed, which introduces an additional feedback path in the input of the second integrator. In this way, unlike other dual-quantisation architectures, larger signal-to-noise ratios can be obtained by means of aggressive noise-shaping, like in a conventional multibit modulator. The proposed modulator is also shown to be more robust against non-idealities than other dual-quantisation architectures.     

Fast simulation of sigma-delta modulators using SPICE

Presents a fast simulation method using SPICE. We traded the prohibitive time-consuming simulation problem for a much less time-consuming problem, plus a little analysis work. This makes it possible for one to use SPICE simulation to optimize the parameters in the modulator within a reasonable time period. Rounding and truncation errors within the circuit simulation algorithms typically set an upper limit on the measurable SNR on the order of 90 dB. This implies that very high-resolution modulators cannot correctly be simulated by SPICE. Fortunately, 90 dB resolution is adequate for most modern communication baseband A/D converters     

A multibit sigma-delta ADC for multimode receivers

A 2.7-V sigma-delta modulator with a 6-bit quantizer is fabricated in a 0.18-/spl mu/m CMOS process. The modulator makes use of noise-shaped dynamic element matching (DEM) and quantizer offset chopping to attain high linearity over a wide bandwidth. The DEM algorithm is implemented in such a way as to minimize additional delay within the feedback loop of the modulator, thereby enabling the use of the highest resolution quantizer yet reported in a multibit sigma-delta analog-to-digital converter of this speed. The part achieves 95-dB peak spurious-free dynamic range and 77-dB signal-to-noise ratio over a 625-kHz bandwidth, and consumes 30 mW at a sampling frequency of 23 MHz. The part achieves 70-dB signal-to-noise ratio over a 1.92-MHz bandwidth and dissipates 50 mW when clocked at 46 MHz.     

New properties of sigma-delta modulators with DC inputs

New properties of single- and double-loop sigma-delta modulators with constant inputs are derived by exploiting the inherent structure os the output sequences or codewords that the modulators are capable of producing. Upper bounds are derived on the number of N-bit codewords for the single- and double-loop modulators. Analytical lower bounds on the mean squared error (MSE) obtainable by any decoder, linear or nonlinear, in approximating the constant input are also derived. Optimal nonlinear decoders for constant inputs based on a table lookup approach which operates directly on the nonuniform quantization intervals are considered. Using simulations is is found that the optimal nonlinear decoders perform better than linear decoders, by about 3 and 20 dB for the single- and double-loop modulators, respectively. A cascade structure specifically for constant inputs is introduced, and its corresponding decoding algorithm is derived. It is shown that for a fixed latency, the MSE performance of the cascade structure is 12 dB superior, and its throughput is twice that of the conventional two-stage MASH modulator     

A high resolution multibit sigma-delta modulator with individuallevel averaging

A second-order sigma-delta modulator with a 3-b internal quantizer employing the individual level averaging technique has been designed and implemented in a 1.2 μm CMOS technology. Testing results show no observable harmonic distortion components above the noise floor. Peak S/(N+D) ratio of 91 dB and dynamic range of 96 dB have been achieved at a clock rate of 2.56 MHz for a 20 kHz baseband. No tone is observed in the baseband as the amplitude of a 10 kHz input sine wave is reduced from -0.5 dB to -107 dB below the voltage reference. The active area of the prototype chip is 3.1 mm² and it dissipates 67.5 mW of power from a 5 V supply     

Stochastic resonance in sigma-delta modulators

Occurrence of the stochastic resonance phenomenon in sigma-delta modulators is reported. It is shown that when the internal quantiser of a /spl Sigma//spl Delta/-modulator comprises a multitude of comparators and noise sources, the system exhibits improved performance for a certain amount of added noise.     

The design of high-order bandpass sigma-delta modulators using low-spread single-stage structure

A structure for single-stage high-order bandpass sigma-delta modulators (BPSDMs) is presented. The proposed structure introduces an additional internal path in each resonator, thus, adding one degree of freedom in coefficient determination. Coefficient spread can therefore be reduced, resulting in significantly reduced capacitance area in switched-capacitor BPSDM circuits. High-order BPSDMs with different quality factors (Q) are demonstrated. It shows that coefficient spread is significantly reduced, especially for high-Q applications. For comparable eighth-order 3-bit BPSDMs, the maximum coefficient spread are respectively 15369 and 7693 for conventional cascade-of-resonator-with-feedback (CRFB) and cascade-of-resonator-with-feedforward (CRFF) designs, and 114 for the proposed structure. For an eighth-order 1-bit example, these respective values are 8994, 2638, and 74. With coefficient mismatch, peak signal-to-noise ratio (PSNR) degradation of the proposed structure is less than those of the CRFB and CRFF structures, demonstrating reduced sensitivity to component mismatch. Hence, the proposed structure can reduce chip area and ease circuit implementation of BPSDMs.     

A 19-bit low-power multibit sigma-delta ADC based on data weightedaveraging

This paper describes a low-power multibit sigma-delta analog-to-digital converter (ADC) which achieves 19-b resolution. Multibit quantization and feedback within a sigma-delta loop are shown to provide a power-efficient solution for high-resolution converters. As the linearity of the digital-to-analog converter (DAC) in the feedback path is a critical issue, a comparison of different DAC solutions is made demonstrating the efficiency of the data weighted averaging algorithm. An implementation of this technique within a monolithic sigma-delta ADC is then described. The whole chip, including the digital decimation filter, consumes only 2.7 mW for an 800-Hz output rate. The resolution and linearity improvement brought by data weighted averaging is confirmed by measurements     

Two-path structure for high performance sigma-delta modulators

A new parallel time-interleaved architecture for a two-path second-order switched-capacitor (SC) sigma-delta modulator is presented. This structure allows doubling of the oversampling sampling ratio (OSR) and, in addition, leaves an idle clock phase available for compensation of nonidealities. Simulations show that the presented architecture has a low sensitivity to path mismatch     

A new dithering method for sigma-delta modulators

A new dithering method to remove limit-cycles in Sigma-Delta modulators is presented. With this new method, the sequence length of a Pseudo-Noise generated dither is matched to the digital decimation filter. This causes the frequency spikes of the dither to coincide with the notches of the filter which results in total elimination of the applied dither power. In contrast to existing dithering techniques, matched dithering will not introduce additional inband noise. Compared to existing dithering techniques, the required dither amplitudes are relatively small (5%–30% FS) and may decrease with increasing oversampling ratio. Matched dithering proves to be very powerful for instrumentation applications.     

Efficient dithering of sigma-delta modulators with adaptive bitflipping

A new technique is presented for dithering single bit sigma-delta modulator (SDM) A/D and D/A converters in the digital domain. The system operates by detecting and randomising the limit cycle oscillations responsible for baseband tones. The system is efficient to implement in hardware and does not surfer from the analogue dither that is required in conventional SDM A/D converters     

Digital noise-shaping of residues in dual-quantization sigma-delta modulators

A new dual-quantization Sigma-Delta modulator is proposed in this paper where the coarse-quantizer output, obtained from the fine-quantizer output by means of a digital noise-shaping coder, is fed back to the input of the first integrator by means of a p-bit digital-to-analog converter (DAC) (typically, p=1). To avoid the truncation error inserted into the first integrator to propagate to the rest of integrators, the residue of the digital coder is first integrated and then fed to the second integrator through an additional multibit DAC. Unlike other dual-quantization architectures, the proposed one allows to obtain a large signal-to-noise plus distortion ratio by using aggressive noise transfer functions, like in conventional multibit modulators. Mismatch effects on performances are carefully analyzed. It will be shown that more than one digital coder can be included in the architecture in order to reduce the number of bits of the additional DAC. Simulation results are presented which support the theoretical analysis.     

A time-domain noise-coupling technique for continuous-time sigma-delta modulators

In this paper, a time-domain noise-coupling technique based on the pulse width modulation is proposed. The time-domain quantization error is digitally extracted and shaped by an asynchronous digital filter. This digitally filtered quantization error is applied to the quantizer input to increase the modulator’s noise-shaping order. By using this technique in continuous-time sigma-delta modulators, the modulator’s shaping property is significantly enhanced. Comparative analytical calculations and simulation results are presented to estimate the performance of modulators employing the proposed quantizer. System-level simulation results reveal a (L + 2)th order noise-shaping capability of the proposed modulator while it employs only L analog integrators. The effects of main circuit non-idealities in the modulator’s performance are analytically investigated and confirmed by the simulation results.     

Optimum selection of capacitive array for multibit Sigma-Delta modulators without DEM

A method for a smart selection and sequencing of unity capacitors in a multibit digital-to-analog converter (DAC) that improves the linearity is proposed. The approach, suitable for the DAC nonlinearity correction in Sigma-Delta modulators, obtains better results than dynamic element matching. The key of the proposed technique is an off-line self-measurement of mismatches with the available hardware. The results significantly improve when redundant DAC capacitors are introduced. Hence, the capacitors are selected from a set that is larger than required. An affordable silicon area overhead introduced by the redundant capacitors avoids extra power consumption, that is unavoidable in other methods during the normal operation of the converter.     

A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/Dconversion

The authors examine the application of oversampling techniques to analog-to-digital conversion at rates exceeding 1 MHz. A cascaded multibit sigma-delta (ΣΔ) modulator that substantially reduces the oversampling ratio required for 12-b conversion while avoiding stringent component matching requirements is introduced. Issues concerning the design and implementation of the modulator are presented. At a sampling rate of 50 MHz and an oversampling ratio of 24, an implementation of the modulator in a 1-μm CMOS technology achieves a dynamic range of 74 dB at a Nyquist conversion rate of 2.1 MHz. The experimental modulator is a fully differential circuit that operates from a single 5-V power supply and does not require calibration or component trimming     

Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators

This paper introduces a possible compensation for finite gain-bandwidth (GBW) induced errors in continuous-time sigma-delta modulators. Therefore, a novel model is derived which reduces the effect of a finite GBW to a corresponding integrator gain-error and feedback loop delays. Thus, previously published methods for the compensation of these errors can be adopted with some modification. The results are confirmed analytically and by simulations and show a possible GBW reduction of about one order of magnitude compared to current designs.     

Exact design of continuous-time sigma-delta modulators with multiple feedback DACs

A technique for the exact design of the noise transfer function of Continuous-Time (CT) Sigma-Delta modulators with arbitrary and multiple DAC responses and real op-amps is here presented. The approach, that presupposes linear behavior of active blocks, produces a CT modulator with the same noise shaping as its Discrete-Time counterpart. The method operates entirely in the time domain and accounts for non-idealities of real implementations such as finite gain and bandwidth of integrators. The procedure can be effectively implemented with circuit simulators to allow the exact design with transistor level blocks. A design example on a third-order scheme confirms the effectiveness of the method.     

On limit cycles of second-order sigma-delta modulators with constant input

Exact analysis of second-order sigma-delta modulators with constant input is presented. Some properties of general limit cycles are established. Sufficient conditions for the existence of a general class of limit cycles of the state vectors of the modulator are determined. The conditions interrelate the input, an initial vector, and the period of the limit cycle. Also, sufficient conditions are determined for a class of initial condition vectors to converge to a limit cycle.