Fabrication and investigation of ferroelectric memristors with various synaptic plasticities

In the post-Moore era, neuromorphic computing has been mainly focused on breaking the von Neumann bottlenecks. Memristors have been proposed as a key part of neuromorphic computing architectures, and can be used to emulate the synaptic plasticities of the human brain. Ferroelectric memristors represent a breakthrough for memristive devices on account of their reliable nonvolatile storage, low write/read latency and tunable conductive states. However, among the reported ferroelectric memristors, the mechanisms of resistive switching are still under debate. In addition, there needs to be more research on emulation of the brain synapses using ferroelectric memristors. Herein, Cu/PbZr_0.52Ti_0.48O₃ (PZT)/Pt ferroelectric memristors have been fabricated. The devices are able to realize the transformation from threshold switching behavior to resistive switching behavior. The synaptic plasticities, including excitatory post-synaptic current, paired-pulse facilitation, paired-pulse depression and spike time-dependent plasticity, have been mimicked by the PZT devices. Furthermore, the mechanisms of PZT devices have been investigated by first-principles calculations based on the interface barrier and conductive filament models. This work may contribute to the application of ferroelectric memristors in neuromorphic computing systems.     

Optimization of broadband RF performance and ESD robustness by π-model distributed ESD protection scheme

Large electrostatic discharge (ESD) protection devices close to the I/O pins, beneficial for ESD protection, have an adverse effect on the performance of broadband radio-frequency (RF) circuits for impedance mismatch and bandwidth degradation. A new proposed ESD protection structure, $\pi$-model distributed ESD ($\pi$-DESD) protection circuit, composed of one pair of ESD devices near the I/O pin, the other pair close to the core circuit, and a coplanar waveguide with under-grounded shield (CPWG) connecting these two pairs, can successfully achieve both excellent ESD robustness and good broadband RF performance. Cooperating with the active power-rail ESD clamp circuit, the experimental chip in a 0.25-μm CMOS process can sustain the human-body-model (HBM) ESD stress of 8 kV.     

某型无人机收发信机静电放电防护加固

无人机交换机芯片易被静电放电(ESD)电磁脉冲损坏,严重影响无人机数据链正常通信。针对此问题,通过搭建人体-金属ESD电路模型并进行仿真分析,发现所选用的TVS防护器件对15 kV等级的ESD防护效果显著。分别对加装TVS防护器件前后的收发信机电路进行了ESD电磁脉冲抗扰度对比试验。试验结果表明,加装防护器件后的电路对ESD电磁脉冲的防护能力最大提升7.4倍。     

Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 μm CMOS process

ESD protection for radio frequency (RF) applications must deal with good ESD performance, minimum capacitance, zero series resistance and good capacitance linearity. In order to fulfill these requirements, different ESD protection strategies for RF applications have been investigated in a 0.18 μm CMOS process. This paper compares different ESD protection devices and shows that a suitable ESD performance target for RF applications (200 fF max, 2 kV HBM) can be reached with a diode network scheme. The optimization of the diodes is then a key point which is detailed. A trade-off has to be found between the ESD performance, the voltage drop during ESD and the parasitic capacitance. Poly as well as shallow trench isolation (STI) bounded diodes have been studied and it appears clearly that a solution based on poly bounded diodes is the best choice.     

传输线长度对静电放电防护器件性能测试的影响

为了研究传输线长度对静电放电防护器件性能测试结果的影响,建立了静电放电模型和传输线脉冲模型两种试验系统,对某限压型防护器件进行了快沿电磁脉冲注入试验,并进行了理论分析。结果表明:传输线长度对静电放电防护器件性能测试结果具有极大影响,选用不当会导致错误结论;在对静电放电防护器件性能测试时,应优先采用传输线脉冲测试法;当采用静电放电脉冲测试法时,其传输线长度不应小于8 m。     

基于忆容器件的神经形态计算研究进展

人工智能的快速发展需要人工智能专用硬件的快速发展,受人脑存算一体、并行处理启发而构建的包含突触与神经元的神经形态计算架构,可以有效地降低人工智能中计算工作的能耗.记忆元件在神经形态计算的硬件实现中展现出巨大的应用价值;相比传统器件,用忆阻器构建突触、神经元能极大地降低计算能耗,然而在基于忆阻器构建的神经网络中,更新、读取等操作存在由忆阻电压电流造成的系统性能量损失.忆容器作为忆阻器衍生器件,被认为是实现低耗能神经网络的潜在器件,引起国内外研究者关注.本文综述了实物/仿真忆容器件及其在神经形态计算中的最新进展,主要包括目:前实物/仿真忆容器原理与特性,代表性的忆容突触、神经元及神经形态计算架构,并通过总结近年来忆容器研究所取得的成果,对当前该领域面临的挑战及未来忆容神经网络发展的重点进行总结与展望.     

Emerging of two-dimensional materials in novel memristor

The rapid development of big-data analytics (BDA), internet of things (IoT) and artificial intelligent Technology (AI) demand outstanding electronic devices and systems with faster processing speed, lower power consumption, and smarter computer architecture. Memristor, as a promising Non-Volatile Memory (NVM) device, can effectively mimic biological synapse, and has been widely studied in recent years. The appearance and development of two-dimensional materials (2D material) accelerate and boost the progress of memristor systems owing to a bunch of the particularity of 2D material compared to conventional transition metal oxides (TMOs), therefore, 2D material-based memristors are called as new-generation intelligent memristors. In this review, the memristive (resistive switching) phenomena and the development of new-generation memristors are demonstrated involving grapheme (GR), transition-metal dichalcogenides (TMDs) and hexagonal boron nitride (h-BN) based memristors. Moreover, the related progress of memristive mechanisms is remarked.     

Comprehensive ESD protection approach in advanced CMOS SOI technologies

In this paper we describe a 90 nm SOI ESD protection network and design methodology including both device and circuit level characterization data. We compare TLP results of SOI MOSFETs and diodes to bulk devices. We present a new response surface method to optimize device sizes in the ESD networks and show circuit level data comparing TLP test results and SPICE simulation results of an I/O test circuit. We also present product test data for standard ESD stress models.     

Design and investigation of novel ultra-high-voltage junction field-effect transistor embedded with NPN

Ultra-high-voltage(UHV) junction field-effect transistors(JFETs) embedded separately with the lateral NPN(JFETLNPN), and the lateral and vertical NPN(JFET-LVNPN), are demonstrated experimentally for improving the electrostatic discharge(ESD) robustness. The ESD characteristics show that both JFET-LNPN and JFET-LVNPN can pass the 5.5-k V human body model(HBM) test. The JFETs embedded with different NPNs have 3.75 times stronger in ESD robustness than the conventional JFET. The failure analysis of the devices is performed with scanning electron microscopy, and the obtained delayer images illustrate that the JFETs embedded with NPN transistors have good voltage endurance capabilities. Finally,the internal physical mechanism of the JFETs embedded with different NPNs is investigated with emission microscopy and Sentaurus simulation, and the results confirm that the JFET-LVNPN has stronger ESD robustness than the JFET-LNPN,because the vertical NPN has a better electron collecting capacity. The JFET-LVNPN is helpful in providing a strong ESD protection and functions for a power device.     

源、漏到栅距离对次亚微米ggNMOS ESD保护电路鲁棒性的影响

基于对静电放电(electrostatic discharge,ESD)应力下高电压、大电流特性的研究,本文通过优化晶格自加热漂移-扩散模型和热力学模型,并应用优化模型建立了全新的0.6 μm CSMC 6S06DPDM-CT02 CMOS工艺下栅接地NMOS (gate grounded NMOS,ggNMOS)ESD保护电路3D模型,对所建模型中漏接触孔到栅距离(drain contact to gate spacing,DCGS)与源接触孔到栅距离(source contact to gate sp 关键词： 栅接地NMOS 静电放电 漏接触孔到栅的距离 源接触孔到栅的距离     

Nanoscale resistive switches: devices,fabrication and integration

With CMOS scaling approaching its limits, there is a great need for advancements in novel devices, disruptive fabrication technologies, advanced materials and alternative computer architectures for future nanoelectronic systems. The emergence of memristive devices is one of promising solutions for the post-CMOS era. In this paper, we first introduce the fabrication of transition metal oxide based memristor cross-bars using nanoimprint lithography (NIL). The fabrication technique is further improved by using only one NIL step, reducing the fabrication efforts and improving the device performance. With shadow evaporation, a host of devices such as 2-terminal lateral memristors and 3-terminal memristive devices (memistors) are also demonstrated. By building memristor cross-bar arrays on foundry-made CMOS substrates using NIL, we have implemented hybrid nano/CMOS architecture. This hybrid chip provides an FPGA-like functionality with reconfigurable memristors defining data paths to wire logic gates into digital circuits. Future trends and issues with fabrication of memristive devices are also briefly discussed.     

Assessment of ESD threats to electronic components

Electrostatic discharge (ESD) is a major source of failures in electronic devices and products detected during manufacturing. Reduction of semiconductor element dimensions as well as implementation of new product and production technologies have made many devices extremely vulnerable to disturbances of electrostatic origin. Effective ESD damage prevention requires that ESD threats are carefully assessed and understood. This paper reviews new research results on electrostatic discharges as well as tools for the assessment of ESD threats to electronic components. Influences of the new results on the ESD control are discussed. There is a need to modify existing standards for the ESD control in electronics industry in order to meet challenges related to the manufacturing of future electronic products.     

忆阻器及其阻变机理研究进展

忆阻器是除电阻、电容、电感之外的第四种电路元件,在信息存储、逻辑运算和神经网络等研究领域具有重要的应用前景.本文综述了忆阻器以及忆阻器材料的研究进展,主要介绍了忆阻器的内涵与特征、阻变机理、材料类型以及应用前景,指出了目前忆阻器研究中需要关注的主要问题,并对以后的发展趋势进行了展望.     

Low capacitance ESD protection circuits for GaAs RF ICs

We present a novel electrostatic discharge (ESD) protection circuit for GaAs radio frequency (RF) integrated circuits (ICs), which are targeted for 10 Gb/s fiber-optic communication applications. The robustness, parasitic impedance, and loading effect of the new ESD protection circuit are studied and compared with the conventional diode-based ESD protection technique. Two versions of this type of ESD protection circuit were fabricated with a 60-GHz InGaP heterojunction bipolar transistor (HBT) technology. These two circuits can withstand, respectively, 2700 and 5000 V human body model (HBM) ESD stress and provide a similar level of ESD protection to RF ICs. The corresponding impedances of the off state are represented by an equivalent shunt capacitance and shunt resistance of 0.22 pF and 500 Ω, and 0.5 pF and 250 Ω, at 10 GHz. This ESD protection circuit can protect the 10 Gb/s RF ICs against much higher level ESD stress than conventional diode-based ESD protection circuits even with smaller size.     

InGaP/GaAs HBT DC-20 GHz distributed amplifier with compact ESD protection circuits

This paper presents design considerations and implementation of InGaP/GaAs HBT DC-20 GHz distributed amplifier with compact ESD protection circuits. The inherit benefits of both bandwidth and ESD robustness of distributed amplifiers are first compared to those of single-ended feedback amplifiers. Next, novel on-chip ESD protection circuits are introduced, featuring low capacitance loading for wide bandwidth, low leakage, and good linearity under high RF power. This paper discusses the principle of operation, ESD performance, and RF loading of the ESD protection circuits. The RF performance and ESD robustness of the distributed amplifier with the ESD protection circuits are also presented.     

Risks of damage to electronics with reference to charged clothing

Risks of damage to electronic devices with reference to charged clothing have been identified and quantified. The key parameters to control, in order to minimise the device failures due to electrostatic discharge (ESD), are peak ESD current and charge transfer in a direct discharge and device charging by induction and rubbing. An extensive experimental program was carried out to gain experience on threshold levels of these parameters. Use of ESD protective garments over normal clothes of operators is highly recommended in order to minimise ESD failures of devices. The ESD protective garments must be properly used and designed, otherwise they themselves form an ESD risk to electronics.     

静电放电火花产生的电磁场特征分析

静电放电(ESD)产生的电磁脉冲(EMP)会对电子系统的正常工作造成严重的干扰,甚至造成系统的损伤.故提出了一种修正的ESD火花电偶极子模型,并用此模型定性地分析了ESD火花产生的电磁场的特征,得出的-些结论对进一步研究ESD的电磁防护措施提供了有益指导.     

基于TLP建模的系统级静电放电效应仿真

系统级静电放电(ESD)效应仿真可以在电子系统进行测试之前进行有效的静电放电效应防护,缩短研发周期。根据传输线脉冲测试(TLP)结果,对瞬态电压抑制(TVS)二极管和芯片引脚进行spice行为建模,结合ESD脉冲源的等效电路模型,PCB板的S参数模型,采用场路协同技术完成了系统级静电放电效应的仿真。针对一个典型的电子系统,在IEC 61000-4-2 ESD应力作用下,完成了一款开关芯片防护电路的仿真,并对电路进行了加工、放电测试,仿真与测试芯片引脚的电压波形吻合良好,验证了该仿真方法的有效性。     

隧道场效应晶体管静电放电冲击特性研究

随着器件尺寸的不断减小,集成度的逐步提高,功耗成为了制约集成电路产业界发展的主要问题之一.由于通过引入带带隧穿机理可以实现更小的亚阈值斜率,隧道场效应晶体管(TFET)器件已成为下一代集成电路的最具竞争力的备选器件之一.但是TFET器件更薄的栅氧化层、更短的沟道长度容易使器件局部产生高的电流密度、电场密度和热量,使得其更容易遭受静电放电(ESD)冲击损伤.此外,TFET器件基于带带隧穿机理的全新工作原理也使得其ESD保护设计面临更多挑战.本文采用传输线脉冲的ESD测试方法深入分析了基本TFET器件在ESD冲击下器件开启、维持、泄放和击穿等过程的电流特性和工作机理.在此基础之上,给出了一种改进型TFET抗ESD冲击器件,通过在源端增加N型高掺杂区,有效的调节接触势垒形状,降低隧穿结的宽度,从而获得更好的ESD设计窗口.     

The influences of model parameters on the characteristics of memristors

As the fourth passive circuit component, a memristor is a nonlinear resistor that can "remember" the amount of charge passing through it. The characteristic of "remembering" the charge and non-volatility makes memristors great potential candidates in many fields. Nowadays, only a few groups have the ability to fabricate memristors, and most researchers study them by theoretic analysis and simulation. In this paper, we first analyse the theoretical base and characteristics of memristors, then use a simulation program with integrated circuit emphasis as our tool to simulate the theoretical model of memristors and change the parameters in the model to see the influence of each parameter on the characteristics. Our work supplies researchers engaged in memristor-based circuits with advice on how to choose the proper parameters.