大别山超高压硬玉石英岩中结构水的显微分析

“名义上无水矿物”（NAMs）可含有痕量的氢，其绝大多数都以羟基群的形式存在。无数NAMs的物理化学性质，如熔融行为、机械强度、电导率等都受痕量氢的影响。透辉石、普通辉石、霓石、绿辉石和斜方辉石中结构水的研究已受到众多学者的关注，并已成为国际研究的热点。但对辉石类矿物-硬玉中含水成分的研究甚少。Su Wen等（2004）结合红外光谱（IR）技术分析了大别山一些特定区域内硬玉石英岩中硬玉的结构水含量特征与其变形程度之间的密切关系。本项工作采用显微Fourier变换红外光谱仪（FTIR）对产自大别山双河和碧溪岭地区超高压硬玉石英岩中的“名义上无水矿物”（NAMs）硬玉（辉石）和石榴石中结构水的赋存状态进行了观察分析，计算结果表明它们都含有以OH^-或者H2O形式存在的氢，而且发现NAMs中结构水的分布并不均匀，硬玉中结构水平均含量均在1000ppm左右，石榴石结构水含量在900ppm～1600ppm之间，同时初步探讨了结构水在促进硬玉石英岩变形方面的效应。     

Au（Ru）-SiO2纳米-微米复合粒子的微观结构

金属或半导体纳米粒子在许多领域具有广阔而重要的应用前景，为降低纳米粒子间的团聚，以充分利用纳米颗粒的优异特性，而把金属或半导体纳米粒子掺杂在诸如玻璃或聚合体等基体中制备微纳复合颗粒的研究是近年来研究的热点。本研究以SiO2为基质，纳米金、钌功能粒子为镶嵌粒子，制备     

Zr-Si-N纳米晶复合膜的生长结构

近来,三元Me-Si-N复合膜因具有超硬效应而受到广泛关注。迄今为止大量研究集中于Ti-Si-N体系,其他体系报道较少。ZrN薄膜的力学性能与TiN薄膜相近,也是一种得到工业应用的硬质涂层材料。在ZrN薄膜中加入Si形成的Zr-Si-N复合膜可能具有良好的综合力学性能。现有关于Zr-Si-N复合膜的研究表明Si的加入能使薄膜得到强化,薄膜的强化可以归结为Si原子溶入ZrN晶格中所形成的固溶强化或形成了非晶Si3N4层分隔包裹三维ZrN纳米晶的微结构模型。本文研究了Si含量对Zr-Si-N复合膜微结构与力学性能的影响。     

超高压硬玉石英岩退变质矿物中的流体包裹体

矿物中的流体包裹体是矿物结晶过程中由晶体缺陷所封存的矿物介质体系，反映了地壳岩石在不同时期所经历的地质事件或地质过程。流体包裹体的研究对于了解岩石的形成条件、构造演化及动力学过程具有重要意义。近年来，我们利用透射电镜(TEM)和能量散射X射线谱仪(EDS)研究了大别山     

硬玉石英岩后成合晶矿物的显微构造研究

大别山高压超高压变质带的研究 ,已成为国内外地球科学研究的热点之一 ,并取得了一系列重要成果。但对大别非基性高压超高压硬玉石英岩矿物(如硬玉、石英、石榴石及金红石等 )的显微构造及超微结构的研究是一个薄弱环节 ,特别是对硬玉石英岩中由硬玉和石榴石退变质作用形成的后成合晶或后成合晶冠状体矿物 (如斜长石、绿闪石、霓辉石及金属矿物等 )的研究更少。该类后成合晶矿物中的化学成分及结构状态分布的非均一性、晶体缺陷及变形构造等复杂的地质特征能为揭示超高压变质岩的形成环境、变质变形作用及构造演化等提供重要信息。本项工作…     

超高压变质岩中几种出溶体的发现及其意义

关于超高压(UHP)变质岩形成深度问题的研究具有重要意义，因为了解折返至地壳超高压岩石的峰变质深度是讨论造山带深部变质作用、岩浆形成和流体活动的关键。一些高压一超高压条件下稳定的矿物固溶体出溶现象的发现，为超高压变质岩形成深度研究提供了重要的依据。作者在对大别     

Theoretical investigation of the electronic structure,optical, elastic,hardness and thermodynamics properties of jadeite

A detailed theoretical study of the electronic structure, optical, elastic and thermodynamics properties of jadeite have been performed by means of the first principles based on the state-of-the-art of density functional theory within the generalized gradient approximation. The optimized lattice constants and the atomic positions are in good agreement with experimental data. The total density of states and partial density of states of jadeite have been discussed. The energy gap has been calculated along the Γ direction found to be 5.338 eV, which shows that jadeite has wide direct band gap. The optical properties, such as the dielectric function, refractive index, extinction coefficient, reflectivity coefficient, loss function and absorption coefficient for [100] and [001] directions have been described for the first time in the energy range 0–40 eV. The elastic constants, bulk modulus, Young׳s modulus, anisotropic factor and Poisson׳s ratio have been calculated. Furthermore, the Vickers hardness and Debye temperature of jadeite have been predicted. The calculated values of all above parameters are compared with the available experimental values.     

纳米多层膜中立方AIN外延生长的HRTEM观察

以亚稳态存在的立方AIN具有很高的硬度、弹性模量、耐磨性、抗氧化性以及高温稳定性等优良的综合力学性能,是一种理想的硬质薄膜材料[1-3].     

Wafer level measurements and numerical analysis of self-heating phenomena in nano-scale SOI MOSFETs

We present an experimental technique and a Finite Element thermal simulation for the determination of the temperature elevation in Silicon on Insulator (SOI) MOSFETs due to self-heating. We evaluate the temperature elevation in two steps, as we calibrate the gate resistance over temperature with the transistor at off state at a first stage, and then we deduce the temperature elevation through gate resistance measurements. We simulate the self-heating phenomena in a Finite Elements Method (FEM) environment, both with 2D and 3D models. In order to set up the simulations, we weight the effects of several parameters, such as thermal material properties, the modeling of heat generation and a careful setting of boundary conditions. We present typical temperature fields and local heat fluxes, thus giving concrete indications for solving thermal reliability issues. Simulation results show temperature elevations up to approximately 120 K in the hot spot, 70 K in the gate and 7 K in the Back End of Line (BEoL). The 3D model gives results that are satisfying over the whole set of MOSFETs we consider in this work. Temperature elevation strongly depends on physical dimensions, where transistors endowed with shorter gates suffer from more severe self-heating. We propose a simplified model based on geometrical parameters that predict maximum and gate temperatures, obtaining satisfying results. Since correlation with measurements confirms the correctness of our model, we believe that our simulations could be a useful tool to determine accurate reliability rules and in a context of thermal aware design.     

Using self-assembly for the fabrication of nano-scale electronic and photonic devices

Challenges facing the scaling of microelectronics to sub-50 nm dimensions and the demanding material and structural requirements of integrated photonic and microelectromechanical systems suggest that alternative fabrication technologies are needed to produce nano-scale devices. Inspired by complex, functional, self-assembled structures and systems found in Nature we suggest that self-assembly can be employed as an effective tool for nanofabrication. We define a self-assembling system as one in which the elements of the system interact in pre-defined ways to spontaneously generate a higher order structure. Self-assembly is a parallel fabrication process that, at the molecular level, can generate three-dimensional structures with sub-nanometer precision. Guiding the process of self-assembly by external forces and geometrical constraints can reconfigure a system dynamically on demand. We survey some of the recent applications of self-assembly for nanofabrication of electronic and photonic devices. Five self-assembling systems are discussed: 1) self-assembled molecular monolayers; 2) self-assembly in supramolecular chemistry; 3) self-assembly of nanocrystals and nanowires; 4) self-assembly of phase-separated block copolymers; 5) colloidal self-assembly. These techniques can generate features ranging in size from a few angstroms to a few microns. We conclude with a discussion of the limitations and challenges facing self-assembly and some potential directions along which the development of self-assembly as a nanofabrication technology may proceed.     

Impact of NBTI on performance of domino logic circuits in nano-scale CMOS

Negative Bias Temperature Instability (NBTI) in pMOS transistors has become a major reliability concern in the state-of-the art digital circuit design. This paper discusses the effects of NBTI on 32 nm technology high fan-in dynamic OR gate, which is widely used in high-performance circuits. The delay degradation and power dissipation of domino logic, as well as the Unity Noise Gain (UNG), are analyzed in the presence of NBTI degradation. We have shown the degradation in the output inverter pMOS transistor of the domino gate has a dominant impact on the delay in comparison with the keeper impact. Based on this analysis we have proposed that upsizing just the output inverter pMOS transistor can compensate for the NBTI degradation. Moreover, the impact of tuning the duty cycle of the clock has been investigated. It has been shown that although the keeper and the precharge transistors experience more NBTI degradation by increasing the low level in the clock signal, the total performance of the circuit will improve. We have also proposed an adaptive compensation technique based on Forward Body Biasing (FBB), to recover the performance of the aged circuit.     

Use of nano-scale double-gate MOSFETs in low-power tunable current mode analog circuits

Use of independently-driven nano-scale double gate (DG) MOSFETs for low-power analog circuits is emphasized and illustrated. In independent drive configuration, the top gate response of DG-MOSFETs can be altered by application of a control voltage on the bottom gate. We show that this could be a powerful method to conveniently tune the response of conventional CMOS analog circuits especially for current-mode design. Several examples of such circuits, including current mirrors, a differential current amplifier and differential integrators are illustrated and their performance gauged using TCAD simulations. The topologies and biasing schemes explored here show how the nano-scale DG-MOSFETs may pave way for efficient, mismatch-tolerant and smaller circuits with tunable characteristics.     

Fabrication of ordered micro- and nano-scale patterns based on optical discs and nanoimprint

A simple method to fabricate one-dimensional(1-D) and two-dimensional(2-D) ordered micro- and nano-scale patterns is developed based on the original masters from optical discs, using nanoimprint technology and soft stamps. Polydimethylsiloxane(PDMS) was used to replicate the negative image of the 1-D grating pattern on the masters of CD-R, DVD-R and BD-R optical discs, respectively, and then the 1-D pattern on one of the PDMS stamps was transferred to a blank polycarbonate(PC) substrate by nanoimprint. The 2-D ordered patterns were fabricated by the second imprinting using another PDMS stamp. Different 2-D periodic patterns were obtained depending on the PDMS stamps and the angle between the two times of imprints. This method may provide a way for the fabrication of complex 2-D patterns using simple 1-D masters.