共查询到19条相似文献,搜索用时 15 毫秒
1.
A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM
A mixed-mode delay-locked loop (MDLL) for a 512 Mb graphics SDRAM is presented in this paper. The MDLL extends its lock range into the gigahertz realm by applying clock division and analog phase generation (APG). The divided clock from the MDLL is used for clocking logic and tracking deterministic access latency in the SDRAM. A short discussion of some of the side effects and advantages of using a divided, multi-phase clock for logic operation is presented. A low-power clock distribution network (CDN) based on the presented MDLL is also disclosed. Fabricated in a 1.5 V 95 nm triple-metal CMOS process, the MDLL achieves a measured RMS jitter of 4.6 ps and peak-to-peak jitter of 38 ps at GDDR4 mode with a 1 GHz clock. Power consumption for the entire MDLL-based CDN is 107 mW at 800 MHz and 1.5 V. 相似文献
2.
Kho R. Boursin D. Brox M. Gregorius P. Hoenigschmid H. Kho B. Kieser S. Kehrer D. Kuzmenka M. Moeller U. Petkov P.V. Plan M. Richter M. Russell I. Schiller K. Schneider R. Swaminathan K. Weber B. Weber J. Bormann I. Funfrock F. Gjukic M. Spirkl W. Steffens H. Weller J. Hein T. 《Solid-State Circuits, IEEE Journal of》2010,45(1):120-133
Modern graphics subsystems (gaming PCs, midhigh end graphics cards, game consoles) have reached the 2.6-2.8 Gb/s/pin regime with GDDR3/GDDR4, and experimental work has shown per pin rates up to 6 Gb/s/pin on individual test setups. In order to satisfy the continuous demand for even higher data bandwidths and increased memory densities, more advanced design techniques are required. This paper describes a 7 Gb/s/pin 1 Gb GDDR5 DRAM and the circuit design and optimization features employed to achieve these speeds. These features include: an array architecture for fast column access, a command-FIFO designed to take advantage of special training/tracking requirements of the GDDR5 interface, a boosting transmitter to increase read eye height, sampling receivers with pre-amplification and offset control, multiple regulated internal voltage (VINT = 1.3 V) domains to control on chip power noise, and a high-speed internal VINT power generator system. The memory device was fabricated in a conventional 75 nm DRAM process and characterized for a 7 Gb/s/pin data transfer rate at 1.5 V Vext. 相似文献
3.
Kwang-Jin Lee Beak-Hyung Cho Woo-Yeong Cho Sangbeom Kang Byung-Gil Choi Hyung-Rok Oh Chang-Soo Lee Hye-Jin Kim Joon-Min Park Qi Wang Mu-Hui Park Yu-Hwan Ro Joon-Yong Choi Ki-Sung Kim Young-Ran Kim In-Cheol Shin Ki-Won Lim Ho-Keun Cho Chang-Han Choi Won-Ryul Chung Du-Eung Kim Yong-Jin Yoon Kwang-Suk Yu Gi-Tae Jeong Hong-Sik Jeong Choong-Keun Kwak Chang-Hyun Kim Kinam Kim 《Solid-State Circuits, IEEE Journal of》2008,43(1):150-162
A 512 Mb diode-switch PRAM has been developed in a 90 nm CMOS technology. The vertical diode-switch using the SEG technology has achieved minimum cell size and disturbance-free core operation. A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are proposed. The 512 Mb PRAM has achieved read throughput of 266 MB/s through the proposed schemes. The write throughput was 0.54 MB/s in internal x2 write mode, and increased to 4.64 MB/s with x16 accelerated write mode at 1.8 V supply. 相似文献
4.
Kim K.-h. Chung H.-J. Kim W.-S. Park M. Jang Y.-C. Kim J.-Y. Park H.-W. Kang U. Coteus P. W. Choi J. S. Kim C. 《Solid-State Circuits, IEEE Journal of》2007,42(1):193-200
This paper proposes a deca-data rate clocking scheme and relevant I/O circuit techniques for a multi-Gb/s/pin memory interface. A deca-data rate scheme transmits 10 bits in one external clock cycle to transfer an error control code along with original data seamlessly without a timing bubble. A 288 Mb SDRAM has been designed using the proposed scheme combined with fast cycling core techniques to have both high I/O bandwidth and fast random cycling. Measured results show that the chip exhibits per-pin data rate of 8 Gb/s and row cycle time of 9.6 ns 相似文献
5.
Pilo H. Anand D. Barth J. Burns S. Corson P. Covino J. Lamphier S. 《Solid-State Circuits, IEEE Journal of》2003,38(11):1974-1980
This paper describes a 144-Mb DRAM that operates at a random cycle of 5.6 ns and is capable of producing data rates of 1.4 Gb/s/pin. The 121-mm/sup 2/ die is fabricated in a 0.13-/spl mu/m logic-based process with embedded DRAM. The cycle time is achieved using an early-write sensing technique that eliminates most of the timing overhead associated with the write cycle. Dynamic-precharge decoding in the subarray decode path is implemented to improve the access time. An improved data-formatting circuit is used to arrange the exit order of the eight-word burst. These circuit techniques produce latencies of 5.0 ns. The DRAM uses a DDR3-SRAM interface and is function and package compatible with industry-standard DDR3 SRAMs. Highlights of the DDR3 interface include the use of active termination circuitry on all inputs. The active termination improves the data-eye window and improves data capturing with minimum data setup and hold. 相似文献
6.
Zerbe J.L. Chau P.S. Werner C.W. Thrush T.P. Liaw H.J. Garlepp B.W. Donnelly K.S. 《Solid-State Circuits, IEEE Journal of》2001,36(5):752-760
A 1.6 Gb/s/pin 4-pulse-amplitude-modulated (PAM) multidrop signaling system has been designed. The motivation for multi-PAM signaling is discussed. The system uses single-ended+reference current-mode signaling with three dc references for maximum bandwidth per pin. A test chip with six I/O pins was fabricated in 0.35-μm CMOS and tested in a 28-Ω evaluation system using on-chip 210 pseudorandom bit sequence (PRBS) generator/checkers. Two different 4-PAM transmitter structures were designed and measured. A high-gain windowed integrating input receiver with wide common-mode range was designed in order to improve signal-to-noise ratio when operating with smaller 4-PAM input levels. Gray coding allowed a folded preamplifier architecture to be used in the LSB input receiver to minimize area and power. In-system margins are measured via system voltage and timing shmoos with a master communicating with two slave devices 相似文献
7.
《Solid-State Circuits, IEEE Journal of》2009,44(7):1927-1941
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《Solid-State Circuits, IEEE Journal of》2008,43(11):2492-2502
9.
Chih-Fan Liao Shen-Iuan Liu 《Solid-State Circuits, IEEE Journal of》2008,43(3):642-655
High-speed front-end amplifiers and CDR circuits play critical roles in broadband data receivers as the former needs to perform amplification at high data rate and the latter has to retime the data with the extracted low-jitter clock. In this paper, the design and experimental results of 40 Gb/s transimpedance-AGC amplifier and CDR circuit are described. The transimpedance amplifier incorporates reversed triple-resonance networks (RTRNs) and negative feedback in a common-gate configuration. A mathematical model is derived to facilitate the design and analysis of the RTRN, showing that the bandwidth is extended by a larger factor compared to using the shunt-series peaking technique, especially in cases when the parasitic capacitance is dominated by the next stage. Operating at 40 Gb/s, the amplifier provides an overall gain of 2 kOmega and a differential output swing of 520 mVpp with for input spanning from to . The measured integrated input-referred noise is 3.3muArms. The half-rate CDR circuit employs a direction-determined rotary-wave quadrature VCO to solve the bidirectional-rotation problem in conventional rotary-wave oscillators. This guarantees the phase sequence while negligibly affecting the phase noise. With 40 Gb/s 231 - 1 PRBS input, the recovered clock jitter is and 0.7psrms. The retimed data exhibits 13.3 pspp jitter with BER . Fabricated in 90 nm digital CMOS technology, the overall amplifier consumes 75 mW and the CDR circuit consumes 48 mW excluding the output buffers, all from a 1.2 V supply. 相似文献
10.
Ki-Won Lee Joo-Hwan Cho Byoung-Jin Choi Geun-Il Lee Ho-Don Jung Woo-Young Lee Ki-Chon Park Yong-Suk Joo Jae-Hoon Cha Young-Jung Choi Moran P.B. Jin-Hong Ahn 《Solid-State Circuits, IEEE Journal of》2007,42(11):2369-2377
Three circuit techniques for a 1.5 V, 512 Mb graphic DDR4 (GDDR4) SDRAM using a 90-nm DRAM process have been developed. First, a dual-clock system increases clocking accuracy and expands internal timing margins for harmonious core operation regardless of external clock frequency. Second, a four-phase data input strobe scheme helps to increase the input data valid window. Third, a fully analog delay-locked loop which provides a stable I/O clock and has 31.67 ps peak-to-peak jitter characteristics is designed. On the basis of these circuit techniques, the data rate is 3.2 Gbps/pin, which corresponds to 12.8 Gbps in times32 GDDR4-based I/O. Also, a multidivided architecture consisting of four independent 128 Mb core arrays is designed to reduce power line and output noise. 相似文献
11.
《Solid-State Circuits, IEEE Journal of》2009,44(11):2891-2900
12.
Villa C. Vimercati D. Schippers S. Polizzi S. Scavuzzo A. Perroni M. Gaibotti M. Sali M.L. 《Solid-State Circuits, IEEE Journal of》2008,43(1):132-140
This paper describes a 1.8 V, 1 Gb 2 b/cell NOR flash memory, based on time-domain voltage-ramp reading concept and designed in a 65 nm technology. Program method, architecture and algorithm to reach 2.25 MB/s programming throughput are also presented, as well as the read concept, allowing 70 ns random access time and a 400 MB/s sustained read throughput via a DDR interface. 相似文献
13.
Fujisawa H. Kubouchi S. Kuroki K. Nishioka N. Riho Y. Noda H. Fujii I. Yoko H. Takishita R. Ito T. Tanaka H. Nakamura M. 《Solid-State Circuits, IEEE Journal of》2007,42(1):201-209
Three circuit techniques for an 8.1-ns column-access 1.6-Gb/s/pin 512-Mb DDR3 SDRAM using 90-nm dual-gate CMOS technology were developed. First, an 8:4 multiplexed data-transfer scheme, which operates in a quasi-4-bit prefetch mode, achieves a 3.17-ns reduction in column-access time, i.e., from 11.3 to 8.13 ns. Second, a dual-clock latency counter reduces standby power by 22% and cycle time from 1.7 to 1.2 ns. Third, a multiple-ODT-merged output buffer enables selection of five effective-resistance values Rtt (20, 30, 40, 60, and 120 Omega) without increasing I/O capacitance. Based on these techniques, 1.6-Gb/s/pin operation with a 1.36-V power supply and a column latency of 7 was accomplished 相似文献
14.
A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link 总被引:1,自引:0,他引:1
《Solid-State Circuits, IEEE Journal of》2009,44(8):2085-2099
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16.
A high integrated monolithic IC,with functions of clock recovery,data decision,and 1∶4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiberoptic communications.The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data (2~31-1).The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data.The 0.97mm×0.97mm IC consumes 550mW under a single 3.3V power supply (not including output buffers). 相似文献
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18.
Suzuki A. Takahashi Y. Yoshida M. Nakazawa M. 《Photonics Technology Letters, IEEE》2007,19(19):1463-1465
We report a polarization-maintaining lambda/4-shifted distributed feedback (DFB) Er-doped fiber laser with a ring cavity configuration. The ring cavity suppressed the self-pulsation of the stand-alone Er-doped DFB fiber laser. The laser with a 57-m-long ring cavity achieved single-longitudinal-mode operation, a linewidth as narrow as 6 kHz, and relaxation-oscillation-free noise characteristics. 相似文献
19.
《IEEE transactions on circuits and systems. I, Regular papers》2009,56(11):2511-2518