Snapback应力引起的90 nm NMOSFET's栅氧化层损伤研究

实验结果发现突发击穿(snapback)，偏置下雪崩热空穴注入NMOSFET栅氧化层，产生界面态，同时空穴会陷落在氧化层中.由于栅氧化层很薄，陷落的空穴会与隧穿入氧化层中的电子复合形成大量中性电子陷阱，使得栅隧穿电流不断增大.这些氧化层电子陷阱俘获电子后带负电，引起阈值电压增大、亚阈值电流减小.关态漏泄漏电流的退化分两个阶段：第一阶段亚阈值电流是主要成分，第二阶段栅电流是主要成分.在预加热电子(HE)应力后，HE产生的界面陷阱在snapback应力期间可以屏蔽雪崩热空穴注入栅氧化层，使器件snapback开态和关态特性退化变小. 关键词： 突发击穿 软击穿 应力引起的泄漏电流 热电子应力     

Study on the drain bias effect on negative bias temperature instability degradation of an ultra-short p-channel metal-oxide-semiconductor field-effect transistor

This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) degradation during negative bias temperature (NBT) stress. When a relatively large gate voltage is applied, the degradation magnitude is much more than the drain voltage which is the same as the gate voltage supplied, and the time exponent gets larger than that of the NBT instability (NBTI). With decreasing drain voltage, the degradation magnitude and the time exponent all get smaller. At some values of the drain voltage, the degradation magnitude is even smaller than that of NBTI, and when the drain voltage gets small enough, the exhibition of degradation becomes very similar to the NBTI degradation. When a relatively large drain voltage is applied, with decreasing gate voltage, the degradation magnitude gets smaller. However, the time exponent becomes larger. With the help of electric field simulation, this paper concludes that the degradation magnitude is determined by the vertical electric field of the oxide, the amount of hot holes generated by the strong channel lateral electric field at the gate/drain overlap region, and the time exponent is mainly controlled by localized damage caused by the lateral electric field of the oxide in the gate/drain overlap region where hot carriers are produced.     

Hot-electron induced impact-ionisation damage at the interface of sub-micron silicon MOS devices: Model and monitor

It is well known that hot-carriers can cause damage to the interface of silicon MOS devices. Sub-micron and nano-channel nMOS devices have a higher electron temperature in the channel leading to increased impact-ionisation and enhanced interface degradation and damage. During dynamic operation of the nMOS device, hot-electron and hot-hole injections may take place giving rise to greater interface damage. Hot electrons produced due to impact ionisation also generate secondary electron-hole pairs in Si substrate. The visible light is generated by radiative recombination between the secondary hot electrons and hot holes. An optimised substrate current model was developed, the model was used to plot substrate current for a sub-micron nMOS transistor and was compared with the actual measurements carried out on similar device. It was found that the substrate current model can be used as a reliable monitor for impact ionisation damage in MOS devices.     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

Charge trapping phenomena in high-efficiency metal-oxide-silicon light-emitting diodes with ion-implanted oxide

This work is a comparative study of the processes of charge trapping in silicon dioxide layers doped with different rare-earth (RE) impurities (Gd, Tb, Er) as well as with Ge. Diode SiO₂-Si structures incorporating such oxide layers exhibit efficient electroluminescence (EL) in the spectral range of UV to IR. Ion implantation was performed over a wide dose range with the implant profiles peaking in the middle of the oxide. Charge trapping was studied using an electron injection technique in constant current regime with simultaneous measurements of the EL intensity (ELI). High-frequency C/V characteristics were used to monitor the net charge in the oxides.Analysis of the charge trapping and the variation of the EL intensity during electron injection shows that the current density range can be divided in three portions: (i) low injection level, where electron/hole capture at traps with large capture cross-sections and low ELI occurs; (ii) medium injection level corresponding to the main operation mode of the devices (odd hole trapping depending on the injected current level is observed); and (iii) high injection level (electrical quenching of the EL that correlates with electron capture at traps of extremely small capture cross-sections takes place). The nature of specific hole trapping at the medium injection level in RE-doped devices is discussed. Mechanisms of EL quenching at the high injection level are proposed.     

薄栅氧化层经时击穿的实验分析及物理模型研究

通过衬底热载流子注入技术,对薄SiO₂层击穿特性进行了研究.与通常的F-N应力实验相比较,热载流子导致的薄栅氧化层击穿显示了不同的击穿特性.通过计算注入到氧化层中的电子能量和硅衬底的电场的关系表明,热电子注入和F-N隧穿的不同可以用氧化层中电子的平均能量来解释.热空穴注入的实验结果表明薄栅氧化层的击穿不仅由注入的空穴数量决定.提出了全新的热载流子增强的薄栅氧化层经时击穿模型 关键词： 薄栅氧化层 经时击穿 衬底热载流子 击穿电荷 模型     

High-field-induced electron detrapping in An AlGaN/GaN high electron mobility transistor

A step stress test is carried out to study the reliability characteristics of an AlGaN/GaN high electron mobility transistor(HEMT).An anomalous critical drain-to-gate voltage with a negative temperature coefficient is observed in the stress sequence,beyond which the HEMT device starts to recover from degradation induced by early lower voltage stress.While the performance degradation featuring the drain current slump stems from electron trapping in the surface or bulk states during low-to-medium bias stress,the recovery is attributed to high field induced electron detrapping.The carrier detrapping mechanism could be helpful for lessening the trapping-related performance degradation of a GaN-based HEMT.     

A unified drain current 1/f noise model for GaN-based high electron mobility transistors

In this work, we present a theoretical and experimental study on the drain current 1/f noise in the AIGaN/GaN high electron mobility transistor （HEMT）. Based on both mobility fluctuation and carrier number fluctuation in a two- dimensional electron gas （2DEG） channel of AlGaN/GaN HEMT, a unified drain current 1/f noise model containing a piezoelectric polarization effect and hot carrier effect is built. The drain current 1/f noise induced by the piezoelectric polarization effect is distinguished from that induced by the hot carrier effect through experiments and simulations. The simulation results are in good agreement with the experimental results. Experiments show that after hot carrier injection, the drain current 1/f noise increases four orders of magnitude and the electrical parameter degradation Agm/gm reaches 54.9%. The drain current 1/f noise degradation induced by the piezoelectric effect reaches one order of magnitude; the electrical parameter degradation Agm/gm is 11.8%. This indicates that drain current 1/f noise of the GaN-based HEMT device is sensitive to the hot carrier effect and piezoelectric effect. This study provides a useful reliability characterization tool for the A1GaN/GaN HEMTs.     

Enhanced contact properties of spray-coated AgNWs source and drain electrodes in oxide thin-film transistors

Facile patterning of electrodes is required for various electronic applications, particularly in solution-processed oxide thin-film transistors (TFTs). In this study, source and drain electrodes were prepared from silver nanowires (AgNWs) using spray-coating and hot press techniques. Although spray coating allowed production of AgNW patterns, which could function as electrodes in oxide TFT, the as-sprayed films did not provide a sufficient physical contact with oxide semiconductors and formed interspaces that impeded electron injection. At the same time, hot press technique produced denser AgNW networks that had a tight contact with the oxide semiconductors. As a result, hot-pressed films were considered as satisfactory source and drain electrodes for high-performance oxide TFTs, as they provided an easy electron injection. Finally, the prepared oxide TFTs with hot-pressed AgNW electrodes exhibited average field-effect mobility of 4.75 ± 1.5 cm²/V, significantly higher than that of the TFTs with as-sprayed AgNW electrodes (0.08 ± 0.05 cm²/V).     

基于脉冲方法的超短栅长GaN基高电子迁移率晶体管陷阱效应机理

陷阱效应导致的电流崩塌是制约GaN基微波功率电子器件性能提高的一个重要因素,研究深能级陷阱行为对材料生长和器件开发具有非常重要的意义.随着器件频率的提升,器件尺寸不断缩小,对小尺寸器件中深能级陷阱的表征变得越发困难.本文制备了超短栅长（L_g=80 nm）的AlGaN/GaN金属氧化物半导体高电子迁移率晶体管（MOSHEMT）,并基于脉冲I-V测试和二维数值瞬态仿真对器件的动态特性进行了深入研究,分析了深能级陷阱对AlGaN/GaN MOSHEMT器件动态特性的影响以及相关陷阱效应的内在物理机制.结果表明,AlGaN/GaN MOSHEMT器件的电流崩塌随着栅极静态偏置电压的增加呈非单调变化趋势,这是由栅漏电注入和热电子注入两种陷阱机制共同作用的结果.根据研究结果推断,可通过改善栅介质的质量以减小栅漏电或提高外延材料质量以减少缺陷密度等措施达到抑制陷阱效应的目的,从而进一步抑制电流崩塌.     

应力导致的薄栅氧化层漏电流瞬态特性研究

分别研究了FN隧穿应力和热空穴(HH)应力导致的薄栅氧化层漏电流瞬态特性.在这两种应力条件下,应力导致的漏电流(SILC)与时间的关系均服从幂函数关系,但是二者的幂指数不同.热空穴应力导致的漏电流中,幂指数明显偏离-1,热空穴应力导致的漏电流具有更加显著的瞬态特性.研究结果表明:热空穴SILC机制是由于氧化层空穴的退陷阱效应和正电荷辅助遂穿中心的湮没.利用热电子注入技术,正电荷辅助隧穿电流可被大大地减弱.     

Ultrathin nickel oxide film as a hole buffer layer to enhance the optoelectronic performance of a polymer light-emitting diode

In order to promote a polymer LED (PLED), we fabricated and introduced an ultrathin nickel oxide (NiO) buffer layer (<10 nm) between the indium tin oxide (ITO) anode and the poly (3, 4-ethylenedioxythiophene) hole injection layer in the PLED. The NiO buffer layer was easily formed on the ITO anode by electron-beam deposition of a nickel (Ni) metal source and an oxygen plasma treatment process. As a result, the PLED device with the NiO buffer layer on its ITO anode had the same turn-on voltage as conventional PLED devices without the NiO buffer layer, and the luminance of the PLED device with the NiO buffer layer was doubled, compared with the conventional PLED devices without the NiO buffer layer. Improvement of the optoelectronic performance of the PLED can be attributed to the increase of the current driven into the diode, resulting from the NiO buffer layer, which can enhance the hole injection and balance the injection of the two types of carriers (holes and electrons). Thus it is an excellent choice to introduce the NiO buffer layer onto the ITO anode of the PLED devices in order to enhance the optoelectronic performance of PLED devices.     

Reduced effective temperature of hot electrons in nano-sized metal-oxide-semiconductor field-effect transistors

Hot electron effects have been extensively studied in metal-oxide-semiconductor field-effect transistors (MOSFETs). The importance of these effects when the dimensions are drastically reduced has so far not been thoroughly investigated. The scope of this paper is therefore to present a detailed study of the effective temperature of excess electrons in nanoscale MOSFETs by solving coupled Schrödinger and Poisson equations. It is found that the increased doping levels and reduced junction depths lead to substantially higher local Fermi levels in the source and drain regions. As a result, the temperature difference between electrons injected into the drain and local electrons is reduced. The scaling of the gate oxide thickness, as well as the drain voltage furthermore reduces the electron temperature in the drain. The detrimental effects of hot electron injection are therefore expected to be decreased by scaling the MOSFET. PACS 73.40.Qv; 73.63.Rt     

Electrical characterization of high-k gate dielectrics on semiconductors

This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks: (1) inelastic electron tunneling spectroscopy (IETS), (2) lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of a MOSFET, and (3) pulse agitated substrate hot electron injection (PASHEI) technique for measuring trapping effects in the gate dielectric at low and modest gate voltages.     

Non-equilibrium effects and self-heating in single-electron Coulomb blockade devices

We present a comprehensive investigation of non-equilibrium effects and self-heating in single electron transfer devices based primarily on the Coulomb blockade effect. During an electron trapping process, a hot electron maybe deposited in a quantum dot or metal island, with an extra energy usually of the order of the Coulomb charging energy, which is much higher than the temperature in typical experiments. The hot electron may relax through three channels: tunneling back and forth to the feeding lead (or island), emitting phonons, and exciting background electrons. Depending on the magnitudes of the rates in the latter two channels relative to the device operation frequency and to each other, the system may be in one of three different regimes: equilibrium, non-equilibrium, and self-heating (partial equilibrium). In the equilibrium regime, a hot electron fully gives up its energy to phonons within a pump cycle. In the non-equilibrium regime, the relaxation is via tunneling with a distribution of characteristic rates; the approach to equilibrium goes like a power law of time (frequency) instead of an exponential. This channel is plagued completely in the continuum limit of the single-electron levels. In the self-heating regime, the hot electron thermalizes quickly with background electrons, whose temperature T_e is elevated above the lattice temperature T_ol. We have calculated the coefficient in the well-known T⁵ law of energy dissipation rate, and compared the results to experimental values for aluminum and copper islands and for a two-dimensional semiconductor quantum dot. Moreover, we have obtained different scaling relations between the electron temperature, the operation frequency and device size for various types of devices.     

Correlation between defect-related electroluminescence and charge trapping in Gd-implanted SiO<Subscript>2</Subscript> layers

When amorphous silica is bombarded with energetic ions, various types of defects are created as a consequence of ion-solid interaction (oxygen deficient centers (ODC), non-bridging oxygen hole centers (NBOHC), E^′-centers, etc.). Luminescent peaks from oxygen deficiency centers at 2.7 eV, non-bridging oxygen hole centers at 1.9 eV and defect centers with emission at 2.07 eV were observed by changing the concentration of implanted Gd³⁺ ions. Charge trapping in Gd-implanted SiO₂ layers was induced using constant current electron injection to study the electroluminescence intensity with dependence on the applied voltage change. The process of electron trap generation during high field carrier injection results in an increase of the electroluminescence from non-bridging oxygen hole centers. Direct correlation between electron trapping and the quenching of the electroluminescence at 2.07 eV and 2.7 eV was observed with variation of the implanted Gd concentration. PACS 78.60.i; 72.20.Jv; 78.20.-e     

高$lt;i$gt;k$lt;/i$gt;栅介质小尺寸全耗尽绝缘体上锗p型金属氧化物半导体场效应晶体管漏源电流模型

通过求解沟道的二维泊松方程得到沟道表面势和沟道反型层电荷, 建立了高k栅介质小尺寸绝缘体上锗(GeOI) p型金属氧化物半导体场效应晶体管(PMOSFET)的漏源电流解析模型. 模型包括了速度饱和效应、迁移率调制效应和沟长调制效应, 同时考虑了栅氧化层和埋氧层与沟道界面处的界面陷阱电荷、氧化层固定电荷对漏源电流的影响. 在饱和区和非饱和区, 漏源电流模拟结果与实验数据符合得较好, 证实了模型的正确性和实用性. 利用建立的漏源电流模型模拟分析了器件主要结构和物理参数对跨导、漏导、截止频率和电压增益的影响, 对GeOI PMOSFET的设计具有一定的指导作用. 关键词： 绝缘体上锗p型金属氧化物半导体场效应晶体管 漏源电流模型 跨导 截止频率     

新型SOANN埋层SOI器件的自加热效应研究

本文提出了一个新型的SOI埋层结构SOANN (silicon on aluminum nitride with nothing),用AlN代替传统的SiO₂材料,并在SOI埋氧化层中引入空洞散热通道. 分析了新结构SOI器件的自加热效应.研究结果表明:用AlN做为SOI埋氧化层的材料, 降低了晶格温度,有效抑制了自加热效应.埋氧化层中的空洞,可以进一步提供散热通道, 使埋氧化层的介电常数下降,减小了电力线从漏端通过埋氧到源端的耦合, 有效抑制了漏致势垒降低DIBL(drain Induced barrier lowering)效应.因此,本文提出的新型SOANN结构可以提高SOI器件的整体性能,具有优良的可靠性.     

New SOI power device with multi-region high-concentration fixed interface charge and the model of breakdown voltage

A new SOI power device with multi-region high-concentration fixed charge(MHFC) is reported. The MHFC is formed through implanting Cs or I ion into the buried oxide layer(BOX), by which the high-concentration dynamic electrons and holes are induced at the top and bottom interfaces of BOX. The inversion holes can enhance the vertical electric field and raise the breakdown voltage since the drain bias is mainly generated from the BOX. A model of breakdown voltage is developed, from which the optimal spacing has also been obtained. The numerical results indicate that the breakdown voltage of device proposed is increased by 287% in comparison to that of conventional LDMOS.     

Light-emitting field-effect transistor based on a tetracene thin film

We report the first organic light-emitting field-effect transistor. The device structure comprises interdigitated gold source and drain electrodes on a Si/SiO(2) substrate. A polycrystalline tetracene thin film is vacuum sublimated on the substrate forming the active layer of the device. Both holes and electrons are injected from the gold contacts into this layer leading to electroluminescence from the tetracene. The output characteristics, transfer characteristics, and the optical emission properties of the device are reported. A possible mechanism for electron injection is suggested.