Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects

A power-aware transceiver for half-duplex bidirectional chip-to-chip optical interconnects has been designed and fabricated in a 0.13 μm complementary metal-oxide-semiconductor （CMOS） technology. The transceiver can detect the presence and absence of received signals and saves 55% power in Rx enabled mode and 45% in Tx enabled mode. The chip occupies an area of 1.034 mm2 and achieves a 3-dB bandwidth of 6 GHz and 7 GHz in Tx and Rx modes, respectively. The disabled outputs for the Tx and Rx modes are isolated with 180 dB and 139 dB, respectively, from the enabled outputs. Clear eye diagrams are obtained at 4.25 Gbps for both the Tx and Rx modes.     

2.5 Gbit/s multifunctional CMOS transceiver for chip-to-chip optical link

A novel multifunctional transceiver for chip-to-chip optical interconnects operating at 2.5 Gbit/s is proposed, which shares a common block between a receiver and a transmitter. This transceiver provides four conversion functions - electrical-to-optical, optical-to-optical, optical-to-electrical, and electrical-to-electrical - depending on the selection switch on a single chip. The whole chip integrated in 0.18 /spl mu/m CMOS occupies an area measuring 0.82/spl times/0.82 mm/sup 2/.     

A 2.5-mW SOS CMOS optical receiver for chip-to-chip interconnect

This paper reports on the design of a differential optical receiver in silicon-on-sapphire (SOS) complementary metal-oxide-semiconductor (CMOS). The low-power characteristics (2.5 mW) and small footprint make it a good candidate for two-dimensional optoelectronic interchip interconnects where the transparency of the substrate facilitates system integration and packaging. A differential transimpedance amplifier (TIA) with positive feedback at the front end extends the bandwidth of traditional differential TIAs when the capacitance of the photodetector is smaller than the capacitance of the gates in the differential pair. The full receiver tested in the 0.5-/spl mu/m ultrathin silicon (UTSi) SOS-CMOS Peregrine process consumes 2.5 mW when operated at or near gigabit rates, with bit-error rates of better than 10/sup -12/ taken at 750 Mb/s.     

A UWB CMOS transceiver

A direct-conversion ultra-wideband (UWB) transceiver for Mode 1 OFDM applications employs three resonant networks and three phase-locked loops. Using a common-gate input stage, the receiver allows direct sharing of the antenna with the transmitter. Designed in 0.13-/spl mu/m CMOS technology, the transceiver provides a total gain of 69-73 dB and a noise figure of 6.5-8.4 dB across three bands, and a TX 1-dB compression point of -10 dBm. The circuit consumes 105 mW from a 1.5-V supply.     

Monolithic vertical-cavity laser/p-i-n photodiode transceiver arrayfor optical interconnects

The design, fabrication, and characterization of a 16-element monolithic 850-nm vertical-cavity laser/p-type-intrinsic-n-type (VCL/p-i-n) photodiode transceiver array for optical interconnects are described. The packaged VCL/p-i-n array exhibits excellent array uniformity over a large temperature range. Packaged VCLs display up to 1 mW of single-mode power and a relative intensity noise below -120 dB/Hz for all currents above threshold at a measuring bandwidth of 2 GHz. The p-i-n photodiodes exhibit a responsivity of 0.535 A/W and a -3-dB bandwidth of 2.3 GHz. A microlens array integrated into the packaged VCL/p-i-n device decreases the VCL beam divergence six to seven times. Polarization control with a mean rejection ratio of 22 dB across the VCL array is achieved with the use of oval aperture VCLs     

A novel bidirectional optical coupling module for subscribers

To overcome drawbacks and limitations of planar lightwave circuit based modules for bidirectional communications, such as the demand for several chips and in consequence more packaging efforts, we have recently developed a novel optical coupling technique using our unique 155 Mbps bidirectional laser chip. Since the chip is structured with a pin-photodiode monolithically integrated on a laser diode's waveguide, the optical coupling requires only the alignment of the chip with a fiber. To optically couple the laser diode and photodiode simultaneously with a single fiber, we have designed an unusual coupling structure using a fiber having a cleaved surface whose normal is 35/spl deg/ angled to the fiber core axis, and using an index-controlling medium with a refractive index of /spl sim/1.3. The bidirectional chip is flip-chip bonded and the fiber is passively aligned using a V-groove on the same substrate of 2.5/spl times/1.3 mm/sup 2/ in size. Even with this extremely small and simple scheme for bidirectional optical coupling, we could obtain an optical output power of -7/spl sim/-10 dBm and a responsivity of <-30 dBm, which are satisfactory to the STM-1 level telecommunications specifications.     

A transceiver PIC for bidirectional optical communication fabricated by bandgap energy controlled selective MOVPE

A transceiver PIC consisting of a DFB-LD, a receiver PD and a Y-shaped branch waveguides is realized by in-plane bandgap energy controlled selective MOVPE. Both active and passive core layers are formed in one step selective growth, and complicated fabrication procedure is no longer required. More than 1 mW fiber coupled power and 7 GHz receiver bandwidth are obtained. The modulation and detection operations at 500 Mb/s are successfully demonstrated.     

Guided-wave optical chip-to-chip interconnections

An optical interconnection technique using a high-silica guided-wave optical circuit composed of channel waveguides and a mixer is proposed for LSI interchip communications. An experimental 4-chip interconnection circuit has 1 Gbit/s transmission capacity performance with an optical power margin of 3 dB.     

A 2.4-GHz CMOS transceiver for Bluetooth

A fully integrated CMOS transceiver tuned to 2.4 GHz consumes 46 mA in receive mode and 47 mA in transmit mode from a 2.7-V supply. It includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), power amplifier, and demodulator. The receiver uses a low-IF architecture for higher level of integration and lower power consumption. It achieves a sensitivity of -82 dBm at 0.1% BER, and a third-order input intercept point (IIP3) of -7 dBm. The direct-conversion transmitter delivers a GFSK modulated spectrum at a nominal output power of 4 dBm. The on-chip voltage controlled oscillator has a close-in phase-noise of -120 dBc/Hz at 3-MHz offset     

A method to tune the cavity-mode wavelength of resonant cavity-enhanced photodetectors for bidirectional optical interconnects

A method to tune the cavity-mode wavelength of resonant cavity-enhanced photodetectors (RCE-PDs) is proposed. The proposed method can enable monolithic integration of vertical-cavity surface-emitting lasers and RCE-PDs to be a cost-competitive choice for bidirectional optical interconnection by reducing the amount of component and packaging costs presently involved. The properly tuned cavity-mode wavelengths remain effectively aligned within a temperature range of -10/spl deg/C/spl sim/50/spl deg/C.     

A 5-GHz direct-conversion CMOS transceiver

A CMOS transceiver fully compliant with IEEE 802.11a in the unlicensed national information infrastructure (UNII) band (5.15-5.35 GHz) achieves a receiver sensitivity of -5 dBm for 64-QAM (quadrature amplitude modulation) with an error vector magnitude (EVM) of -29.3 dB. A single-sideband mixing technique for local-oscillator signal generation avoids frequency pulling. Realized in 0.18-/spl mu/m CMOS and operating from 1.8-V power supply, the design consumes 171 mW in receive mode and 135 mW in transmit mode while occupying less than 13 mm/sup 2/.     

A dual-antenna phase-array ultra-wideband CMOS transceiver

Ultra-wideband (UWB) systems use high-bandwidth signals to enable a new generation of ultra-high-data-rate wireless applications. Implementation of a high-bandwidth RF system in the 3-5 GHz band presents challenges that can be solved by circuit and system techniques. This article looks at the motivation and requirements for a WiMedia-compliant UWB system implemented for a target application in wireless video transmission. It explores the circuit-level trade-offs in CMOS radio and some of the system-level methods, such as selection diversity and equal-gain combining, used to increase robustness in multipath and interference environments. The radio (S. Lo, 2006) is part of a two-chip solution that includes a digital baseband chip that implements the WiMedia-compliant PHY and MAC. The measured results of the 0.18 /spl mu/m CMOS UWB transceiver demonstrate the efficacy of these techniques in the final RF and system performance.     

Differential bidirectional transceiver for on-chip long wires

This work presents a differential bidirectional transceiver (DBT) for on-chip long wires. To enhance operating speed and reduce power consumption, the voltage swing on the wire is reduced using current-mode scheme. Consequently, our design performs higher data rate when wire length is extended. Moreover, adoption of differential scheme with a moderate tradeoff of area effectively lowers power supply noise and common mode noise. The receiver adopts four input differential pairs along with current summation circuit to evaluate small signal differences of every that state resulted from transmitting different data. Simulations using 0.18-μm device model indicates that the total input to output delay over a 5 mm long wire is 0.96 ns, with a power consumption of 8.724 mW at a speed of 1.2 Gbps and a maximum achievable data rate of 1.5 Gbps. A test chip is realized and successfully verifies the performance of the transceiver.     

A 2-V CMOS cellular transceiver front-end

This work presents the design and implementation of a 2-V cellular transceiver front-end in a standard 0.25-μm CMOS technology. The prototype integrates a low-IF receiver (low noise amplifier, I/Q mixers, and VGAs) and a direct-upconversion transmitter (I/Q mixers and pre-amplifier) on a single die together with a complete phase-locked loop, including a 64/79 prescaler, a fully integrated loop filter, and a quadrature voltage controlled oscillator with on-chip inductors. Design trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low voltage. As a result, the IC operates from a power supply of only 2 V, while consuming 191 mW in receiver (RX) mode and 160 mW in transmitter (TX) mode. To build a complete transceiver system for 1,8-GHz cellular communication, only an antenna, an antenna filter, a power amplifier, and a digital baseband chip must be added to the analog front-end. This work shows the potential of achieving the analog performance required for the class I/II DCS-1800 cellular system in a standard 0.25-μm CMOS technology, without tuning or trimming     

Multichip optical transmitter module for chip-to-chip interconnection on optical PCBs

A multichip module of an optical transmitter, which consists of flip-chip bonded 1/spl times/4 VCSELs on a CMOS driver array IC, is fabricated and demonstrated. The -3 dB bandwidth and adjacent crosstalk of the hybrid integration multichip module are about 4.5 GHz and less than -30 dB, respectively. The whole integrated multichip volume is 1.1/spl times/1.2/spl times/0.52 mm/sup 3/ for four channels.     

A low-power monolithic CMOS transceiver for 802.11b wireless LANs

A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18 μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta (∑△) fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of-3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7×4.2 mm2.     

256-channel bidirectional optical interconnect using VCSELs andphotodiodes on CMOS

Two-dimensional parallel optical interconnects (2-D-POIs) are capable of providing large connectivity between elements in computing and switching systems. Using this technology we have demonstrated a bidirectional optical interconnect between two printed circuit boards containing optoelectronic (OE) very large scale integration (VLSI) circuits. The OE-VLSI circuits were constructed using vertical cavity surface emitting lasers (VCSELs) and photodiodes (PDs) flip-chip bump-bonded to a 0.35-μm complementary metal-oxide-semiconductor (CMOS) chip. The CMOS was comprised of 256 laser driver circuits, 256 receiver circuits, and the corresponding buffering and control circuits required to operate the large transceiver array. This is the first system, to our knowledge, to send bidirectional data optically between OE-VLSI chips that have both VCSELs and photodiodes cointegrated on the same substrate     

13.56 MHz CMOS transceiver for RFID applications

An Amplitude Shift Keying (ASK) transceiver for RFID applications is presented in this paper. The proposed transceiver is suitable for communications with electronic devices that are powered through an inductive link. The circuit has been designed to be compatible with the communication standards ISO 14443. It operates at 13.56 MHz with a communication speed from 200 kHz up to 847 kHz. In modulation mode of operation, a solution based on programmable CMOS inverters is proposed to control the modulation depth in the range [0–100%]. The demodulator has been designed using versatile current rectifier and a simple operational transconductance amplifier stage. The proposed transceiver was implemented in a standard 0.5 μm CMOS process. The circuit covers an area of 2 mm² and the total DC power consumption is lower than 5.3 mW under 4V DC supply voltage. Stéphane Meillére has received the Engineer degree in Microelectronics from the ISEN-Toulon, Institut Supérieur d’Electronique et du Numérique, School at Toulon in 2000 and the M.Sc. and Ph.D. degrees from the University of Provence Aix-Marseille I, France, in 2000 and 2004, respectively, all in Microelectonics. From 2003 to 2005, he worked as a Research Engineer at the ISEN-Toulon. Since 2005 he joined the University of Provence as an Assistant Professor. His research interests are mainly in the design of full custom ASICs. He integrated in the same time the Integrated Circuits Design Team at the L2MP laboratory. He worked on different research project with industry. Hervé Barthélemy has received the MSc degree in Electrical Engineering in 1992 and the PhD degree in Electronics from the University of Paris XI Orsay, France in 1996. In 2002 he received the HDR degree from the University of Provence, Aix-Marseille I, France. From 1996 to 2000 he was an Assistant Professor at the Institut Supérieur d’Electronique de la Méditerranée (ISEN) in Toulon, France. Since 2000 he joined the University of Provence where is has been a full Professor in 2005. Since 2005 he has headed the Integrated Circuits Design Team at the L2MP laboratory. The team counts 12 Researchers and 20 PhD students and is involved in several research projects with industry. His research interests are mainly in the design of radiofrequency analog integrated circuits. He authored and co-authored multiple publications in international journals and conference proceeding. Michel Martin received an engineering degree in applied physics, option Micro-electronics from Ecole Nationale Supérieure de Physics in Marseille in 1991. He worked previously in ST Microelectronics, and he was involved in the design of the Smart Card Group’s product. He joined Gemplus in ’91 where he designed chips for secured smart cards memories. In 1995, he was the Co-founder of INSIDE Contactless. He was involved in the analog and EEPROM memories designs for contact and contactless chips. Michel was promoted I.C. Design Director with a team of 15 people divided on 2 Design Centers. He still maintains an active part in the chip Design. He is also the responsible for technical interface with the foundries to develop EEPROM memory bit cell, and improve the new processes dedicated the smart cards application.     

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.     

A CMOS 10-gb/s SONET transceiver

This paper presents a single-chip SONET OC-192 transceiver (transmitter and receiver) fabricated in a 90-nm mixed-signal CMOS process. The transmitter consists of a 10-GHz clock multiplier unit (CMU), 16:1 multiplexer, and 10-Gb/s output buffer. The receiver consists of a 10-Gb/s limiting input amplifier, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. Both transmit and receive phase-locked loops employ a 10-GHz on-chip LC voltage-controlled oscillator (VCO). This transceiver exceeds all SONET OC-192 specifications with ample margin. Jitter generation at 10.66-Gb/s data rate is 18 mUI/sub pp/ (unit interval, peak-to-peak) and jitter tolerance is 0.6 UI/sub pp/ at 4-MHz jitter frequency. This transceiver requires 1.2V for the core logic and 1.8 V for input/output LVDS buffers. Multiple power supply domains are implemented here to mitigate crosstalk between receiver and transmitter. The overall power dissipation of this chip is 1.65 W.