一种新的减少媒体处理器中寄存器文件复杂度的方法

寄存器文件被广泛地应用于最新的DSP和媒体处理器的设计,为了能够减小处理器所开销的芯片面积、功耗以及体系结构的复杂度,必须合理设计寄存器文件结构.本文通过对现行采用的几种寄存器文件结构的分析对比,提出了一种新的独立寄存器文件单元结构,即将寄存器文件作为一个流水级单元,并且通过编译器静态调度的方法实现了寄存器文件端口数的减少以及旁路电路的简化.从实验的结果可以看出,这种结构不仅能满足媒体处理器的目标要求,而且对VLIW结构的媒体处理器有重要的意义.     

数字信号处理器中10端口高速寄存器文件设计

本文采用1P2M0.35滋m的N阱CMOS工艺,设计了一种用于数字信号处理器的10端口高速32×64位寄存器文件。寄存器文件中设计了写优先级比较机制和读写直通机制,避免不同数据源在同一周期内对同一寄存器的写冲突,保持读写数据的一致性。同时还设计了一种高速低功耗的电流灵敏运放读操作电路。仿真结果表明室温下,电源电压为3.3V时,寄存器文件的工作频率可以达到300MHz。     

媒体处理器的视频滤波考虑

以往,在医用、工业和军事系统中进行实时视频或图像分析时,设计师通常需要采用昂贵的专用处理器。但随着定点、高性能嵌入式媒体处理器的出现,使低成本的实时图像处理成为可能。为了开发高效的算法,产品设计工程师需要充分利用这些处理器所提供的体系结构特点。本文讨论了数字图像滤波算法能够如何利用嵌入式媒体处理器体系结构的多媒体特性。该Blackfin处理器的特点和指令集可用作一个参照,但是同样的概念通常也适用于其他高性能媒体处理器。     

一种基于SystemC的软硬件协同设计方法

随着集成电路工艺的飞速发展,传统的设计方法已不能满足设计高集成度的复杂数字系统的要求。软硬件协同设计成为嵌入式系统设计的新方法。SystemC是一种兼容C++的系统建模语言,它同时支持RTL级、行为级和系统级描述,使其成为软硬件协同设计平台的基础。     

基于SOPC的软硬件协同设计

对SOPC的发展现状和相关技术进行了研究,简要论述了SOPC的优点,介绍了软硬件协同设计可以根据系统各功能模块的特点和设计约束来选择合适的软件或硬件实现方式的设计原理。以Altera公司的SOPC实现平台为背景,结合实际工程应用,介绍了基于SOPC的软硬件协同设计的设计流程,从而探讨出一种便捷实用的软硬件协同设计方法。     

面向寄存器的流水线处理器建模及验证方法

提出了一种新的流水线处理器功能的验证方法 ,这种方法的主要思想是通过验证流水线处理器中所有寄存器的功能来验证处理器的功能 .流水线处理器绝大部分是由同步电路组成的 ,同步电路的状态则完全由寄存器的状态决定 ,因此如果能够保证每个寄存器功能正确就可以保证整个同步电路功能正确 .对于流水线处理器来说 ,寄存器状态的变迁是由处理器的原始输入和寄存器本身状态决定的 .原始输入包括控制信号 (如复位信号 )和数据输入 (如指令输入 ) .如果把对每个寄存器的赋值操作转换成对控制信号和数据输入的操作 ,就可以生成一个验证序列 ,这个序列包括每个     

面向寄存器的流水线处理器建模及验证方法

提出了一种新的流水线处理器功能的验证方法,这种方法的主要思想是通过验证流水线处理器中所有寄存器的功能来验证处理器的功能.流水线处理器绝大部分是由同步电路组成的,同步电路的状态则完全由寄存器的状态决定,因此如果能够保证每个寄存器功能正确就可以保证整个同步电路功能正确.对于流水线处理器来说,寄存器状态的变迁是由处理器的原始输入和寄存器本身状态决定的.原始输入包括控制信号(如复位信号)和数据输入(如指令输入).如果把对每个寄存器的赋值操作转换成对控制信号和数据输入的操作,就可以生成一个验证序列,这个序列包括每个时钟周期控制信号和数据输入的值.有了这个序列就可以把目标设计和参考模型进行结果比较,从而验证目标设计功能是否正确.同时这种方法也便于调试.     

软硬件协同的SOC设计方法

软硬件协同设计是一种正在发展中的设计方法。本文首先分析了它在SOC设计中的必要性，其次给出了软硬件协同设计的基本流程，并探讨了其优点和现存的技术难点。最后给出了设计及验证实例。     

基于资源受限的软硬件划分方法

本文提出了一种在硬件资源受限的情况下进行软硬件划分的一种方法。以贪婪算法(greedy)作为划分的核心，并对所抽取的划分图进行结点的预先分类，减小贪婪算法探索的设计空间，加速算法的执行。通过反复地迭代，获得了最终的软硬件划分选择。实验证明，这种软硬件划分的方法具有高效率及高面积利用率的特点。     

一种基于JTAG的软硬件协同SOC调试接口

提出了一种处理器片上调试系统。使用科学的设计方法学完成了硬件与软件部分的设计,采用优化策略改进了硬件部分,得到了测试覆盖率高、稳定性较高、实时性较好的可调试SOC。软件部分通过层次化设计,连接硬件和UI,具有一定的价值。     

基于Altera FPGA的软硬件协同仿真

简要介绍了软硬件协同仿真技术，指出了在大规模FPGA开发中软硬件协同仿真的重要性和必要性，给出基于A1tera FPGA的门级软硬件协同仿真实例。     

65nm下低功耗稳定性高的寄存器堆的设计

本文详细分析了低功耗稳定性高的32x32, 4读2写的寄存器堆,提出了采用MUX和锁存器的输出结构。该输出结构没有任何动态或模拟电路,提高了鲁棒性的同时降低了功耗。简化的时序不仅降低了功耗,而且增强了鲁棒性。连续读“0”或“1”的时候,这种结构能够消耗更小的功耗。该寄存器堆已在65nm下流片,芯片测试结果显示,它1.2V电源电压下,工作频率为0.8GHZ,消耗功耗7.2mW。     

软件导引的模拟退火算法在硬软件划分中的应用

对系统级设计中的硬软件分割问题建立数学模型．将系统级设计工具提供的性能分析功能与模拟退火算法相结合，设计了一种软件导引的模拟退火算法。该实现中将嵌入式系统性能指标（任务的执行时间）作为约束，将实现代价以及功耗作为硬软件分割方法优化的目标。在保证系统的设计目标（任务执行时间）满足要求的基础上。通过选择系统中各模块实现代价和功耗较小的实现方法．进而优化整个系统的实现代价和功耗．彻底改变了以往航天应用的嵌入式系统设计中依赖人工经验进行硬软件划分下现状。     

An isolated SNM model for high-stability multi-port register file in 65 nm CMOS

In modern microprocessors, the multi-port register file is one of the key modules which provides fast and multiple data access for instructions. As the number of access ports in register files increases, stability becomes a key issue due to the voltage fluctuation on bit lines. We propose to apply an isolated inverter to address the voltage fluctuation. To assess the register stability, we derive a closed-form expression of static noise margin (SNM) for our register file. The proposed SNM model can be used as a guideline to predict the impact of several register parameters on the stability and optimize register file designs. To validate the proposed SNM model, we fabricated a test chip of two-write-four-read (2W4R) 1024 bits register file in a TSMC 65 nm low-power CMOS technology. The experimental result shows that the stability of our register file cells with an isolated inverter improve the conventional cells by approximately 2.4 times. Also, the supply voltage causes a fluctuation of SNM of about 65%, while temperature and transistor mismatch cause a fluctuation of SNM of about 20%.     

Functional Validation of Mixed Hardware/Software Systems based on Specification, Partitioning, and Simulation of Test Cases

Tecs is a test case development methodology for the functional validation of large electronic systems, typically consisting of several custom hardware and software components. The methodology determines a hierarchical top-down test case development process including test case specification, validation, partitioning and implementation. The test case development process addresses the functional validation of the system and its components such as ASICs, boards, HW and software modules; it does not facilitate timing or performance verification. The system functions are used to define test cases at the system level and to derive sub-functions for the system components. Test cases are specified, using a special purpose formalism, and validated before they are applied to the system under test. Furthermore, we propose a technique to partition test cases corresponding to the partitioning of the system into sub-systems and components. This technique can significantly reduce system simulation time because it allows the full validation of system functions by simulation at the sub-system and component level. The system model need only be simulated with a reduced set of stimuli to validate the interfaces between sub-systems. We present a test case specification language and tools that support the proposed methodology. The validation of a switching function illustrates methodology, language, and tools.     

Algorithmic aspects for functional partitioning and scheduling in hardware/software co-design

Hardware/software (HW/SW) partitioning and scheduling are the crucial steps during HW/SW co-design. It has been shown that they are classical combinatorial optimization problems. Due to the possible sequential or concurrent execution of the tasks, HW/SW partitioning and scheduling has become more difficult to solve optimally. In this paper more efficient heuristic algorithms are proposed for the HW/SW partitioning and scheduling. The proposed algorithm partitions a task graph by iteratively moving the task with highest benefit-to-area ratio in higher priority. The benefit-to-area ratio is updated in each iteration step to cater for the task concurrence. The proposed algorithm for task scheduling executes the task lying in hardware-only critical path in higher priority to enhance the task forecast. A large body of experimental results conclusively shows that the proposed heuristic algorithm for partitioning is superior to the latest efficient combinatorial algorithm (Tabu search) cited in this paper. Moreover, the Tabu search for partitioning has been further improved by utilizing the proposed heuristic solution as its initial solution. In addition, the proposed scheduling algorithm obtains the improvements over the most widely used approaches by up to 10% without large increase in running time. This work was presented in part at 2006 IEEE International Conference on Field Programmable Technology (ICFPT).     

Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures

New applications demand very high processing power when run on embedded systems. Very Long Instruction Word (VLIW) architectures have emerged as a promising alternative to provide such processing capabilities under the given energy budget. However, in this new VLIW-based architectures, the register file is a very critical contributor to the overall power consumption and new approaches have to be proposed to reduce its power while preserving system performance. In this paper, we propose a novel joint hardware-software approach that reduces the leakage energy in the register files of these embedded VLIW architectures. This approach relies upon an energy-aware register assignment method and a hardware support that creates sub-banks in the global register file that can be switched on/off at run time. Our results indicate energy savings in the register file, after considering the overhead of the added extra hardware, up to 50% for modern multimedia embedded applications without performance degradation. We illustrate this approach using real-life applications running on these processors. We also illustrate the tradeoff between the area overhead vs. the gains in the leakage energy for the different strategies.     

软硬件协同设计语言System C在SoC设计中的应用

软硬件协同设计是未来VLSI设计的发展趋势.作为新的系统级VLSI设计标准,System C是一种通过类对象扩展的基于C/C++建模平台,支持系统级软硬件协同设计、仿真和验证.文章讨论了SystemC复杂芯片设计中的设计流程、设计优势,并给出具体设计实例.     

一种基于可配置共享寄存器堆的多核处理器核间数据交换结构设计

针对多核体系架构提出了一种利用可配置共享寄存器堆实现多核处理器核间数据交换的结构,详细介绍了该结构的各组成部分及其实现机制,并对该结构的性能做出了相应的评估.