AlGaN/GaN HEMT based hydrogen sensor with platinum nanonetwork gate electrode

AlGaN/GaN high electron mobility transistor (HEMT) based hydrogen sensors incorporating platinum nanonetworks in the gate region were demonstrated. Pt nanonetworks with 2–3 nm diameter were synthesized by a simple and low-cost solution phase method, and applied to the gate electrode of transistor sensor. The HEMT with physically and electrically connected Pt nanonetwork gate showed good pinch-off and modulation of drain current characteristics. Compared to conventional Pt thin film AlGaN/GaN HEMT sensor, the Pt nanonetwork sensor has dramatically improved current response to hydrogen. Relative current change of Pt nanonetwork gated sensor in 500 ppm H₂ balanced with Air ambient was 3.3 × 10⁶% at V_GS of ?3.3 V, while 2.5 × 10²% at V_GS of ?2.9 V for Pt film. This results from large increase in channel conductance induced by huge catalytic surface area of nanostructured Pt networks.     

Non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor with high breakdown voltage

A non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor(quasi-EDHEMT) with a thin barrier, high breakdown voltage and good performance of drain induced barrier lowering(DIBL)was presented. Due to the metal organic chemical vapor deposition(MOCVD) grown 9-nm undoped AlGaN barrier, the effect that the gate metal depleted the two-dimensiomal electron gas(2DEG) was greatly impressed. Therefore, the density of carriers in the channel was nearly zero. Hence, the threshold voltage was above 0 V. Quasi-E-DHEMT with 4.1-μm source-to-drain distance, 2.6-μm gate-to-drain distance, and 0.5-μm gate length showed a drain current of 260 mA/mm.The threshold voltage of this device was 0.165 V when the drain voltage was 10 V and the DIBL was 5.26 mV/V. The quasi-E-DHEMT drain leakage current at a drain voltage of 146 V and a gate voltage of-6 V was below 1 mA/mm. This indicated that the hard breakdown voltage was more than 146 V.     

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×10¹³ el/cm², a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×10¹⁴ el/cm² was observed.     

An AlGaN/GaN HEMT with reduced surface electric field and improved breakdown voltage

A reduced surface electric field in AlGaN/GaN high electron mobility transistor (HEMT) is investigated by employing a localized Mg-doped layer under the two-dimensional electron gas (2-DEG) channel as an electric field shaping layer. The electric field strength around the gate edge is effectively relieved and the surface electric field is distributed evenly as compared with those of HEMTs with conventional source-connected field plate and double field plate structures with the same device physical dimensions. Compared with the HEMTs with conventional source-connected field plate and double field plate, the HEMT with Mg-doped layer also shows that the breakdown location shifts from the surface of the gate edge to the bulk Mg-doped layer edge. By optimizing both the length of Mg-doped layer, L_m, and the doping concentration, a 5.5 times and 3 times the reduction in the peak electric field near the drain side gate edge is observed as compared with those of the HEMTs with source-connected field plate structure and double field plate structure, respectively. In a device with V_GS=-5 V, L_m=1.5 μm, a peak Mg doping concentration of 8× 10¹⁷ cm^-3 and a drift region length of 10 μm, the breakdown voltage is observed to increase from 560 V in a conventional device without field plate structure to over 900 V without any area overhead penalty.     

Junctionless nanowire transistor fabricated with high mobility Ge channel

The junctionless nanowire metal–oxide–semiconductor field‐effect transistor (JNT) has recently been proposed as an alternative device for sub‐20‐nm nodes. The JNT architecture eliminates the need for forming PN junctions, resulting in simple processing and competitive electrical characteristics. In order to further boost the drive current, alternative channel materials such as III–V and Ge, have been proposed. In this Letter, JNTs with Ge channels have been fabricated by a CMOS‐compatible top–down process. The transistors exhibit the lowest subthreshold slope to date for JNT with Ge channels. The devices with a gate length of 3 μm exhibit a subthreshold slope (SS) of 216 mV/dec with an I_ON/I_OFF current ratio of 1.2 × 10³ at V_D = –1 V and drain‐induced‐barrier lowering (DIBL) of 87 mV. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

A study on the performance of metal-oxide-semiconductor-field-effect-transistors with asymmetric junction doping structure

Diode currents of MOSFET were studied and characterized in detail for the ion implanted pn junction of short channel MOSFETs with shallow drain junction doping structure. The diode current in MOSFET junctions was analyzed on the point of view of the gate-induced-drain leakage (GIDL) current. We could found the GIDL current is generated by the band-to-band tunneling (BTBT) of electrons through the reverse biased channel-to-drain junction and had good agreement with BTBT equation. The effect of the lateral electric field on the GIDL current according to the body bias voltage is characterized and discussed. We measured the electrical doping profiling of MOSFETs with a short gate length, ultra thin oxide thickness and asymmetric doped drain structure and checked the profile had good agreement with simulation result. An accurate effective mobility of an asymmetric source–drain junction transistor was successfully extracted by using the split C–V technique.     

Electrical properties and memory effect in the field effect transistor based on organic ferroelectric insulator and pentacene

We have fabricated a field effect transistor (FET) based on an organic ferroelectric insulator and molecular conductor, and investigated the electrical properties and memory effects on the PEN-FET. We have observed a drastic change in the drain current at around the coercive electric fieldE _c of the organic ferroelectric insulator in not only a FET (PEN-FET) based on a pentacene (PEN) film but also a FET (IPEN-FET) based on an iodine doped PEN film. The magnitude of the change of the drain current for the IPEN-FET is 200 times larger than that for the PEN-FET. It is expected from these results that the PEN-FET (especially the IPEN-FET) is an improvement in such devices, since it operates at a low gate electric field accompanied by the appearance of the spontaneous polarization in the organic ferroelectric insulator. In addition, we have found that the drain current for the PEN-FET does not return to the initial drain current ofE _G =0 V/cm for more than one week, even if the gate electric field is changed to 0 V/cm from 500 V/cm(>E _c ). From these results, it is suggested that the PEN-FET becomes a memory device.     

基于NPB的垂直构型有机发光晶体管的光电特性研究

通过将有机空穴阻挡材料BCP薄层插入垂直构型有机发光晶体管器件ITO/NPB（40nm）/Al（30nm）/NPB（20nm）/Alq₃（55nm）/Al中的不同位置对器件光电特性的影响来研究器件漏电流较大的原因以及器件中具体的载流子过程.充分证明了栅极注入的空穴对沟道中的电流有贡献.进而通过用LiF薄层修饰漏极来增强电子的注入并减小漏电流,得到了相对稳定的发光晶体管器件,其发光强度有很大提高并可很好地由栅极电压来进行调控.更换发光材料层容易得到不同颜色的发光晶体管. 关键词： 垂直构型有机发光晶体管（VOLET） 静电感应晶体管（SIT） N')" href="#">NPB （N N′-diphenyl-N')" href="#">N′-diphenyl-N N′-bis（1-naphtyl）-1')" href="#">N′-bis（1-naphtyl）-1 1′-biphenyl-4     

InN纳米线的低压化学气相沉积及其场发射特性研究

利用低压化学气相沉积方法在以Au作催化剂的Si衬底上生长了InN纳米线. 扫描电子显微镜分析表明，这些纳米线的直径在60—100 nm的范围内, 而其长度大于1 μm.高分辨透射电子显微镜图像表明，合成的纳米线中含有六方相和立方相的InN晶体.这些InN纳米线具有良好的场发射特性和稳定的场发射电流，其开启场为10.02 V/μm(电流密度为10 μA/cm²)，在24 V/μm 的电场下，其电流密度达到5.5 mA/cm².此外，对InN纳米线的场发射机理也进行了讨论. 关键词： InN纳米线 场电子发射 非线性Fower-Nordheim曲线     

A 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain

As the scaling of CMOS transistors extends to the sub-20 nm regime, the most challenging aspect of device design is the control of the off-state current. The traditional methods for controlling leakage current via the substrate doping profile will be difficult to implement at these dimensions. A promising method for controlling leakage in sub-20 nm transistors is the reduction in source-to-drain leakage paths through the use of a body region which is significantly thinner then the gate length, with either a single or a double gate. In this paper we present ultra-thin body PMOS transistors with gate lengths down to 20 nm fabricated using a low-barrier silicide as the source and drain. Calixarene-based electron-beam lithography was used to define critical device dimensions. These transistors show 260 μ A μ m ^{− 1}on-current and on/off current ratios of 10⁶, for a conservative oxide thickness of 40 Å and | V_g − V_t| = 1.2 V. Excellent short-channel effect, with only 0.2 V reduction in | V_t| is obtained in devices with gate lengths ranging from 100 to 20 nm.     

具有高阈值电压和大栅压摆幅的常关型槽栅AlGaN/GaN金属氧化物半导体高电子迁移率晶体管

介绍了一种具有高阈值电压和大栅压摆幅的常关型槽栅AlGaN/GaN金属氧化物半导体高电子迁移率晶体管。采用原子层淀积(ALD)方法实现Al₂O₃栅介质的沉积。槽栅常关型AlGaN/GaN MOS-HEMT的栅长(L_g)为2 μm,栅宽(W_g)为0.9 mm(0.45 mm×2),栅极和源极(L_gs)之间的距离为5 μm,栅极和漏极(L_gd)之间的距离为10 μm。在栅压为－20 V时,槽栅常关型AlGaN/GaN MOS-HEMT的栅漏电仅为0.65 nA。在栅压为+12 V时,槽栅常关型AlGaN/GaN MOS-HEMT的栅漏电为225 nA。器件的栅压摆幅为－20~+12 V。在栅压V_gs=+10 V时,槽栅常关型AlGaN/GaN MOS-HEMT电流和饱和电流密度分别达到了98 mA和108 mA/mm (W_g=0.9 mm), 特征导通电阻为4 mΩ·cm²。槽栅常关型AlGaN/GaN MOS-HEMT的阈值电压为+4.6 V,开启与关断电流比达到了5×10⁸。当V_ds=7 V时,器件的峰值跨导为42 mS/mm (W_g=0.9 mm,V_gs=+10 V)。在V_gs=0 V时,栅漏间距为10 μm的槽栅常关型AlGaN/GaN MOS-HEMT的关断击穿电压为450 V,关断泄露电流为0.025 mA/mm。     

基于有限元方法的有机场效应晶体管特性模拟与实验验证

采用有限元方法,借助多物理场软件COMSOL模拟了底栅顶接触结构有机场效应晶体管电位和载流子浓度随源漏电压Vds的变化。模拟结果表明,当固定栅压V_g=-10 V时,改变V_(ds)从0~-10 V,对于电位分布,从栅极到源漏电极竖直方向有渐进的变化,而从源极到漏极的水平方向呈现由大到小明显的梯度变化。对于载流子浓度,观察到沟道处从源极向漏极逐渐减少,在靠近漏极的区域减少得尤为明显,而当源漏电压等于栅极电压时,产生夹断现象。进一步将模拟结果与实际制备的器件性能进行了对比,模拟结果与实验数据所显示的分布趋势大体相同,印证了模拟的合理性。由此表明,采用模拟方法分析有机场效应晶体管的器件特性,对于实际制备器件具有重要的指导意义。     

纳米体硅鳍形场效应晶体管单粒子瞬态中的源漏导通现象

体硅鳍形场效应晶体管(FinFET)是晶体管尺寸缩小到30 nm以下应用最多的结构,其单粒子瞬态产生机理值得关注.利用脉冲激光单粒子效应模拟平台开展了栅长为30, 40, 60, 100 nm Fin FET器件的单粒子瞬态实验,研究FinFET器件单粒子瞬态电流脉冲波形随栅长变化情况;利用计算机辅助设计(technology computer-aided design, TCAD)软件仿真比较电流脉冲产生过程中器件内部电子浓度和电势变化,研究漏电流脉冲波形产生的物理机理.研究表明,不同栅长Fin FET器件瞬态电流脉冲尾部都存在明显的平台区,且平台区电流值随着栅长变短而增大;入射激光在器件沟道区下方体区产生高浓度电子将源漏导通产生导通电流,而源漏导通升高了体区电势,抑制体区高浓度电子扩散,使得导通状态维持时间长,形成平台区电流;尾部平台区由于持续时间长,收集电荷量大,会严重影响器件工作状态和性能.研究结论为纳米Fin FET器件抗辐射加固提供理论支撑.     

Glasses of heavy metal and gallium oxides doped with neodymium

Abstract

Optical and physical properties of a new family of Nd: BPG (Bi₂O₃-PbO-Ga₂O₃) glasses are presented at 1 mol% Nd doping level. Knoop hardness of 321 kg/mm² and density of 4.63 g/cm³ were measured. These high refractive index glasses present a very large absorption cross section of 2.5 × 10^?20 cm² at 800 nm. Emission occurs at three bands centered at 877 nm, 1066 nm and 1341 nm with a fluorescence lifetime associated to these transitions of 110 μs. At 1066 nm, the spectral linewidth is 30 nm. These properties make these glasses good candidates for laser action.     

Chalcogen-based thin film transistor using CuInSe2 photo-active layer

We propose chalcogen-based photo-thin film transistor (P-TFT) using CuInSe₂ (CIS) homo-junction. By using a tri-layer process, we fabricated n- and p-type CIS films. Optical and electrical properties of the fabricated CIS films are measured to be suitable for homo-junction. For the fabrication of a P-TFT, n-type CIS generating higher photo current was used for a channel layer whereas p-type CIS with higher carrier density was used for source and drain. The fabricated transistor exhibited typical transistor operation of p-channel enhancement mode and current increase with light.     

Room-temperature flexible thin film transistor with high mobility

We report a room-temperature and high-mobility InGaZnO thin-film transistor on flexible substrate. To gain both high gate capacitance and low leakage current, we adopt stacked dielectric of Y₂O₃/TiO₂/Y₂O₃. This flexible IGZO TFT shows a low threshold voltage of 0.45 V, a small sub-threshold swing of 0.16 V/decade and very high field-effect mobility of 40 cm²/V. Such good performance is mainly contributed by improved gate stack structure and thickness modulation of IGZO channel that reduce the interface trap density without apparent mobility degradation.     

InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operating and standby power application below supply voltage of 0.5 V

An In_0.53Ga_0.47As/InP heterojunction-channel tunneling field-effect transistor (TFET) with enhanced subthreshold swing (S) and on/off current ratio (I_on/I_off) is studied. The proposed TFET achieves remarkable characteristics including S of 16.5 mV/dec, on-state current (I_on) of 421 μA/μm, I_on/I_off of 1.2 × 10¹² by design optimization in doping type of In_0.53Ga_0.47As channel at low gate (V_GS) and drain voltages (V_DS) of 0.5 V. Comparable performances are maintained at V_DS below 0.5 V. Moreover, an extremely fast switching below 100 fs is accomplished by the device. It is confirmed that the proposed TFET has strong potentials for the ultra-low operating power and high-speed electron device.     

Nanoscale SiGe-on-insulator (SGOI) MOSFET with graded doping channel for improving leakage current and hot-carrier degradation

A novel graded doping profile, for the first time is introduced for reliability improvement and leakage current reduction. The proposed structure is called graded doping channel SiGe-on-insulator (GDC-SGOI). The key idea in this work is to modify the electric field and band energy with novel doping distribution in the channel for improving leakage current and hot electron. Using two-dimensional two-carrier simulation we demonstrate that the GDC-SGOI shows lower electron temperature near the drain region in the channel in comparison with the conventional SGOI (C-SGOI) with uniform doping. On the other hand, short channel effects (SCEs) such as drain induced barrier lowering (DIBL) and threshold voltage roll-off improvement leads to leakage current reduction. DIBL decrement and less dependence of the threshold voltage and DIBL on channel length variation in the GDC-SGOI structure show SCEs suppression. Furthermore the on-off current ratio (I_on/I_off) in the GDC-SGOI is higher than that achieved from the C-SGOI. Therefore, the results show that the GDC-SGOI structure especially in low power and device reliability has excellent performance in comparison with the C-SGOI.     

Exploring the warped bulk

In this study, a gallium nitride (GaN) high electron mobility transistor (HEMT) with recessed insulator and barrier is reported. In the proposed structure, insulator is recessed into the barrier at the drain side and barrier is recessed into the buffer layer at the source side. We study important device characteristics such as electric field, breakdown voltage, drain current, maximum output power density, gate-drain capacitance, short channel effects and DC transconductance using two-dimensional and two-carrier device simulator. Recessed insulator in the drain side of the proposed structure reduces maximum electric field in the channel and therefore increases the breakdown voltage and maximum output power density compared to the conventional counterpart. Also, gate-drain capacitance value in the proposed structure is less than that of the conventional structure. Overall, the proposed structure reduces short channel effects. Because of the recessed regions at both the source and the drain sides, the average barrier thickness of the proposed structure is not changed. Thus, the drain current of the proposed structure is almost equivalent to that of the conventional transistor. In this work, length (L _r) and thickness (T _r) of the recessed region of the barrier at the source side are the same as those of the insulator at the drain side.     

A p-channel SMC poly-Si thin film-transistor with a GOLDD structure

We have developed a silicide-mediated crystallization (SMC) polycrystalline silicon (poly-Si) thin film transistor (TFT) with a gate overlapped lightly doped drain (GOLDD) structure. Applying a GOLDD structure to the SMC poly-Si TFT, the off-state leakage current of coplanar TFT is reduced, while the reduction of the on-state current is relatively small. The p-channel poly-Si TFT with a GOLDD structure exhibited a field effect mobility of 50 cm²/V s and an off-state leakage current of 3.8×10⁻¹¹ A/μm at the drain voltage of −5 V and the gate voltage of 10 V.