pMOS金属栅极材料的研究进展

随着金属氧化物半导体场效应管(metal-oxide-semiconductor field-effect transistors,MOSFETs)等比缩小迈向45nm技术节点,金属栅极已应用于新型MOSFET器件,改善了与高k栅介质的兼容性,并消除了传统多晶硅栅极的栅耗尽及硼穿透等效应.文章综述了pMOS器件金属栅极材料的发展历程、面临的主要问题以及未来的研究趋势等.     

Influence of ultra-thin TiN thickness(1.4 nm and 2.4 nm) on positive bias temperature instability(PBTI)of high-k/metal gate nMOSFETs with gate-last process

The positive bias temperature instability(PBTI) degradations of high-k/metal gate(HK/MG) n MOSFETs with thin Ti N capping layers(1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI(90?C,125?C, 160?C) are studied and activation energy(Ea) values(0.13 e V and 0.15 e V) are extracted. Although the equivalent oxide thickness(EOT) values of two Ti N thickness values are almost similar(0.85 nm and 0.87 nm), the 2.4-nm Ti N one(thicker Ti N capping layer) shows better PBTI reliability(13.41% at 0.9 V, 90?C, 1000 s). This is due to the better interfacial layer/high-k(IL/HK) interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.     

Total Ionization Dose Effects on Charge Storage Capability of Al_2O_3/HfO_2/Al_2O_3-Based Charge Trapping Memory Cell

Because of the discrete charge storage mechanism, charge trapping memory(CTM) technique is a good candidate for aerospace and military missions. The total ionization dose(TID) effects on CTM cells with Al_2O_3/HfO_2/Al_2O_3(AHA) high-k gate stack structure under in-situ 10 keV x-rays are studied. The C-V characteristics at different radiation doses demonstrate that charge stored in the device continues to be leaked away during the irradiation,thereby inducing the shift of flat band voltage(V_(fb)). The dc memory window shows insignificant changes, suggesting the existence of good P/E ability. Furthermore, the physical mechanisms of TID induced radiation damages in AHA-based CTM are analyzed.     

A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors(NMOSFETs)is presented.In the process,a HfSiON gate dielectric with an equivalent oxide thickness of 10 A was prepared by a simple physical vapor deposition method.Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate.After the source/drain formation,the poly-Si dummy gate was removed by tetramethylammonium hydroxide(TMAH)wet-etching and replaced by a TaN metal gate.Because the metal gate was formed after the ion-implant doping activation process,the effects of the high temperature process on the metal gate were avoided.The fabricated device exhibits good electrical characteristics,including good driving ability and excellent sub-threshold characteristics.The device’s gate length is 73 nm,the driving current is 117μA/μm under power supply voltages of VGS=VDS=1.5 V and the off-state current is only 4.4 nA/μm.The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage(~0.24 V)for high performance NMOSFETs.The device’s excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.     

Interface models and processing technologies for surface passivation and interface control in III-V semiconductor nanoelectronics

Interface models and processing technologies are reviewed for successful establishment of surface passivation, interface control and MIS gate stack formation in III-V nanoelectronics. First, basic considerations on successful surface passivation and interface control are given, including review of interface models for the band alignment at interfaces, and effects of interface states in nanoscale devices. Then, a brief review is given on currently available surface passivation technologies for III-V materials, including the Si interface control layer (ICL)-based passivation scheme by the authors’ group. The Si-ICL technique has been successfully applied to surface passivation of nanowires and to formation of a HfO₂ high-k dielectric/GaAs interfaces with low values of the interface state density.     

Interface Evolution of TiN/Poly Si as Gate Material on Si/HfO2 Stack

TiN as gate electrode in Si/HfO₂/TiN/poly-Si stack is evaluated after the postmetal annealing treatments. Interface reactions are investigated usingelectron-energy-loss spectroscopy and x-ray photoelectron spectroscopy. The work function of the TiN/poly-Si stack shows strong dependence on the postmetal deposition annealing conditions. The interfacial product in TiN/poly-Si interface is inferred as TiSiN, which is beneficial for the whole high-k stack since TiSiN possesses higher work function compared to TiN and poly-Si.     

Removal of GaN film over AlGaN with inductively coupled BCl3/Ar atomic layer etch

Atomic layer etching(ALE)of thin film GaN(0001)is reported in detail using sequential surface modification by BCl₃ adsorption and removal of the modified surface layer by low energy Ar plasma exposure in a reactive ion etching system.The estimated etching rate of GaN is~0.74 nm/cycle.The GaN is removed from the surface of AlGaN after 135 cycles.To study the mechanism of the etching,the detailed characterization and analyses are carried out,including scanning electron microscope(SEM),x-ray photoelectron spectroscopy(XPS),and atomic force microscope(AFM).It is found that in the presence of GaCl_x after surface modification by BCl₃,the GaCl_x disappears after having exposed to low energy Ar plasma,which effectively exhibits the mechanism of atomic layer etch.This technique enables a uniform and reproducible fabrication process for enhancement-mode high electron mobility transistors with a p-GaN gate.     

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO7340Q, 7325http://cpb.iphy.ac.cn/CN/10.1088/1674-1056/19/5/057302https://cpb.iphy.ac.cn/CN/article/downloadArticleFile.do?attachType=PDF&id=111774Ge substrate, transistor, HfSiON, hole mobilityProject supported by the National Basic Research Program of China (Grant No.~2006CB302704).Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO$_{x}$ ($1Ge;substrate;transistor;HfSiON;hole;mobilityGe and Si p-channel metal-oxide-semiconductor field-effect-transistors(p-MOSFETs) with hafnium silicon oxynitride(HfSiON) gate dielectric and tantalum nitride(TaN) metal gate are fabricated.Self-isolated ring-type transistor structures with two masks are employed.W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately.Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor(MOS) capacitors may be caused by charge trapping centres in GeOx(1 < x < 2).Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method.The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V.s) and 81.0 cm2/(V.s),respectively.Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.     

小尺寸MOSFET隧穿电流解析模型

基于表面势解析模型，通过将多子带等效为单子带，建立了耗尽/反型状态下小尺寸MOSFET直接隧穿栅电流解析模型.模拟结果与自洽解及实验结果均符合较好，表明此模型不仅可用于SiO₂、也可用于高介电常数(k)材料作为栅介质以及叠层栅介质结构MOSFET栅极漏电特性的模拟分析，计算时间较自洽解方法大大缩短，适用于MOS器件电路模拟. 关键词： 隧穿电流 MOSFET 量子机理 解析模型     

Semiconductor patterning technologies for nano devices

In the era of nano devices, patterning technology encounters many challenges, which arise from not only lithography but also plasma etching. Water-immersion lithography (193 nm) is clearly within sight and many lithography technologies, including extreme ultra-violet (EUV) and other methods, are being developed as the next generation lithography technologies. For nano device etching, introduction of very thin photoresist and more complex device structure requires subtle improvement of etching. Also, the adoption of new materials such as high-k dielectric, metal gate, and phase change materials require more improvement in the view point of profile and selectivity. Finally, since the process window is getting narrower, control and monitoring technologies such as advanced process control (APC) and advanced equipment control (AEC) are strongly required.     

Characteristics of high-quality HfSiON gate dielectric prepared by physical vapour deposition

This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride (HfSiON) on ultrathin SiO₂ buffer layer. The gate dielectric with 10? (1?= 0.1 nm) equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielectric constant (k=14) and low gate-leakage current (I_g=1.9×10^-3A/cm² @V_g=V_fb-1V for EOT of 10?). TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.     

Interface engineering with an MOCVD grown ZnO interface passivation layer for ZrO2-GaAs metal-oxide-semiconductor devices

This work deals with the fabrication of a GaAs metal-oxide-semiconductor device with an unpinned interface environment. An ultrathin (∼2 nm) interface passivation layer (IPL) of ZnO on GaAs was grown by metal organic chemical vapor deposition to control the interface trap densities and to prevent the Fermi level pinning before high-k deposition. X-ray photoelectron spectroscopy and high resolution transmission electron microscopy results show that an ultra thin layer of ZnO IPL can effectively suppress the oxides formation and minimize the Fermi level pinning at the interface between the GaAs and ZrO₂. By incorporating ZnO IPL, GaAs MOS devices with improved capacitance-voltage and reduced gate leakage current were achieved. The charge trapping behavior of the ZrO₂/ZnO gate stack under constant voltage stressing exhibits an improved interface quality and high dielectric reliability.     

Numerical Study on a Lateral Double-Gate Tunnelling Field Effect Transistor

A novel lateral double-gate tunnelling field effect transistor （DG-TFET） is studied and its performance is presented by a two-dimensional device simulation with code ISE. The result demonstrates that this new tunnelling transistor allows for the steeper sub-threshold swing below 60mV/dec, the super low supply voltage （operable at VDD 〈 0.3 V） and the rail-to-rail logic （significant on-state current at the drain-source voltage VDS = 50mV） for the aggressive technology assumptions of the availability of high-k/metal stack with equivalent gate oxide thickness EOT =0.24 nm and the work function difference 4.5 eV of materials.     

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering(FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain(LDD) overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.     

Investigation of a 4H-SiC metal-insulation-semiconductor structure with an Al2O3/SiO2 stacked dielectric

Atomic layer deposited(ALD) Al2O3 /dry-oxidized ultrathin SiO2 films as a high-k gate dielectric grown on 8°off-axis 4H-SiC(0001) epitaxial wafers are investigated in this paper.The metal-insulation-semiconductor(MIS) capacitors,respectively with different gate dielectric stacks(Al2O3/SiO2,Al2O3,and SiO2) are fabricated and compared with each other.The I-V measurements show that the Al2O3/SiO2 stack has a high breakdown field(≥12 MV/cm) comparable to SiO2,and a relatively low gate leakage current of1×10-7A/cm2 at an electric field of4 MV/cm comparable to Al2O3.The 1-MHz high frequency C-V measurements exhibit that the Al2O3/SiO2 stack has a smaller positive flat-band voltage shift and hysteresis voltage,indicating a less effective charge and slow-trap density near the interface.     

Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO₂ than SiO₂ in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, I_ON/I_OFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO₂, DIBL shows a reduction of 61.5% over SiO₂. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO₂ when compared to SiO₂. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO₂ based device. From the analysis, it is found that HfO₂ will be a better alternative for the future nanoscale device.     

In situ measurement of plasma charging on SiO2 hole bottoms and reduction by negative charge injection during etching

Charging damage in the fabrication of a micro- and nanoelectronic device is one of the electrical damages during plasma etching and caused basically by a huge difference of the flux velocity distribution between positive ions and electrons toward the wafer to be processed. Beam-like positive ions are accumulated on the bottom of a miniaturized structure during etching. With the evolution of the technology node, charging damage will increase due to several factors, increase of plasma exposure time, decrease of annealing temperature, and narrow process window, etc., caused by the increase of the number of metal layers and the introduction of new materials such as low-k and high-k instead of SiO₂. The progress of a top-down nanotechnology depends on the development of in situ diagnostics regarding plasma damage to lower-level elements and on the development of charging-free plasma process. In this paper, in situ charging measurements by using a test chip and negative charge injection to the wafer by optical computerized tomography are first demonstrated. Second, we discuss the characteristics of the charging potential on the bottom of SiO₂holes during etching in a two-frequency capacitively coupled plasma (2f-CCP), and refer to the procedure to reduce the positive potential by utilizing the negative charge acceleration to the hole bottom under the artificial formation of a double-layer close to the wafer. In addition, the charging’s effect on the aspect ratio of the hole and the antenna ratio are discussed.     

Influences of different oxidants on characteristics of La_2O_3/Al_2O_3 nanolaminates deposited by atomic layer deposition

A comparative study of two kinds of oxidants(H_2O and O_3) with the combination of two metal precursors(TMA and La(~iPrCp)_3) for atomic layer deposition(ALD) La_2O_3/Al_2O_3 nanolaminates is carried out. The effects of different oxidants on the physical properties and electrical characteristics of La_2O_3/Al_2O_3 nanolaminates are studied. Initial testing results indicate that La_2O_3/Al_2O_3 nanolaminates could avoid moisture absorption in the air after thermal annealing. However, moisture absorption occurs in H_2O-based La_2O_3/Al_2O_3 nanolaminates due to the residue hydroxyl/hydrogen groups during annealing. As a result, roughness enhancement, band offset variation, low dielectric constant and poor electrical characteristics are measured because the properties of H_2O-based La_2O_3/Al_2O_3 nanolaminates are deteriorated. Addition thermal annealing effects on the properties of O_3-based La_2O_3/Al_2O_3 nanolaminates indicate that O_3 is a more appropriate oxidant to deposit La_2O_3/Al_2O_3 nanolaminates for electron devices application.     

Improved high-k stacks with chemical oxide interfacial layer by DPN/PNA treatment

A decoupled plasma nitridation (DPN) with post nitridation annealing (PNA) treatment method was introduced to improve the performances of MOS devices with high-k (HK)-last/gate-last integration scheme and chemical oxide interface layer (IL). By introducing N to form HfSiON, it was found that DPN + PNA treatments could provide smaller equivalent oxide thickness (EOT) for both nMOS and pMOS devices. It was also found that we could achieve the best overall device performance for the HK-last/gate-last integration scheme with a chemical oxide IL by introducing nitrogen gas with low percentage content during DPN followed by high temperature PNA.     

Dry etching of MgCaO gate dielectric and passivation layers on GaN

MgCaO films grown by rf plasma-assisted molecular beam epitaxy and capped with Sc₂O₃ are promising candidates as surface passivation layers and gate dielectrics on GaN-based high electron mobility transistors (HEMTs) and metal-oxide semiconductor HEMTs (MOS-HEMTs), respectively. Two different plasma chemistries were examined for etching these thin films on GaN. Inductively coupled plasmas of CH₄/H₂/Ar produced etch rates only in the range 20-70 Å/min, comparable to the Ar sputter rates under the same conditions. Similarly slow MgCaO etch rates (∼100 Å/min) were obtained with Cl₂/Ar discharges under the same conditions, but GaN showed rates almost an order of magnitude higher. The MgCaO removal rates are limited by the low volatilities of the respective etch products. The CH₄/H₂/Ar plasma chemistry produced a selectivity of around 2 for etching the MgCaO with respect to GaN.