Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO₂ than SiO₂ in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, I_ON/I_OFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO₂, DIBL shows a reduction of 61.5% over SiO₂. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO₂ when compared to SiO₂. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO₂ based device. From the analysis, it is found that HfO₂ will be a better alternative for the future nanoscale device.     

Ge metal oxide semiconductor field effect transistors with optimized Si cap and HfSiO2 high-k metal gate stacks

High mobility metal-oxide-semiconductor-field-effect-transistors (MOSFETs) are demonstrated on high quality epitaxial Si_0.75Ge_0.25 films selectively grown on Si (100) substrates. With a Si cap processed on Si_0.75Ge_0.25 channels, HfSiO₂ high-k gate dielectrics exhibited low C–V hysteresis (<10 mV), interface trap density (7.5 × 10¹⁰), and gate leakage current (∼10⁻²A/cm² at an EOT of 13.4 Å), which are comparable to gate stack on Si channels. The mobility enhancement afforded intrinsically by the Si_0.75Ge_0.25 channel (60%) is further increased by a Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. The Si cap process also mitigates the low potential barrier issues of Si_0.75Ge_0.25 channels, which are major causes of the high off-state current of small band gap energy Si_0.75Ge_0.25 pMOSFETs, by improving gate control over the channel.     

Temperature- and voltage-dependent trap generation model in high-k metal gate MOS device with percolation simulation

High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to the breakdown characteristic.In this work,a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up,and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation.It is found that all degradation factors,such as trap generation rate time exponent m,Weibull slope β and percolation factor s,each could be expressed as a function of trap density time exponent α.Based on the percolation relation and power law lifetime projection,a temperature related trap generation model is proposed.The validity of this model is confirmed by comparing with experiment results.For other device and material conditions,the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.     

绝缘栅双极晶体管串联关键技术

为实现绝缘栅双极晶体管（IGBT）的多级串联,以电阻/电容/二极管（RCD）缓冲电路为动态均压电路,通过数学分析及PSpice仿真验证,建立了RCD缓冲电路参数选择模型;设计了基于数字信号处理器（DSP）控制、光纤隔离传输,以M57962L为IGBT驱动器的驱动电路及故障反馈电路,能驱动32只串联IGBT并对其进行过流和短路保护,32只IGBT的最大导通时间不超过90 ns,短路保护响应时间约为6 s;设计了8路独立输出的50 kV隔离的高压隔离电源,实现IGBT串联电路各部分的供电及电隔离。基于以上IGBT串联方法,实现了32只1200 V IGBT的串联,串联电路可稳定工作在20 kV电压下。     

绝缘栅双极晶体管串联关键技术

为实现绝缘栅双极晶体管（IGBT）的多级串联,以电阻/电容/二极管（RCD）缓冲电路为动态均压电路,通过数学分析及PSpice仿真验证,建立了RCD缓冲电路参数选择模型;设计了基于数字信号处理器（DSP）控制、光纤隔离传输,以M57962L为IGBT驱动器的驱动电路及故障反馈电路,能驱动32只串联IGBT并对其进行过流和短路保护,32只IGBT的最大导通时间不超过90 ns,短路保护响应时间约为6 s;设计了8路独立输出的50 kV隔离的高压隔离电源,实现IGBT串联电路各部分的供电及电隔离。基于以上IGBT串联方法,实现了32只1200 V IGBT的串联,串联电路可稳定工作在20 kV电压下。     

Probing buried interfaces on Ge-based metal gate/high-k stacks by hard X-ray photoelectron spectroscopy

In this contribution, we present results of a non-destructive in-depth analysis of concentration of chemical components at buried interfaces on Ge-based CMOS by means of hard X-ray photoelectron spectroscopy (HAXPES) and low angle X-ray reflectivity (XRR). Two samples composed of a Ge/Si/SiO₂/HfO₂/TiN stack, with layer and interlayer thicknesses of 2500, 0.9, 0.5, 4.9, 3.4 nm and 2500, 0.7, 1, 5.8, 3 nm have been studied. The use of electrons with kinetic energies from few eV up to 15 keV enables to tune the information depth being able to analyze the desired interface in a non-destructive way. XRR enables the determination of the exact layer thickness and density. The results suggest that the Si interlayer prevents the Ge oxidation. Depth profiles of the electronic structure have been obtained for both samples by following the evolution of the photoemission signal from the Hf 2p_3/2 core level as a function of the photoelectron kinetic energy. The depth profile of the electronic structure reveals the presence of a chemical shift of the Hf 2p_3/2 core level, which is related to an interfacial bonding state. Our results demonstrate the excellent capability of HAXPES to study buried interfaces in a non-destructive way.     

Pulsed laser deposited ZrAlON films for high-k gate dielectric applications

ZrAlON films were fabricated using the reactive ablation of a ceramic ZrAlO target in N₂ ambient by pulsed laser deposition (PLD) technique. ZrAlON films were deposited directly on n-Si(100) substrates and Pt coated silicon substrates, respectively, at 500 °C in a 20 Pa N₂ ambient, and rapid thermal annealed (RTA) in N₂ ambient at 1000 °C for 1 min. Cross sectional high-resolution transmission electron microscopy (HRTEM) images clearly show that the ZrAlON/Si interface is atomically sharp without an interfacial layer, and the films are completely amorphous. The electron diffraction pattern of TEM also indicates the amorphous structure of the RTA ZrAlON film. X-ray photoelectron spectroscopy (XPS) measurement was performed to confirm the effective incorporation of nitrogen with a content of about 6 at. %, and to reveal the N–O bonding in ZrAlON films. The dielectric constant of amorphous ZrAlON was determined to be about 18.2 which is more than 16.8 for ZrAlO by measuring the Pt/films/Pt capacitors. Capacitance–voltage (C–V) measurements show that a small equivalent oxide thickness (EOT) of 1.03 nm for 4 nm ZrAlON film on the n-Si substrate with a leakage current of 28.7 mA/cm² at 1 V gate voltage was obtained. PACS 77.55.+f; 81.15.Fg; 73.40.Qv     

Electrical characterization of high-k gate dielectrics on semiconductors

This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks: (1) inelastic electron tunneling spectroscopy (IETS), (2) lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of a MOSFET, and (3) pulse agitated substrate hot electron injection (PASHEI) technique for measuring trapping effects in the gate dielectric at low and modest gate voltages.     

Characterization of high-k gate dielectric/silicon interfaces

We have shown that, for thermally evaporated Ta₂O₅ or ZrO₂ thin films on Si(1 0 0), O₂ annealing at 300–500 °C causes the formation of an interfacial silicon oxide layer as thin as 1–2 nm which can be interpreted in terms of their high permeability to oxygen. And we have demonstrated how useful the energy loss spectra of photoexcited electrons from core levels such as O 1s are to measure the energy bandgaps of very thin insulators. With the combination of measured bandgaps and valence band lineups determined for X-ray photoelectron spectroscopy valence band spectra, we have determined the energy band alignments of Ta₂O₅ and ZrO₂ with Si(1 0 0) before and after the O₂ annealing at 500 °C. In addition, we have demonstrated that total photoelectron yield spectroscopy provides us direct information to quantify the energy distributions of both the defect states in the high-k dielectrics and the dielectric/Si(1 0 0) interface states over nearly entire Si bandgap.     

稀土元素掺杂的Hf基栅介质材料研究进展

随着金属氧化物半导体场效应管(MOSFETs)等比缩小到45 nm技术节点,具有高介电常数的栅介质材料(高k材料)取代传统的SiO₂已经成为必然,然而Hf基高k材料在实际应用中仍然存在许多不足,而稀土元素掺杂在提高Hf基栅介质材料的k值、降低缺陷密度、调整MOSFETs器件的阈值电压等方面表现出明显的优势.本文综述了Hf基高k材料的发展历程,面临的挑战,稀土掺杂对Hf基高k材料性能的调节以及未来研究的趋势. 关键词： k栅介质')" href="#">Hf基高k栅介质 稀土掺杂 氧空位缺陷 有效功函数     

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

A multi-deposition multi-annealing technique(MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device's performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown(TDDB) characteristics of positive channel metal oxide semiconductor(PMOS) under different MDMA process conditions, including the deposition/annealing(DA) cycles, the DA time, and the total annealing time. The results show that the increases of the number of DA cycles(from 1 to 2) and DA time(from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail(TTF) at 63.2% increases by about several times. However, too many DA cycles(such as 4 cycles) make the equivalent oxide thickness(EOT) increase by about 1 ?A and the TTF of PMOS worsen. Moreover, different DA times and numbers of DA cycles induce different breakdown mechanisms.     

High performance trench MOS barrier Schottky diode with high-k gate oxide

A novel trench MOS barrier Schottky diode(TMBS) device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS.     

Study on two-dimensional analytical models for symmetrical gate stack dual gate strained silicon MOSFETs

Based on the exact resultant solution of two-dimensional Poisson’s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.     

Y掺杂Al2O3高k栅介质薄膜的制备及性能研究

利用射频反应共溅射方法制备了Y掺杂Al2O3电介质薄膜,用掠入射x射线衍射检测了薄膜的结构,用高分辨率扫描电子显微镜(HRSEM)、原子力显微镜(AFM)观察了薄膜断面和表面形貌,用高频C-V和变频C-V及J-V测量了样品的电学特性.结果表明,Y的掺入使电介质薄膜的介电常数k有了很大提高(8.14-11.8),并体现出了较好的介电特性.分析认为:与氧具有较大电负性差的Y离子的加入,增大了薄膜中的金属-氧键(M-O)的强度;同时,Y的加入使Al2O3的结构和原子配位发生了改变,从而提高了离子极化对薄膜介电常数的贡献.退火前后的XRD谱均显示薄膜为非晶态;HRSEM断面和AFM形貌像显示所制备的薄膜非常平整,能够满足器件要求.     

LaTiO高k栅介质Ge MOS电容电特性及Ti含量优化

采用共反应溅射法将Ti添加到La_2O_3中,制备了LaTiO/Ge金属-氧化物-半导体电容,并就Ti含量对器件电特性的影响进行了仔细研究.由于Ti-基氧化物具有极高的介电常数,LaTiO栅介质能够获得高k值;然而由于界面/近界面缺陷随着Ti含量的升高而增加,添加Ti使界面质量恶化,进而使栅极漏电流增大、器件可靠性降低.因此,为了在器件电特性之间实现协调,对Ti含量进行优化显得尤为重要.就所研究的Ti/La_2O_3比率而言,18.4%的Ti/La_2O_3比率最合适.该比率导致器件呈现出高k值(22.7)、低D_(it)(5.5×10~(11)eV~(-1)·cm~(-2))、可接受的J_g(V_g=1V,J_g=7.1×10~(-3)A·cm~(-2))和良好的器件可靠性.     

考虑量子效应的高k栅介质SOIMOSFET特性研究

本文主要研究考虑量子效应的高k栅介质SOIMOSFET器件特性．通过数值方法自治求解薛定谔方程和泊松方程,得到了垂直于SiO2／Si界面方向上载流子波函数及能级的分布情况,结合Young模型,在考虑短沟道效应和高庀栅介质的情况下,对SOIMOSFET的阈值电压进行模拟分析．结果表明：随着纵向电场的增加,量子化效应致使反型层载流子分布偏离表面越来越严重,造成了有效栅氧化层厚度的增加和阈值电压波动．采用高向栅介质材料,可以减小阈值电压,抑制DIBL效应．较快的运算速度保证了模拟分析的效率,计算结果和ISE仿真结果的符合说明了本文的模型精度高．     

Comparative study of pulsed laser deposited HfO2 and Hf–aluminate films for high-k gate dielectric applications

The thermal stability and the electrical properties of HfO₂ and Hf–aluminate films prepared by the pulsed laser deposition technique have been investigated by X-ray diffraction, differential thermal analysis, capacitance–voltage correlation, leakage-current measurements and high-resolution transmission electron microscopy observation, respectively. A crystallization transformation from HfO₂ amorphous phase to polycrystalline monoclinic structure occurs at about 500 °C. In contrast, the amorphous structure of Hf–aluminate films remains stable at higher temperatures up to 900 °C. Rapid thermal annealing at 1000 °C for 3 min leads to a phase separation in Hf–aluminate films. Tetragonal HfO₂(111) is predominant, and Al₂O₃ separates from Hf–aluminate and is still in the amorphous state. The dielectric constant of amorphous HfO₂ and Hf–aluminate films was determined to be about 26 and 16.6, respectively, by measuring a Pt/dielectric film/Pt capacitor structure. A very small equivalent oxide thickness (EOT) value of 0.74 nm for a 3-nm physical thickness Hf–aluminate film on a n-Si substrate with a leakage current of 0.17 A/cm² at 1-V gate voltage was obtained. The interface at Hf–aluminate/Si is atomically sharp, while a thick interface layer exists between the HfO₂ film and the Si substrate, which makes it difficult to obtain an EOT of less than 1 nm. PACS 77.55.+f; 81.15.Fg; 73.40.Qv     

Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown(TDDB) characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer.From the charge pumping measurement and secondary ion mass spectroscopy(SIMS) analysis,it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density.In addition,the influences of interface and bulk trap density ratio N_(it)/N_(ot) are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo(kMC) method.The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.