Packaging technology for 40-Gb/s optical receiver module with anMU-connector interface

A compact 40-Gb/s optical receiver module with an MU-connector interface has been developed. Its packaging has three main technical features. (1) Coplanar waveguide (CPW) patterns of the waveguide photodiode (WG-PD) and of the preamplifier IC in the facing area of the flip-chip structure are optimized for impedance matching. (2) A film carrier is used to connect the preamplifier IC to an electrical coaxial connector for electrical signal output. (3) An MU-connector is used as the optical interface to reduce the module size. Optimum design enabled a module size of 14.0 mm wide, 40.4 mm long, and 9.65 mm high. Measurements showed a 3-dB down bandwidth of the optical/electrical response of at least 50 GHz and a clear open eye pattern for a 40-Gb/s nonreturn-to-zero (NRZ) signal input. This optical receiver module is suitable for large-capacity communication network systems     

A 25-Gb/s inductorless SiGe BiCMOS receiver for 100-Gb/s optical links

This paper presents the design and measurements of a 25-Gb/s inductorless optical receiver in a 0.25-μm SiGe BiCMOS process for 100-Gb/s (25-Gb/s × 4 lines) Ethernet. As the first stage of the proposed optical receiver, a transimpedance amplifier (TIA) employing a pseudo-differential structure with a feedback resistor incorporates DC offset cancellation (DOC) to enhance the input dynamic range. Cascaded by the improved two-stage limiting amplifiers and a 50-Ω output buffer, the receiver achieves high differential swings. For a bit-error rate (BER) of 10⁻¹² at 25 Gb/s, the measured transimpedance gain, bandwidth, sensitivity, and output swing are 63.17 dBΩ, 20.7 GHz, −10.3 dBm, and 352.7 mV, respectively. The power consumption of the entire receiver is 111.6 mW and the core area of the die is 640 μm × 135 μm.     

Experimental study on optically band-limited 40-Gb/s RZ signals with optically time-division demultiplexing receiver

The impact of optical filtering on 40-Gb/s return-to-zero (RZ) signals was experimentally investigated with an optically time-division multiplexing (OTDM) receiver. Through the evaluation of the signal performance by changing the interpulse-phase conditions of the symmetrically band-limited 40-Gb/s signals, we have confirmed that similar performance was obtained regardless of the interpulse-phase condition, owing to the pulse-reshaping capability of an OTDM receiver. A performance comparison was also conducted between symmetrically and asymmetrically filtered 40-Gb/s RZ signals. It was found that the symmetrically filtered signal was more tolerant for the dispersion-compensation error, while the asymmetrically filtered signal was more tolerant for fiber nonlinearity with optical filters that have a 3-dB bandwidth of 45 GHz.     

Novel and simple model of 10-Gb/s electroabsorption modulated lasers and its experimental validation of transmission performance due to overshoot of optical signals

We have experimentally and theoretically investigated the transmission performance of 10-Gb/s electroabsorption modulated lasers (EMLs) due to the overshoot of optical pulses. When a highly negative bias voltage is applied to EMLs, the overshoot becomes larger due to nonlinear transfer curves of EMLs. In order to further understand the overshoot effect of optical pulses from EMLs on transmission performance, we propose a novel and simple EML model based on the frequency response (magnitude and phase) and the transfer curves (P-V and /spl alpha/-V) of EMLs. Although the model does not solve the rate equations and the wave equations, it can accurately predict output pulse shapes and the frequency chirp as well as the transmission performance with reducing simulation time. Using the EML model, we can calculate the overshoot and dispersion power penalty due to modulation bandwidth and group delay difference in 10-Gb/s EMLs. Our results suggest that the overshoot should be considered to accurately predict the transmission performance of 10-Gb/s EMLs.     

Si bipolar chip set for 10-Gb/s optical receiver

Three Si bipolar ICs, a preamplifier, a gain-controllable amplifier, and a decision circuit, have been developed for 10-Gb/s optical receivers. A dual-feedback configuration with a phase adjustment capacitor makes it possible to increase the preamplifier bandwidth up to 11.2 GHz, while still retaining flat frequency response. The gain-controllable amplifier, which utilizes a current-dividing amplifier stage, has an 11.4-GHz bandwidth with 20-dB gain variation. A master-slave D-type flip-flop is also operated as the decision circuit at 10 Gb/s. On-chip coplanar lines were applied to minimize the electrical reflection between the ICs     

Clock and data recovery IC for 40-Gb/s fiber-optic receiver

The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.     

2.5-Gb/s low-jitter low-power monolithically integrated optical receiver

A high-scale integrated optical receiver including a preamplifier, a limiting amplifier, a clock and data recovery (CDR) block, and a 1:4 demultiplexer (DEMUX) has been realized in a 0.25???m CMOS technology. Using the loop parameter optimization method and the low-jitter circuit design technique, the rms and peak-to-peak jitter of the recovered 625-MHz clock are 9.4 and 46.3?ps, respectively, which meet the jitter specifications stipulated in ITU-T recommendation G.958. The recovered and frequency divided 625?MHz clock has a phase noise of ?83.8 dBc/Hz at 20?kHz offset in response to 2.5?Gb/s PRBS input data (2²³?C1), and the 2.5?Gb/s PRBS data has been demultiplexed into four 625?Mb/s data. The power dissipation is only 0.3?W under a single 3.3 V supply (excluding output buffers).     

Monolithic integration of 5-Gb/s optical receiver block for shortdistance communication

The authors developed an optical receiver block for applications such as board-to-board or chip-to-chip data communications. They implemented the optical receiver block with an interdigit metal-semiconductor-metal (MSM)type photodetector and 0.35-μm gate junction FETs which were monolithically integrated on a GaAs substrate. High-speed operation of 5 Gb/s was observed with a relatively low power consumption of 8.2 mW     

40-Gb/s optical 3R regenerator using electroabsorption modulatorsfor optical networks

A 40-Gb/s optical retiming, reshaping, and retransmitting (3R) regenerator was proposed and demonstrated using wavelength converters based on electroabsorption (EA) modulators for effectively implementing 40-Gb/s-based or higher bit rate wavelength division multiplexing (WDM) optical networks. The proposed optical 3R regenerator is configured in a very simple architecture, consisting of two wavelength converters, a clock recovery section, and an optical clock generator section. Furthermore, the stable and polarization-insensitive operation, as well as simple adjustment of an optimal operation condition of our proposed optical 3R regenerator, were confirmed by conducting transmission experiments. To investigate the applicability of optical 3R regenerators to optical networks, it was evaluated by insertion between two 500-km-long segments of transmission line. A Q-factor improvement of about 1.5 dB was obtained after transmission over 1000 km, compared to evaluation without the regenerator. This type of optical 3R regenerator proves extremely useful in future high-speed and scaleable all-optical networks     

Wide temperature operation of 40-Gb/s 1550-nm electroabsorption modulated lasers

Electroabsorption modulated lasers (EMLs) exploiting the quantum confined Stark effect need thermoelectric coolers to achieve stable output power levels and dynamic extinction ratios. Temperature-independent operation is reported between 20/spl deg/C and 70/spl deg/C for InGaAlAs-InP-based monolithically integrated 1550-nm EMLs exploiting a shared active area at 40 Gb/s by actively controlling the electroabsorption modulator bias voltage. Dynamic extinction ratios of at least 8 dB and fiber-coupled mean modulated optical power of at least 0.85 mW are obtained over the mentioned temperature range.     

Numerical comparison between distributed and discrete amplificationin a point-to-point 40-Gb/s 40-WDM-Based transmission system with threedifferent modulation formats

We describe a detailed numerical investigation on the relative merits of gain flattened distributed Raman amplification (DRA) and discrete gain flattened amplifiers. We simulate a system with forty 40-Gb/s channels spaced at 100 GHz and compare the performance of three different modulation formats nonreturn-to-zero (NRZ), return-to-zero (RZ) and carrier-suppressed RZ (CS-RZ). Three types of amplifiers, multifrequency backward- and forward-pumped DRAs, and an idealized discrete gain flattened amplifier are examined for various signal powers and transmission distances. For the backward-pumped DRA, we also describe calculated tolerance limits imposed by incomplete dispersion slope compensation and polarization mode dispersion (PMD) level     

40-Gb/s X-cut LiNbO/sub 3/ optical modulator with two-step back-slot structure

We propose a newly designed X-cut lithium niobate (LiNbO/sub 3/) optical modulator. It has a two-step back-slot structure to satisfy the velocity-matching condition without the buffer layer of silicon dioxide (SiO/sub 2/). Accordingly, this modulator can achieve low drive voltage and low optical insertion loss. In addition, the dc-drift phenomena due to the buffer layer can be suppressed. This structure is fabricated with micromachining technology using excimer laser ablation. The optical 3-dB bandwidth of the fabricated modulator reaches 30 GHz, and the drive voltage is less than 3 V at 1 kHz. From the measurement of the optical eye diagram at 43.5-Gb/s, clear eye openings were obtained. This modulator is sufficient for 40-Gb/s optical transmission systems.     

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.     

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a triple-inductive transimpedance amplifier (TIA), direct current (DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers (VGA), and a reference-less clock and data recovery (CDR) circuit with built-in equalization technique. The TIA/VGA front-end measurement results demonstrate 72-dBΩ transimpedance gain, 20.4-GHz −3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10⁻¹² BER at 26 Gb/s for a 2¹⁵−1 PRBS input with a −7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.     

InP-HBT chip-set for 40-Gb/s fiber optical communication systemsoperational at 3 V

A chip set for a 40 Gb/s fiber optical communication system has been designed and fabricated. On-wafer measurements have been performed to verify circuit operations. As far as available measurement capabilities show, all circuits are functionally fulfilling specifications for 10 Gb/s operation at less than or equal to 3 V supply voltage. During the design phase especially the influence of interconnects on signal integrity was investigated and the results were implemented for automatic extraction. All the circuits were operational after the first processing round. No redesign was necessary     

10- and 40-Gb/s forward error correction devices for optical communications

Two standard forward error correction (FEC) devices for 10- and 40-Gb/s optical systems are presented. The first FEC device includes RS(255, 239) FEC, BCH(4359, 4320) FEC, and standard compliant framing and performance monitoring functions. It can support a single 10-Gb/s channel or four asynchronous 2.5-Gb/s channels. The second FEC device implements RS(255, 239) FEC at a data rate of 40 Gb/s. This paper presents the key ideas applied to the design of Reed-Solomon (RS) decoder blocks in these devices, especially those for achieving high throughput and reducing complexity and power. Implemented in a 1.5-V, 0.16-/spl mu/m CMOS technology, the RS decoder in the 10-Gb/s, quad 2.5-Gb/s device has a core gate count of 424 K and consumes 343 mW; the 40-Gb/s RS decoder has a core gate count of 364 K and an estimated power consumption of 360 mW. The 40-Gb/s RS FEC is the highest throughput implementation reported to date.     

Investigation of system upgradability over installed fiber-optic cable using 40-Gb/s WDM signals toward multiterabit optical networks

An investigation of system upgradability of installed fiber-optic cable was conducted using 40-Gb/s wavelength-division-multiplexing (WDM) signals toward multiterabit optical networks. A field trial of 63-channel 40-Gb/s dispersion-managed soliton WDM signal transmission was successfully demonstrated over 320-km (4 /spl times/ 80-km) installed nonzero-dispersion-shifted fibers. The average Q factor of 15.4 dB was obtained, and very stable long-term bit-error-ratio performance was confirmed without polarization-mode dispersion compensation. This system upgradability investigation in the field environment provided the confidence to introduce 40-Gb/s technologies and effectively to construct multiterabit optical networks following the demand increase in the future.     

High performance 10 Gbit/s pin-FET optical receiver

An optical receiver suitable for a 10 Gbit/s direct detection optical transmission system is described. It uses a pin diode, commercial GaAs MESFETs and hybrid construction techniques on a coplanar substrate. The measured sensitivity of the receiver is -20.4 dBm, which is the best reported sensitivity at 10 Gbit/s for a pin-FET optical receiver to date.<>     

A 1-Gb/s, 0.7-μm CMOS optical receiver with full rail-to-railoutput swing

This paper presents a 1-Gb/s optical receiver with full rail-to-rail output swing realized in a standard 0.7-μm CMOS technology. The receiver consists of a 1-kΩ transimpedance preamplifier followed by a postamplifier based on a biased inverter chain. The latter performs both a linear and a limiting amplification. The automatic biasing of the chain is provided through an offset tolerant replica circuit. The receiver requires no external components or biasing voltages. It is designed for a relatively large 0.8-pF input capacitance and is fed from a single 5-V power supply. These properties make the circuit suitable for a commercial environment. A sensitivity of 10 μA was measured at 1 Gb/s. The complete receiver, including all biasing and replicas, consumes approximately 100 mW from the 5-V supply. When powered from a 3.3-V supply, a maximal bit rate of 600 Mb/s is achieved, while the power consumption is reduced to approximately 26.5 mW