Cu/low-k dielectric TDDB reliability issues for advanced CMOS technologies

With the wide application of low-k and ultra-low-k dielectric materials at the 90 nm technology node and beyond, the long-term reliability of such materials is rapidly becoming a critical challenge for technology qualification. Low-k time-dependent dielectric breakdown (TDDB) is usually considered as one of the most important reliability issues during Cu/low-k technology development because low-k materials generally have weaker intrinsic breakdown strength than traditional SiO₂ dielectrics. This problem is further exacerbated by the aggressive shrinking of the interconnect pitch size due to continuous technology scaling. In this paper, three critical issues of low-k TDDB characteristics during low-k development and qualification will be reviewed. In the first part, a low-k TDDB field acceleration model and its determination will be discussed. In the second part, low-k dielectric time-to-breakdown (t_BD) statistical distribution and TDDB area scaling law for reliability projection will be examined. In the last part, as low-k TDDB has been found to be sensitive to all aspects of integration, the effects of process variations on low-k TDDB degradation will be demonstrated. Some key aspects which need to be carefully addressed to control overall low-k TDDB performance from process and integration side will be discussed.     

ESD issues for advanced CMOS technologies

As technologies advance towards the deep submicron, the ESD protection design issues have been known to become more critical. This paper examines the recent trends in ESD protection designs, the technology impact, and the specific approaches to build-in ESD reliability. It is shown that the efficient performance of advanced protection designs requires an optimized process that can meet the ESD robustness criterion.     

Impact of wafer charging on hot carrier reliability and optimization of latent damage detection methodology in advanced CMOS technologies

We have studied the possibility to use hot carrier stresses to reveal the latent damage due to Wafer Charging during plasma process steps in 0.18 μm and 0.6 μm CMOS technologies. We have investigated various hot carrier conditions in N- and PMOSFETs and compared the results to classical parametric studies and short electron injections under high electric field in Fowler–Nordheim regime, using a sensitivity factor defined as the relative shift towards a reference protected device. The most accurate monitor remains the threshold voltage and the most sensitive configuration is found to be short hot electron injections in PMOSFET’s. The ability of very short hot electron injections to reveal charging damage is even more evidenced in thinner oxides and the better sensitivity of PMOSFET is explained in terms of conditions encountered by the device during the charging process step.     

Some issues in advanced CMOS gate stack performance and reliability

This paper summarizes and analyzes some of our previous works on the advanced gate stacks for CMOS transistors focused on the following two topics: 1. Frequency dependence of Dynamic Bias Temperature Instability (DBTI) and the transistor degradation mechanism, 2. A novel way for metal gate Effective Work Function (EWF) modulation by incorporation of lanthanum elements in HfO₂ gate dielectric.     

Channel hot carrier effects in n-MOSFET devices of advanced submicron CMOS technologies

A review of the channel hot carrier (CHC) mechanism and its effects on n-MOSFET devices of deep submicron CMOS bulk technologies is presented. Even with power supply reduction (V_supply ≈ 1.0 V) CHC effects still limit aggressive transistor scaling. In this work it is shown that the “Lucky Electron Model” picture is not adequate to describe carrier heating under quasi ballistic transport. A more general physical picture is proposed, in which the driving force of the hot carrier damage is the “carrier dominant energy” determined by the energy convolution of the effective interface states generation (ISG) cross section (S_IT(E)) and the electron energy distribution function (EEDF) at given bias stress conditions. Both the CHC LEM and the energy driven approximations are derived. The latter is shown to be more adequate to describe the CHC degradation with supply voltage reduction. This approach allows an experimental quantification of S_IT(E).     

Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.     

ESD protection design for I/O libraries in advanced CMOS technologies

There are several approaches for ESD protection of integrated circuits. This paper provides practical guidelines to I/O library designers to choose the right methodology for ESD protection of I/O libraries in advanced CMOS technologies. Guidelines are provided predominantly for low-voltage I/O libraries that are commonly used for general purpose interfaces and industrial low-voltage interfaces such as DDR, MLB, USB, etc. Additionally, some general background issues of ESD protection methodologies used in the industry are considered. This paper is focused on HBM and MM ESD protection solutions. Special CDM ESD protection solutions are not considered.     

Review of fuse and antifuse solutions for advanced standard CMOS technologies

Specific applications require large amounts of high-performance, dense and low-cost non-volatile memories with CMOS standard process compatibility. There exists numerous structures for one-time-programming (OTP) bitcells, exploiting various physical phenomena as programming modes. Not all of these physical phenomena will behave in a satisfactory manner with the CMOS technology shrink. Moreover, it is not easy to evaluate the effect of geometry and technology on the trade-off between density and reliability of the OTP bitcells.This paper aims to review literature about OTP memories and show that metal fuse, polyfuse and antifuse are the best candidates so far. Other memories require either additional masks with regards to core process, additional technological steps or unaffordable programming conditions. Significant results will be listed in comparison tables.This paper also wishes to give a summary of the physical phenomena involved in bitcell architectures. Opinions are given about the suitability of OTP architectures for specific applications, the most suitable bitcell architectures have been layouted in 65 and 45 nm for density comparison purpose. Particularly, promising structures are manufactured and characterized as they present fair trade offs for standard CMOS process. Discussion and conclusion are intended to give a comprehensive review about the parameters impacting the performances, the density and the cost of the OTP bitcell. Comparison tables are edited with the most pertinent parameters and available results.     

Analysis of width edge effects in advanced isolation schemes fordeep submicron CMOS technologies

The evolution of the active area/isolation transition has resulted in modification of the isolation induced parasitic effects on the device. Based on experimental and simulation results, this paper presents an analysis of the corner parasitic effects induced by an abrupt transition. The substrate bias, transistor length and width dependence of the corner effect Is studied. It is shown that the corner parasitic transistor is less sensitive to short channel and substrate bias effects. The parasitic effect behavior as a function of certain technological parameters is studied by simulating the isolation process. It is demonstrated that certain technological parameters linked to the isolation process must be perfectly controlled for a good integration of future isolation technologies, especially for shallow trench isolation (STI)     

Device to circuit reliability correlations for metal gate/high-k transistors in scaled CMOS technologies

Metal gate/high-k stacks are in CMOS manufacturing since the 45 nm technology node. To meet technology performance and yield targets, gate stack reliability is constantly being challenged. Assessing the associated reliability risk for CMOS products relies on a solid understanding of device to circuit reliability correlations. In this paper we summarize our findings on the correlation between device reliability and circuit degradation and highlight areas for future work to focus on.     

Synchronization reliability in CMOS technology

The synchronization performance of CMOS circuits is examined theoretically and experimentally. Criteria for maximizing CMOS gain are determined and are then compared with NMOS gain curves. The phase characteristics of metastability are identified. Experimental measurements of error rate are made on a CMOS test circuit, and the gain-bandwidth product for the circuit is determined from these data.     

Designing low-power digital CMOS

The increasing levels of circuit integration are leading to the implementation of highly sophisticated algorithms. Many of the commercial application areas have a requirement for portability, which leads to the need for low-power design. This paper considers the issues and design solutions for complex low-power digital CMOS IC design     

RF CMOS reliability simulations

We present a simulation approach to assess the reliability of an RF CMOS circuit under user conditions, based on existing DC degradation models for gate-oxide breakdown and hot-carrier degradation. The simulator allows for lifetime prediction of circuits that can withstand multiple breakdown events. Simulation results show that three power amplifiers with comparable initial circuit performance show an astronomic difference in reliability. The tool thus proves to be an asset in the analog design process.     

Updating of CMOS reliability

Updated results of massive life tests on CMOS are reported. The failure rate derived from laboratory conditions is extrapolated for long life use and compared with field results. Failure mechanism distribution is also reported.     

CMOS integrated circuit reliability

This paper summarizes recently published data on CMOS integrated circuit failure rates, and provides information on the effects of voltage, temperature, device complexity, and packaging on CMOS failure rates. Other factors which can affect failure rate are also indicated, including designs, materials, processes, in-process controls, screening tests, and product maturity. Data on failure rates of NMOS and PMOS integrated circuits are provided to enable comparison with CMOS data. It is concluded that available data do not indicate any consistent reliability difference for CMOS versus NMOS or PMOS integrated circuits. Because of the many advantages of CMOS integrated circuit technology, continued increase in usage of CMOS circuits has been forecast, accompanied by further increases in CMOS integrated circuit reliability.     

Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies

This paper introduces a new distributed active MOSFET rail clamp network that offers surprising advantages in layout area efficiency, bus resistance tolerance, design modularity, and ease of reuse. SPICE simulation results using an extended vertical PNP bipolar transistor compact model and a new method for optimizing distributed rail clamp networks are presented along with chip-level test results.     

Impact of advanced processing modules on the low-frequency noise performance of deep-submicron CMOS technologies

Fundamental studies related to the low-frequency (LF) noise performance in semiconductors started more than 40 years ago. In 1957, McWhorter published the first model for the 1/f noise in semiconductors, which is still in use. Whereas for many decades LF noise studies were mainly of fundamental and theoretical interests, in recent years, LF noise characterisation has become a very valuable diagnostic technique for the development of semiconductor materials and devices. Especially, the use of noise characterisation as a tool for reliability predictions has triggered the semiconductor engineering society. Not only the silicon starting material, but also many of the used process modules have a strong impact on the noise performance. This trend is becoming even more pronounced for the advanced deep-submicron technologies. For analog applications of scaled technologies, LF noise may even act as a showstopper. This review, therefore, focuses on the impact of advanced processing on the low-frequency noise behaviour. Both front- and back-end process modules are discussed.     

A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies

A novel power supply protection clamp is presented which incorporates feedback techniques to improve ESD and normal operational mode behavior. The design uses a short duration RC trigger, which enables the clamp to tolerate very fast power supply ramp rates and exhibit reduced area and leakage. The design is built in a 90 nm CMOS technology with fully salicided source/drain regions.