SOA注入电流及位置偏移量对TOAD开关窗口的影响

对影响太赫兹光学非对称解复用器(TOAD)开关窗口的半导体光放大器(SOA)的注入电流和在环路中的偏移量这两个因素进行了数值模拟及实验研究，加大注入电流可以增加SOA的增益，使得开关窗口的高度增加；SOA在环路中的偏移量决定了开关窗口的宽度。由于实验中用连续光代替信号脉冲以观察开关窗口，可以看到随着偏移量的增大，开关窗口的主窗口的宽度先增大，当窗口宽度为控制脉冲周期的一半后，开关窗口的主窗口的宽度又变小。     

Architecture design,performance analysis and VLSI implementation of a reconfigurable shared buffer for high‐speed switch/router

Modern switches and routers require massive storage space to buffer packets. This becomes more significant as link speed increases and switch size grows. From the memory technology perspective, while DRAM is a good choice to meet capacity requirement, the access time causes problems for high‐speed applications. On the other hand, though SRAM is faster, it is more costly and does not have high storage density. The SRAM/DRAM hybrid architecture provides a good solution to meet both capacity and speed requirements. From the switch design and network traffic perspective, to minimize packet loss, the buffering space allocated for each switch port is normally based on the worst‐case scenario, which is usually huge. However, under normal traffic load conditions, the buffer utilization for such configuration is very low. Therefore, we propose a reconfigurable buffer‐sharing scheme that can dynamically adjust the buffering space for each port according to the traffic patterns and buffer saturation status. The target is to achieve high performance and improve buffer utilization, while not posing much constraint on the buffer speed. In this paper, we study the performance of the proposed buffer‐sharing scheme by both a numerical model and extensive simulations under uniform and non‐uniform traffic conditions. We also present the architecture design and VLSI implementation of the proposed reconfigurable shared buffer using the 0.18 µm CMOS technology. Our results manifest that the proposed architecture can always achieve high performance and provide much flexibility for the high‐speed packet switches to adapt to various traffic patterns. Furthermore, it can be easily integrated into the functionality of port controllers of modern switches and routers. Copyright © 2008 John Wiley & Sons, Ltd.     

自由空间奇数端口非对称型光开关研究

有别于传统的偶数端口对称型光开关设计,本文采用积木叠层方法设计,结构非对称、奇数端口的2×3和3×3光开关;各光开关基本功能单元结构类似,均由偏振光分束器(PBS)、相位型空间光调制器(PSLM)和反射镜组成;利用成熟的偏振控制技术实现信号光的控制和路由选择,有效避免路径的冲突与阻塞。这种设计具有结构简单紧凑、控制方便灵活、双向操作、与偏振无关、即插即用、易集成、易扩容和升级等特点。对2×2光开关单元的实验分析表明,该光开关插损小、串扰低和可靠性高,对于构建大规模的奇数端口和非对称结构的交换矩阵有帮助。     

Design and implementation of a scalable switch architecture for efficient high‐speed data multicasting

This paper presents the design and implementation of a new scalable cell‐based multicast switch fabric for broadband communications. Using distributed control and modular design, the multicast balanced gamma switch features a scalable, high performance architecture for unicast, multicast and combined traffic under both uniform and non‐uniform traffic conditions. The important design characteristic of the switch is that a distributed cell replication function for multicast cells is integrated into the functionality of the switch element with the self‐routing and contention resolution functions. Thus, no dedicated copy network is required. In the paper, we discuss in detail the design issues associated with the multicast functionality of the switch using 0.18 µm CMOS technology and discuss the scalability of the switch in terms of architectural, implementation, and performance scalability. Synthesized results are provided for measures of circuit complexity and timing. Copyright © 2006 John Wiley & Sons, Ltd.     

非对称型多级混洗网络拓扑结构与路由研究

为了避免完全无阻塞型crossbar网络拓扑结构复杂、硬件成本高的缺点,以及可重排无阻塞型多级光互连网络链路函数不一致引起的光学实现困难等问题,提出和设计具有相同链路结构的多级光互连网络,对其拓扑结构进行详细的分析与比较,将其路由算法进行优化,并用于8×8omega+omega网络的路由判断和节点状态的确定。结果表明,该多级混洗光互连网络具有结构简单、操作性强、控制灵活、路由算法时间短、路径选择简并度高和易扩容升级等特点,能够实现输入信号的完全无阻塞输出与排序。