Fast Quantum-Dot Cellular Automata Adder/Subtractor Using Novel Fault Tolerant Exclusive-or Gate and Full Adder

Quantum-dot Cellular automata is a promising area to implement digital systems at nano scale level. Adders and subtractors are widely used in almost every digital information processing system. This work targets to design an efficient 8-bit adder/subtractor that can perform addition as well as subtraction by using a novel control signal distribution scheme. To perform controlled inversion of inputs a novel exclusive-or gate with fewer cells is proposed. During Quantum-dot Cellular automata circuit fabrication, missing cell defects have the potential to affect the performance of a circuit. The proposed designs have higher fault resistance to missing cell defects compared to the existing state-of-the-art designs. Results demonstrate that the proposed design has (N-2) less clock phases compared to the existing state-of-the-art designs. The proposed design can be extended to implement any N-bit adder/subtractor. All the designs are designed and verified using coherence vector simulation engine in QCADesigner.

     

On Design of Parity Preserving Reversible Adder Circuits

In this paper novel parity preserving reversible logic blocks are presented and verified. Then, we present cost-effective parity preserving reversible implementations of Full Adder, 4:2 Compressor, Binary to BCD converter, and BCD adder using these blocks. The proposed parity preserving reversible BCD adder is designed by cascading the presented 4-digit parity preserving reversible Full Adder and a parity preserving reversible Binary to BCD Converter. In this design, instead of realizing the detection and correction unit, we design a Binary to BCD converter that its inputs are the output of parity preserving binary adder, and its output is a parity preserving BCD digit. In addition, several theorems on the numbers of garbage outputs, constant inputs, quantum cost and delay of the designs have been presented to show its optimality. In the presented circuits, the delay and the quantum cost are reduced by deriving designs based on the proposed parity preserving reversible blocks. The advantages of the proposed designs over the existing ones are quantitatively described and analysed. All the scales are in the Nano-metric area.     

Mach-Zehnder interferometer-based all-optical reversible logic gate

In recent years, reversible logic has emerged as a promising computing paradigm having application in low-power CMOS, quantum computing, nanotechnology and optical computing. Optical logic gates have the potential to work at macroscopic (light pulses carry information), or quantum (single photons carry information) levels with great efficiency. However, relatively little has been published on designing reversible logic circuits in all-optical domain. In this paper, we propose and design a novel scheme of Toffoli and Feynman gates in all-optical domain. We have described their principle of operations and used a theoretical model to assist this task, finally confirming through numerical simulations. Semiconductor optical amplifier (SOA)-based Mach-Zehnder interferometer (MZI) can play a significant role in this field of ultra-fast all-optical signal processing. The all-optical reversible circuits presented in this paper will be useful to perform different arithmetic (full adder, BCD adder) and logical (realization of Boolean function) operations in the domain of reversible logic-based information processing.     

Design of Ultra-Efficient Reversible Gate Based 1-bit Full Adder in QCA with Power Dissipation Analysis

The difficulties which the CMOS technology is facing at the nano scale has led to the investigation of quantum-dot cellular automata (QCA) nanotechnology and reversible logic as an alternative to conventional CMOS technology. In this paper, these two paradigms have been combined. Firstly, a new 3 × 3 reversible gate, SSG-QCA, which is universal and multifunctional in nature, is proposed and implemented in QCA using conventional 3-input majority voter based logic. By using the concept of explicit interaction of cells, the proposed gate is further optimized and then used to design an ultra-efficient 1-bit full adder in QCA. The universal nature has been verified by designing all the logic gates from the proposed SSG-QCA gate whereas the multifunctional nature is verified by implementing all the 13 standard Boolean functions. The proposed 3 × 3 gate and adder designs are then extensively compared with the existing literature and it is observed that the proposed designs are ultra-efficient in terms of both area and cost in QCA technology. In addition to this energy dissipation analysis for different scenarios is also done on all the designs and it is observed that the proposed designs dissipate minimum energy thereby making them suitable for ultra-low power designs.

     

A Power-Efficient Single Layer Full Adder Design in Field-Coupled QCA Nanocomputing

As an emerging technology device, Quantum-dot cellular automata (QCA) may be a suitable substitute for traditional semiconductor transistor technology. Arithmetic logic unit in field-coupled QCA has been also studied extensively in recent year. In this paper, the new low-power Exclusive-OR gate is presented, which is mainly based on QCA cellular leveled format. This Exclusive-OR gate can be used to design various useful QCA circuits. By using this gate, we design and implement a novel full adder circuit with low dissipation. The circuit is designed using only 45 normal cells in a single layer without crossover. Compared with previous designs, both decimal adders achieve better performance in terms of latency and overall cost. The operation of the proposed circuit has been verified by QCADesigner version 2.0.3 and energy dissipation investigated by QCAPro tool. We also compared with previous designs in terms of power dissipation, cell-counts, area, latency and cost. The proposed full adder has the smallest area with less number of cells. And the total energy dissipation of our proposed full adder are only 0.05112 eV, 0.07454 eV and 0.10181 eV when tunneling energy levels are 0.5 Ek, 1 Ek and 1.5 Ek, respectively. The proposed single full adder also has the lowest total energy dissipation with a reduction of 20.94, 11.25 and 4.82% in 0.5 E_k, 1 E_k and 1.5 E_k tunneling energy levels, respectively when compared with the previous most power-efficient design.

     

Shannon Logic Based Novel QCA Full Adder Design with Energy Dissipation Analysis

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to replace VLSI-CMOS digital circuits. Due to its attractive features such as low power consumption, ultra-high speed switching, high device density, several digital arithmetic circuits have been proposed. Adder circuit is the most prominent component used for arithmetic operations. All other arithmetic operation can be successively performed using adder circuits. This paper presents Shannon logic based QCA efficient full adder circuit for arithmetic operations. Shannon logic expression with control variables helps the designer to reduce hardware cost; using with minimum foot prints of the chip size. The mathematical models of the proposed adder are verified with the theoretical values. In addition, the energy dissipation losses of the proposed adder are carried out. The energy dissipation calculation is evaluated under the three separate tunneling energy levels, at temperature T = 2K.The proposed adder dissipates less power. QCAPro tool is used for estimating the energy dissipation. In this paper we proposed novel Shannon based adder for arithmetic calculations. This adder has been verified in different aspects like using Boolean algebra besides it power analysis has been calculated. In addition 1-bit full adder has been enhanced to propose 2-bit and 4-bit adder circuits.     

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing

The challenges which the CMOS technology is facing toward the end of the technology roadmap calls for an investigation of various logical and technological solutions to CMOS at the nano scale. Two such paradigms which are considered in this paper are the reversible logic and the quantum-dot cellular automata (QCA) nanotechnology. Firstly, a new 3 × 3 reversible and universal gate, RG-QCA, is proposed and implemented in QCA technology using conventional 3-input majority voter based logic. Further the gate is optimized by using explicit interaction of cells and this optimized gate is then used to design an optimized modular full adder in QCA. Another configuration of RG-QCA gate, CRG-QCA, is then proposed which is a 4 × 4 gate and includes the fault tolerant characteristics and parity preserving nature. The proposed CRG-QCA gate is then tested to design a fault tolerant full adder circuit. Extensive comparisons of gate and adder circuits are drawn with the existing literature and it is envisaged that our proposed designs perform better and are cost efficient in QCA technology.     

Optimization Approaches for Designing a Novel 4-Bit Reversible Comparator

Reversible logic is a new rapidly developed research field in recent years, which has been receiving much attention for calculating with minimizing the energy consumption. This paper constructs a 4×4 new reversible gate called ZRQ gate to build quantum adder and subtraction. Meanwhile, a novel 1-bit reversible comparator by using the proposed ZRQC module on the basis of ZRQ gate is proposed as the minimum number of reversible gates and quantum costs. In addition, this paper presents a novel 4-bit reversible comparator based on the 1-bit reversible comparator. One of the vital important for optimizing reversible logic is to design reversible logic circuits with the minimum number of parameters. The proposed reversible comparators in this paper can obtain superiority in terms of the number of reversible gates, input constants, garbage outputs, unit delays and quantum costs compared with the existed circuits. Finally, MATLAB simulation software is used to test and verify the correctness of the proposed 4-bit reversible comparator.     

Robust Coplanar Full Adder Based on Novel Inverter in Quantum Cellular Automata

Quantum dot cellular automata (QCA) is one of the nano-scale computing paradigms which promises high speed and ultra-low power consumption. Since the one-bit full adder is a fundamental building block of arithmetic circuits, designing an efficient QCA full adder cell is very imperative in this new technology. In this paper, we propose a QCA full adder using a new inverter gate which leads to reduced complexity and area occupation. The proposed layout is simulated by the QCA designer engines. We also provide a performance comparison of our proposed QCA full adder with the previous relevant designs. Furthermore, a detailed analysis of energy dissipation is performed which demonstrates the superiority of the proposed design in terms of the energy efficiency.

     

An Improved Design of n-Bit Universal Reversible Gate Library

Reversible logic has been considered as an important solution to the power dissipation problem in the existing electronic devices. Many universal reversible libraries that include more than one type of gates have been proposed in the literature. This paper proposes a novel reversible n-bit gate that is proved to be universal for synthesizing reversible circuits. Reducing the reversible circuit synthesis problem to permutation group allows Schreier-Sims Algorithm for the strong generating set-finding problem to be used in the synthesize of reversible circuits using the proposed gate. A novel optimization rules will be proposed to further optimize the synthesized circuits in terms of the number of gates, the quantum cost and the utilization of library to achieve better results than that shown in the literature.

     

Effective Designs of Reversible Vedic Multiplier

Power dissipation problem is one of the most challenging problems in designing conventional electronic circuits. One of the best approaches to overcome this problem is to design reversible circuits. Nowadays, reversible logic is considered as a new field of study that has various applications such as optical information processing, design of low power CMOS circuits, quantum computing, DNA computations, bioinformatics and nanotechnology. Due to the vulnerability of the digital circuits to different environmental factors, the design of circuits with error-detection capability is considered a necessity. Parity preserving technique is known as one of the most famous methods for providing error-detection ability. Multiplication operation is considered as one of the most important operations in computing systems, which can play a significant role in increasing the efficiency of such systems. In this paper, two efficient 4-bit reversible multipliers are proposed using the Vedic technique. The Vedic technique is able to increase the speed of multiplication operation by producing partial products and their sums simultaneously in a parallel manner. The first architecture lacks the parity preserving potential, while the second architecture has the ability parity preserving. Since a 4-bit Vedic multiplier includes 2-bit Vedic multipliers and 4-bit ripple carry adders (RCA), so in the first design, TG, PG and FG gates have been used to design an efficient 2-bit reversible Vedic multiplier, as well as PG gate and HNG block have been applied as a half-adder (HA) and full-adder (FA) in the 4-bit RCAs. Also, in the second design, 2-bit parity preserving reversible Vedic multiplier has been designed using FRG, DFG, ZCG and PPTG gates as well as ZCG and ZPLG blocks have been utilized as HA and FA in the 4-bit RCAs. Proposed designs are compared in terms of evaluation criteria of circuits such as gate count (GC), number of constant inputs (CI), number of garbage outputs (GO), quantum cost (QC), and hardware complexity. The results of the comparisons indicate that the proposed designs are more efficient compared to available counterparts.

     

Quantum Fourier Transform-Based Arithmetic Logic Unit on a Quantum Processor

This study proposes and construct a primitive quantum arithmetic logic unit (qALU) based on the quantum Fourier transform (QFT). The qALU is capable of performing arithmetic ADD (addition) and logic NAND gate operations. It designs a scalable quantum circuit and presents the circuits for driving ADD and NAND operations on two-input and four-input quantum channels, respectively. By comparing the required number of quantum gates for serial and parallel architectures in executing arithmetic addition, it evaluates the performance. It also execute the proposed quantum Fourier transform-based qALU design on real quantum processor hardware provided by IBM. The results demonstrate that the proposed circuit can perform arithmetic and logic operations with a high success rate. Furthermore, it discusses in detail the potential implementations of the qALU circuit in the field of computer science, highlighting the possibility of constructing a soft-core processor on a quantum processing unit.     

Realization of Quantum Circuits in Fock Space

In this letter, by using the method we offered in our paper [L. Ma and Y.D. Zhang, Commun. Theor. Phys. (Beijing, China) 36 (2001) 119], some extended quantum logic gates, such as quantum counter, quantum adder, are studied and their expressions are given. It may be useful for us to study the more complicated quantum logic circuits deeply.     

Polarization-encoded all-optical quaternary multiplexer and demultiplexer - A proposal

Multi-valued logic is positioned as a coming generation technology that can execute arithmetic functions faster and with less interconnect than binary logic. Furthermore, nonbinary data storage would require less physical space than binary data. The application of multi-valued digital signals can provide considerable relief of capacity constraints. In electronics many proposals have already been reported. But, here for the first time we propose an all-optical circuit for designing quaternary (four-valued) multiplexer and demultiplexer with the help of some polarization-encoded basic quaternary logic gates (quaternary min and quaternary delta literal). Nonlinear interferometer-based optical switch can take an important role here. The principles and possibilities of design of all-optical quaternary multi-valued multiplexer and demultiplexer circuits are proposed and described.     

Adder on ternary base elements for a quantum computer

A circuit consisting of elementary quantum logic operators has been proposed for an adder in the ternary number system. A sequence of RF magnetic field pulses has been found for its implementation by the nuclear magnetic resonance method on a chain of quadrupole nuclei with spin I = 1. The numerical simulation of the adder operation has been performed.     

Quantum Circuit Synthesis using a New Quantum Logic Gate Library of NCV Quantum Gates

Since Controlled-Square-Root-of-NOT (CV, CV^?) gates are not permutative quantum gates, many existing methods cannot effectively synthesize optimal 3-qubit circuits directly using the NOT, CNOT, Controlled-Square-Root-of-NOT quantum gate library (NCV), and the key of effective methods is the mapping of NCV gates to four-valued quantum gates. Firstly, we use NCV gates to create the new quantum logic gate library, which can be directly used to get the solutions with smaller quantum costs efficiently. Further, we present a novel generic method which quickly and directly constructs this new optimal quantum logic gate library using CNOT and Controlled-Square-Root-of-NOT gates. Finally, we present several encouraging experiments using these new permutative gates, and give a careful analysis of the method, which introduces a new idea to quantum circuit synthesis.     

Photonic crystal-based all-optical arithmetic circuits without SOA-based switches

Various proposed optical computing devices involve nonlinear optical operation and use semiconductor optical amplifier (SOA)-based switches as fundamental elements for logic operations. Due to the nonlinear operation, these devices suffer from high power that causes problems in very large-scale optical integration. In this paper, a method is proposed to implement arithmetic operations using a photonic crystal (PhC) cell and eliminate the SOA-based switches altogether. The proposed method is employed on designing an all-optical full adder/subtractor circuit that requires only beam combiners and photonic crystal NOT gates.     

飞秒激光直写光量子逻辑门

量子比特在同一时刻可处于所有可能状态上的叠加特性使得量子计算机具有天然的并行计算能力,在处理某些特定问题时具有超越经典计算机的明显优势.飞秒激光直写技术因其具有单步骤高效加工真三维光波导回路的能力,在制备通用型集成光量子计算机的基本单元—量子逻辑门中发挥着越来越重要的作用.本文综述了飞秒激光直写由定向耦合器构成的光量子比特逻辑门的进展.主要包括定向耦合器的功能、构成、直写和性能表征,集成波片、哈达玛门和泡利交换门等单量子比特逻辑门、受控非门和受控相位门等两量子比特逻辑门的直写加工,并对飞秒激光加工三量子比特逻辑门进行了展望.     

Quantum Circuit Realization of Morphological Gradient for Quantum Grayscale Image

In this paper, based on the principle of classical morphology operations, the flat grayscale dilation and erosion operations are proposed for NEQR quantum image model. Furthermore, through combining these two morphology operations, we further realize the morphological gradient operation. As the basis of designing of grayscale morphology operations, a series of quantum circuit designs arepresented, which includes special add one operation UA₁(n) and special subtract one operation US₁(n) both for an n-length qubits sequence, quantum unitary operation U_C, parallel subtractor (PS) module, quantum comparator output the large QCOL and quantum comparator output the small QCOS modules. When designsthe concrete quantum circuit, a sequence of UA₁(n) and US₁(n) modules are used to obtain the quantum image sets based on the shape of specific structuring element. Then, the searching for maximaor minima in a certain space is involved, which can be solved by cascading a series of QCOL and QCOS modules in certain order. Finally, the PS module can be used to calculate the difference of the maxima and minima for producing the morphological gradient. The circuit’s complexity analysis illustrate that our scheme is very lower to the classical morphology operations.