Design of Cost-Efficient QCA Reversible Circuits via Clock-Zone-Based Crossover

Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for reversible logic. A novel Reversible Gate is developed using QCA technology. Performance of the proposed gate is verified using thirteen standard three variables Boolean functions, which demonstrate from 14.3% to 42.8% superiority in term of gate counts obtained with other reversible gates. Proposed reversible gate requires switching and leakage energy dissipation of 0.168 eV and 0.271 eV, respectively, at 1.5 E_k energy level. The proposed gate uses 146 cells occupying only 0.14 μ m² area and then used to design a full adder. We use a coplanar QCA crossover architecture in the designs that uses non-adjacent clock zones for the two crossing wires. These designs have been realized with QCADesigner.     

Robust Coplanar Full Adder Based on Novel Inverter in Quantum Cellular Automata

Quantum dot cellular automata (QCA) is one of the nano-scale computing paradigms which promises high speed and ultra-low power consumption. Since the one-bit full adder is a fundamental building block of arithmetic circuits, designing an efficient QCA full adder cell is very imperative in this new technology. In this paper, we propose a QCA full adder using a new inverter gate which leads to reduced complexity and area occupation. The proposed layout is simulated by the QCA designer engines. We also provide a performance comparison of our proposed QCA full adder with the previous relevant designs. Furthermore, a detailed analysis of energy dissipation is performed which demonstrates the superiority of the proposed design in terms of the energy efficiency.

     

Design of Ultra-Efficient Reversible Gate Based 1-bit Full Adder in QCA with Power Dissipation Analysis

The difficulties which the CMOS technology is facing at the nano scale has led to the investigation of quantum-dot cellular automata (QCA) nanotechnology and reversible logic as an alternative to conventional CMOS technology. In this paper, these two paradigms have been combined. Firstly, a new 3 × 3 reversible gate, SSG-QCA, which is universal and multifunctional in nature, is proposed and implemented in QCA using conventional 3-input majority voter based logic. By using the concept of explicit interaction of cells, the proposed gate is further optimized and then used to design an ultra-efficient 1-bit full adder in QCA. The universal nature has been verified by designing all the logic gates from the proposed SSG-QCA gate whereas the multifunctional nature is verified by implementing all the 13 standard Boolean functions. The proposed 3 × 3 gate and adder designs are then extensively compared with the existing literature and it is observed that the proposed designs are ultra-efficient in terms of both area and cost in QCA technology. In addition to this energy dissipation analysis for different scenarios is also done on all the designs and it is observed that the proposed designs dissipate minimum energy thereby making them suitable for ultra-low power designs.

     

Shannon Logic Based Novel QCA Full Adder Design with Energy Dissipation Analysis

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to replace VLSI-CMOS digital circuits. Due to its attractive features such as low power consumption, ultra-high speed switching, high device density, several digital arithmetic circuits have been proposed. Adder circuit is the most prominent component used for arithmetic operations. All other arithmetic operation can be successively performed using adder circuits. This paper presents Shannon logic based QCA efficient full adder circuit for arithmetic operations. Shannon logic expression with control variables helps the designer to reduce hardware cost; using with minimum foot prints of the chip size. The mathematical models of the proposed adder are verified with the theoretical values. In addition, the energy dissipation losses of the proposed adder are carried out. The energy dissipation calculation is evaluated under the three separate tunneling energy levels, at temperature T = 2K.The proposed adder dissipates less power. QCAPro tool is used for estimating the energy dissipation. In this paper we proposed novel Shannon based adder for arithmetic calculations. This adder has been verified in different aspects like using Boolean algebra besides it power analysis has been calculated. In addition 1-bit full adder has been enhanced to propose 2-bit and 4-bit adder circuits.     

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing

The challenges which the CMOS technology is facing toward the end of the technology roadmap calls for an investigation of various logical and technological solutions to CMOS at the nano scale. Two such paradigms which are considered in this paper are the reversible logic and the quantum-dot cellular automata (QCA) nanotechnology. Firstly, a new 3 × 3 reversible and universal gate, RG-QCA, is proposed and implemented in QCA technology using conventional 3-input majority voter based logic. Further the gate is optimized by using explicit interaction of cells and this optimized gate is then used to design an optimized modular full adder in QCA. Another configuration of RG-QCA gate, CRG-QCA, is then proposed which is a 4 × 4 gate and includes the fault tolerant characteristics and parity preserving nature. The proposed CRG-QCA gate is then tested to design a fault tolerant full adder circuit. Extensive comparisons of gate and adder circuits are drawn with the existing literature and it is envisaged that our proposed designs perform better and are cost efficient in QCA technology.     

Toward Efficient Design of Flip-flops in Quantum-Dot Cellular Automata with Power Dissipation Analysis

Quantum-dot cellular automata (QCA) is one of the emergent nano-technologies and a potential substitute for transistor based technologies. In this research, an efficient QCA based T, SR and JK flip-flops have been proposed. The proposed gates are implemented with multiplexer, three-input Majority gate and XOR gate. The circuit layouts are designed and verified using QCADesigner version 2.0.3. The simulation result reviles the excellence of the proposed design. The proposed T flip-flop archives 35% improvement in terms cell count. Similarly, the reported RS and JK flip-flop requires 43% and 50% less area respectively in comparison to the previous best single layer design. In addition, QCAPro tool has been used to estimate the power dissipation of all considered designs at different tunneling energy level.     

An Efficient Module for Full Adders in Quantum-dot Cellular Automata

Quantum-dot cellular automata (QCA), a new computing paradigm at nanoscale, may be a prospective alternative to conventional CMOS-based integrated circuits. Modular design methodology in QCA domain has not been widely investigated. In this paper, an efficient module with fault tolerance is proposed, which can be employed to fabricate three-input and five-input majority gates that are the fundamental primitives for designing circuits in QCA. With cells omission in the versatile module, various logic gates will be achieved, such as Nand-Nor-Inverter (NNI) gate and And-Or-Inverter (AOI) gate. Moreover, in order to seek out an efficient full adder, five various QCA full adders are designed and exhaustively compared in terms of area, complexity, latency, reliability and power dissipation and also compared with existing fault-tolerant full adders. Two simulation tools, QCADesigner and QCAPro, are utilized in the waveform simulations for verifying the correctness of proposed circuits and power consumption, respectively. The analysis results reveal that full adder V has significant improvements in contrast to its counterparts with above criteria. To test the practicability of full adder V, multi-bit adders will be designed in single-layer and compared with previous adders in terms of area, complexity and QCA cost, which proves the merits of our work.     

Design of Low-Complexity and High-Speed Coplanar Four-Bit Ripple Carry Adder in QCA Technology

Quantum-dot Cellular Automata (QCA) technology is a suitable technology to replace CMOS technology due to low-power consumption, high-speed and high-density devices. Full adder has an important role in the digital circuit design. This paper presents and evaluates a novel single-layer four-bit QCA Ripple Carry Adder (RCA) circuit. The developed four-bit QCA RCA circuit is based on novel QCA full adder circuit. The developed circuits are simulated using QCADesigner tool version 2.0.3. The simulation results show that the developed circuits have advantages in comparison with existing single-layer and multilayer circuits in terms of cell count, area occupation and circuit latency.     

Designing a New 4:2 Compressor Using an Efficient Multi-Layer Full-Adder Based on Nanoscale Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) is novel prominent nanotechnology. It promises a substitution to Complementary Metal–Oxide–Semiconductor (CMOS) technology with a higher scale integration, smaller size, faster speed, higher switching frequency, and lower power consumption. It also causes digital circuits to be schematized with incredible velocity and density. The full adder, compressor, and multiplier circuits are the basic units in the QCA technology. Compressors are an important class of arithmetic circuits, and researchers can use quantum compressors in the structure of complex systems. In this paper, first, a novel three-input multi-layer full-adder in QCA technology is designed, and based on it, a new multi-layer 4:2 compressor is presented. The proposed QCA-based full-adder and compressor uses an XOR gate. The proposed design offers good performance regarding the delay, area size, and cell number comparing to the existing ones. Also, in this gate, the output signal is not enclosed, and we can use it easily. The accuracy of the suggested circuits has been assessed with the utilization of QCADesigner 2.0.3. The results show that the proposed 4:2 compressor architecture utilizes 75 cell and 1.25 clock phases, which are efficient than other designs.

     

A New Coplanar Design of Multiplier Based on Nanoscale Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) nanotechnology is emerging as a replacement technique for maintaining increasing microprocessor performance and it yields small size, high speed, and low power consumption. On the other hand, a multiplier is a circuit that multiplies two binary values for performing sequential addition operations and accumulating the results. This type of circuit is the basic structural unit of many arithmetic logical units, digital signal processing, and communication system. The multiplier circuit contains some full adders that can perform add operations, so, it is very important that low-complexity full adders are used. Therefore, in this paper, a new 2 × 2 array multiplier circuit in QCA by employing an efficient structure of full adder is designed and implemented. This design is constructed using coplanar layouts and compared its performance with existing QCA multipliers. The operation and efficiency of the proposed structure have been confirmed using QCADesigner tool. The simulation results have demonstrated that the 2 × 2 multiplier leads to less cell count and area as the prime designing factors.

     

Fast Quantum-Dot Cellular Automata Adder/Subtractor Using Novel Fault Tolerant Exclusive-or Gate and Full Adder

Quantum-dot Cellular automata is a promising area to implement digital systems at nano scale level. Adders and subtractors are widely used in almost every digital information processing system. This work targets to design an efficient 8-bit adder/subtractor that can perform addition as well as subtraction by using a novel control signal distribution scheme. To perform controlled inversion of inputs a novel exclusive-or gate with fewer cells is proposed. During Quantum-dot Cellular automata circuit fabrication, missing cell defects have the potential to affect the performance of a circuit. The proposed designs have higher fault resistance to missing cell defects compared to the existing state-of-the-art designs. Results demonstrate that the proposed design has (N-2) less clock phases compared to the existing state-of-the-art designs. The proposed design can be extended to implement any N-bit adder/subtractor. All the designs are designed and verified using coherence vector simulation engine in QCADesigner.

     

Designing Nanoscale Counter Using Reversible Gate Based on Quantum-Dot Cellular Automata

Some new technologies such as Quantum-dot Cellular Automata (QCA) is suggested to solve the physical limits of the Complementary Metal-Oxide Semiconductor (CMOS) technology. The QCA as one of the novel technologies at nanoscale has potential applications in future computers. This technology has some advantages such as minimal size, high speed, low latency, and low power consumption. As a result, it is used for creating all varieties of memory. Counter circuits as one of the important circuits in the digital systems are composed of some latches, which are connected to each other in series and actually they count input pulses in the circuit. On the other hand, the reversible computations are very important because of their ability in reducing energy in nanometer circuits. Improving the energy efficiency, increasing the speed of nanometer circuits, increasing the portability of system, making smaller components of the circuit in a nuclear size and reducing the power consumption are considered as the usage of reversible logic. Therefore, this paper aims to design a two-bit reversible counter that is optimized on the basis of QCA using an improved reversible gate. The proposed reversible structure of 2-bit counter can be increased to 3-bit, 4-bit and more. The advantages of the proposed design have been shown using QCADesigner in terms of the delay in comparison with previous circuits.     

Key role of molecular kinetic energy in early stages of pentacene island growth

Organic molecular beam deposition is studied systematically at thermal and hyperthermal regimes aiming at investigating the role of molecular kinetic energy on the growth mechanism of pentacene submonolayers on SiO _x /Si. We show that the kinetic energy of the impinging molecule (E _k ) plays a crucial role in determining island structure and shape, distribution of island sizes, the crystalline quality of the first monolayer, and even the growth mode of subsequent layers. With increasing E _k , the island structure changes from fractal to nonfractal, the shape becomes more anisotropic and the island size more uniform, pointing to correlated island growth. Moreover, while 3D island growth is observed for thermal organic molecular beam deposition, supersonic molecular beam deposition gives rise to layer-by-layer growth, at least for the first two layers. When E _k ≥5.0 eV, the first monolayer is composed of large single crystalline domains which can extend over up to 10 μm, inferred from comparing atomic force micrographs of height and net transverse shear force. In these growth conditions both the high surface diffusivity and energy redistribution play a major role. We propose a mechanism where the energy dissipation occurring during the molecule–surface collision leads to the reorientation of whole islands during island coalescence, resulting in the elimination of grain boundaries.     

Charge storage characteristics of nonvolatile memories with chemically-synthesized and vacuum-deposited gold nanoparticles

Carrier injection and charge loss characteristics of nonvolatile memories with chemically-synthesized (CS) and vacuum-deposited (VD) gold nanoparticles (Au-NPs) have been investigated. Compared to CS counterparts, the memories with VD Au-NPs exhibit a higher dot density of 3.77 × 10¹¹ cm⁻², leading to a larger memory window. Further, the energy from valence-band edge to vacuum level (E_{VB_vac}) of tunneling oxide for the samples with CS and VD Au-NPs is found to be 9.04 and 9.85 eV respectively. The small E_{VB_vac} value of the memories with CS Au-NPs is resulted from the formation of a thin chemical oxide (SiO_x) on thermally-grown SiO₂ tunneling layer during the chemically synthesized process, contributing to a slow erasing behavior. Besides, the programming of the memories with VD Au-NPs is saturated at high gate bias, which has been well-explained by the electrons induced potential coupling between Au-NPs. Superior data retention property and high temperature dependence of charge loss are observed for the memories with CS Au-NPs, which can be ascribed to the thick tunneling oxide layer by the additional SiO_x film.     

Novel Efficient Circuit Design for Multilayer QCA RCA

The novel emerging technology, QCA technology, is a candidate for replacing CMOS technology. Full Adder (FA) circuits are also widely used circuits in arithmetic circuits design. In this paper, two new multilayer QCA architectures are presented: one-bit FA and 4-bit Ripple Carry Adder (RCA). The designed one-bit multilayer FA architecture is based on a new XOR gate architecture. The designed 4-bit multilayer QCA RCA is also developed based on the designed one-bit multilayer QCA FA. The functionality of the designed architectures are verified using QCADesigner tool. The results indicate that the designed architecture for 4-bit multilayer QCA RCA requires 5 clock phases, 125 QCA cells, and 0.17 μm² area. The comparison results confirm that the designed architectures provide improvements compared with other adder architectures in terms of cost, cell count, and area.

     

Design of Improved Arithmetic Logic Unit in Quantum-Dot Cellular Automata

The quantum-dot cellular automata (QCA) can be replaced to overcome the limitation of CMOS technology. An arithmetic logic unit (ALU) is a basic structure of any computer devices. In this paper, design of improved single-bit arithmetic logic unit in quantum dot cellular automata is presented. The proposed structure for ALU has AND, OR, XOR and ADD operations. A unique 2:1 multiplexer, an ultra-efficient two-input XOR and a low complexity full adder are used in the proposed structure. Also, an extended design of this structure is provided for two-bit ALU in this paper. The proposed structure of ALU is simulated by QCADesigner and simulation result is evaluated. Evaluation results show that the proposed design has best performance in terms of area, complexity and delay compared to the previous designs.     

QCA Gray Code Converter Circuits Using LTEx Methodology

The Quantum-dot Cellular Automata (QCA) is the prominent paradigm of nanotechnology considered to continue the computation at deep sub-micron regime. The QCA realizations of several multilevel circuit of arithmetic logic unit have been introduced in the recent years. However, as high fan-in Binary to Gray (B2G) and Gray to Binary (G2B) Converters exist in the processor based architecture, no attention has been paid towards the QCA instantiation of the Gray Code Converters which are anticipated to be used in 8-bit, 16-bit, 32-bit or even more bit addressable machines of Gray Code Addressing schemes. In this work the two-input Layered T module is presented to exploit the operation of an Exclusive-OR Gate (namely LTEx module) as an elemental block. The “defect-tolerant analysis” of the two-input LTEx module has been analyzed to establish the scalability and reproducibility of the LTEx module in the complex circuits. The novel formulations exploiting the operability of the LTEx module have been proposed to instantiate area-delay efficient B2G and G2B Converters which can be exclusively used in Gray Code Addressing schemes. Moreover this work formulates the QCA design metrics such as O-Cost, Effective area, Delay and Cost _α for the n-bit converter layouts.     

超薄栅氧化层n-MOSFET软击穿后的导电机制

研究了恒压应力下超薄栅氧化层n型金属-氧化物-半导体场效应晶体管（n-MOSFET）软击穿 后的导电机制.发现在一定的栅电压V_g范围内，软击穿后的栅电流I_g符合Fowl er-Nordheim隧穿公式，但室温下隧穿势垒_b的平均值仅为0936eV，远小于S i/Si O₂界面的势垒高度315eV.研究表明，软击穿后，处于Si/SiO₂界 面量子化能级上的 电子不隧穿到氧化层的导带，而是隧穿到氧化层内的缺陷带上._b与缺陷带能 级和电 子所处的量子能级相关；高温下，激发态电子对隧穿电流贡献的增大导致_b逐 渐降低. 关键词： 软击穿 栅电流 类Fowler-Nordheim隧穿 超薄栅氧化层     

Quaternary Quantum/Reversible Half-Adder,Full-Adder,Parallel Adder and Parallel Adder/Subtractor Circuits

Multiple valued quantum logic is a promising research area in quantum computing technology having several advantages over binary quantum logic. Adder circuits as well as subtractor circuits are the major components of various computational units in computers and other complex computational systems. In this paper, we propose a quaternary quantum reversible half-adder circuit using quaternary 1-qudit gates, 2-qudit Feynman and Muthukrishnan-Stroud gates. Then we propose a quaternary quantum reversible full adder and a quaternary quantum parallel adder circuit. In addition, we propose a quaternary quantum reversible parallel adder/subtractor circuit. The proposed designs are compared with existing designs and improvements in terms of hardware complexity, quantum cost, number of constant inputs and garbage outputs are reported.

     

Robust Multiplexer Design and Analysis Using Quantum Dot Cellular Automata

Quantum Dot Cellular Automata (QCA) is an alternate version of the existing conventional CMOS technology due to its low power intake, faster speed, and smaller size. A multiplexer is a very important logical block in VLSI designs. In this paper, a 2:1 multiplexer (MUX) architecture is proposed, analyzed and compared with related existing architectures. The kink energy of proposed circuit has been calculated and hazard analysis has been completed successfully. All designs in this paper are simulated, checked, and verified using the popular QCADesigner tool. The comparisons of the proposed design with respect to different parameters of the existing MUX(s) along with their corresponding graphical representations prove the robustness of the proposed multiplexer.