A 77-GHz MMIC power amplifier for automotive radar applications

A MMIC 77-GHz two-stage power amplifier (PA) is reported in this letter. This MMIC chip demonstrated a measured small signal gain of over 10 dB from 75 GHz to 80 GHz with 18.5-dBm output power at 1 dB compression. The maximum small signal gain is above 12 dB from 77 to 78 GHz. The saturated output power is better than 21.5 dBm and the maximum power added efficiency is 10% between 75 GHz and 78 GHz. This chip is fabricated using 0.1-/spl mu/m AlGaAs/InGaAs/GaAs PHEMT MMIC process on 4-mil GaAs substrate. The output power performance is the highest among the reported 4-mil MMIC GaAs HEMT PAs at this frequency and therefore it is suitable for the 77-GHz automotive radar systems and related transmitter applications in W-band.     

A true logarithmic amplifier for radar IF applications

There are certain radar receivers where the settling time of an AGC loop is unacceptable and an amplifier is required which will compress the dynamic range instantaneously. A common technique for accomplishing this is to use a logarithmic amplifier. This has other advantages in radar applications in that a logarithmic amplifier can assist in separating wanted signals from unwanted signals known as `clutter' caused by unwanted targets such as raindrops. In systems such as MTI radar systems, where it is required to detect moving targets, the phase information is important hence the logarithmic output must be at the IF frequency. In order to preserve the phase information the phase shift or delay through the log amplifier should not vary with input signal level. This type of amplifier is known as a true logarithmic amplifier. The device described in this paper is capable of producing a true logarithmic amplifier with phase matching of /spl plusmn/4/spl deg/ over an 80 dB input dynamic range at 70 MHz.     

Adaptively linearised MMIC power amplifier for W-CDMA applications

A high-linearity and high-efficiency MMIC power amplifier is proposed that adopts a new on-chip adaptive bias circuit, which simultaneously improves efficiency at the low output power level and linearity at the high output power level. The intelligent W-CDMA power amplifier using the adaptive bias circuit extends the maximum linear output power of 0.6 dB and exhibits an improvement of average power usage efficiency of 1.85 times.     

A novel power amplifier structure for RFID tag applications

A novel matching method between the power amplifier(PA) and antenna of an active or semi-active RFID tag is presented.A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240×70μm~2 in a 0.18μm CMOS process due to saving two on-chip integrated inductors.Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal,the PA shows a measured output power of 8 dBm at the 1 dB compression point.     

Silicon-germanium BiCMOS HBT technology for wireless power amplifier applications

This paper discusses and illustrates the key device design issues for SiGe BiCMOS HBTs suitable for wireless power amplifier (PA) applications. Experimental results addressing ruggedness, ac performance, and safe operating area for high-breakdown SiGe HBTs built in several generations of BiCMOS technology are presented. Implications of recent high-performance SiGe HBT scaling achievements for BiCMOS technologies targeting wireless PA applications are considered. Circuit results for GSM, PCS, GPRS, and EDGE front-end modules have been obtained. A one-chip solution is demonstrated, including control circuitry and switching functionality, that supports all GPRS, PCS, and EDGE modes featuring output power at 33.8 dBm and overall power added efficiency of 37% withstanding voltage standing wave ratio conditions of 15:1.     

一种应用于RFID标签的新型功率放大器设计

A novel matching method between the power amplifier (PA) and antenna of an active or semi-active RFID tag is presented. A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240 × 70 μm² in a 0.18 μm CMOS process due to saving two on-chip integrated inductors. Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal, the PA shows a measured output power of 8 dBm at the 1 dB compression point.     

Thin-film silicon-on-sapphire LDMOS structures for RF power amplifier applications

This work is addressed to the investigation of the electro-thermal performance of RF-LDMOS transistors integrated in TF-SOI, TF-SOS and thinned TF-SOS substrates by means of numerical simulations. Reported experimental trap density, carrier mobility and capture cross-section values have been used together with sapphire datasheet thermal properties, in order to provide accurate simulation results. It is found that subthreshold characteristics are the same for all the analysed substrates while blocking-state, on-state and power dissipation process depends on the substrate type.     

SiGe MMIC power amplifier with on-chip lineariser for X-band applications

An X-band linear power amplifier with an on-chip lineariser is developed using a 0.25 mum SiGe HBT BiCMOS process. The proposed on-chip lineariser improves the 1 dB compression to as much as 3.4 dB with no additional DC power consumption. Under a 3.3 V DC power supply, the single-stage cascode amplifier shows a measured small-signal gain of 12.2 dB and output PI dB of 20.8 dBm, with power added efficiency of 27.4% at the operating frequency range 8.5-10.5 GHz.     

High-efficiency dynamic supply CMOS audio power amplifier for low-power applications

This paper describes the analysis and design of a dynamic supply CMOS audio power amplifier for low-power applications. The dynamic supply technique is used to increase the efficiency of a class AB power amplifier. The polarization of its output stage is adaptive so that the maximum efficiency enhancement can be achieved without jeopardizing the linearity of the system. Two types of adaptive polarization are proposed and compared. A concept of power supplies switching is also proposed. Simulation results are presented showing that an efficiency of 53.6% at a total harmonic distortion (THD) of less than 0.1% can be achieved, whereas the maximal theoretical value for a class AB amplifier is approximately 33.3%.     

A high average-efficiency SiGe HBT power amplifier for WCDMA handset applications

The linearity of a silicon-germanium (SiGe) HBT power amplifier (PA) is analyzed with the help of a power-dependent coefficient Volterra technique. The effect of emitter inductance is included and the dominant sources of nonlinearity are identified. A dynamic current biasing technique is developed to improve the average power efficiency for wide-band code-division multiple-access (WCDMA) PAs. The average power efficiency is improved by more than a factor of two compared to a typical class-AB operation, while the power gain keeps roughly constant. The measured adjacent channel power ratio with 5and 10-MHz offsets at 23.9-dBm average channel output power are -33 and -58.8 dBc, respectively, and satisfies the Third-generation partnership project WCDMA specifications. The output power at the 1-dB compression point is 25.9 dBm     

Design of broadband class-F power amplifier for multiband LTE handsets applications

A broadband class-F power amplifier for multiband LTE handsets applications is developed across 2.3-2.7 GHz. The power amplifier maintains constant fundamental impedance at the output matching circuit which is operating for broadband. The nearly zero of second harmonic impedance and nearly infinity of third harmonic impedance are found for highly efficient class-F PA. The harmonic control circuits are immersed into the broadband output matching for fundamental frequency. For demonstration, the PA is implemented in InGaP/GaAs HBT process, and tested across the frequency range of 2.3-2.7 GHz using a long-term evolution signal. The presented PA delivers good performance of high efficiency and high linearity, which shows that the broadband class-F PA supports the multiband LTE handsets applications.     

Class E switching-mode power amplifier for high-frequency electric process heating applications

The letter is concerned with the application of a class E convertor to electric process heating. A simple efficient convertor is described which is suitable for high-frequency electric process heating loads.     

High-efficiency power amplifier using dynamic power-supply voltagefor CDMA applications

Efficiency and linearity of the microwave power amplifier are critical elements for mobile communication systems. This paper discusses improvements in system efficiency that are obtainable when a DC-DC converter is used to convert available battery voltage to an optimal supply voltage for the output RF amplifier. A boost DC-DC converter with an operating frequency of 10 MHz is demonstrated using GaAs heterojunction bipolar transistors. Advantages of 10 MHz switching frequency and associated loss mechanisms are described. For modulation formats with a time-varying envelope, such as CDMA, the probability of power usage is described. Gains in power efficiency and battery lifetime are calculated. An envelope detector circuit with a fast feedback loop regulator is discussed. Effects of varying supply voltage with respect to distortion are examined along with methods to increase system linearity     

A 900-MHz fully integrated SOI power amplifier for single-chipwireless transceiver applications

This paper presents a silicon-on-insulator (SOI) fully integrated RF power amplifier for single-chip wireless transceiver applications. The integrated power amplifier (IPA) operates at 900 MHz, and is designed and fabricated using a 1.5-μm SOI LDMOS/CMOS/BJT technology. This technology is suitable for the complete integration of the front-end circuits with the baseband circuits for low-cost low-power high-volume production of single-chip transceivers. The IPA is a two-stage Class E power amplifier. It is fabricated along with the on-chip input and output matching networks. Thus, no external components are needed. At 900 MHz and with a 5-V supply, the power amplifier delivers 23-dBm output power to a 50-Ω load with 16-dB gain and 49% power-added efficiency     

HBT power amplifier with dynamic base biasing for 3G handset applications

In this paper, a performance optimization of a digital signal processing driven and dynamically biased 3G handset's power amplifier technique is proposed, simulated and implemented. This technique uses a new dynamically base biasing heterojunction bipolar transistor which reduces the dc power consumption at low level drive and at the same time compensates the nonlinear distortion at high power drive of the PA in the transmitter of a universal mobile telecommunications system (UMTS) system with a high integrability. With the UMTS system, at low level drive, the dc power reduction is about 60% and at high emission power, the nonlinearity of the PA is corrected to respect the adjacent channel power ratio (ACPR) and error vector magnitude constraints imposed by the UMTS. With our system, the ACPR and efficiency of the power amplifier are improved, respectively, by 5 dB and 8%.     

Optimum design of a predistortion RF power amplifier for multicarrier WCDMA applications

This paper provides a design guide for optimum design of an RF power amplifier with a predistortion linearizer. For a two-tone signal, three performance degradation factors, higher order terms, amplitude, and phase mismatches are analyzed quantitatively. The results are implemented to the design of optimized predistortion power amplifier for a WCDMA signal application. For the experiments, a 2.4-GHz class-AB power amplifier is fabricated using an LDMOSFET with a 30-W peak envelope power. A simple third-order predistorter is used to measure the relative phases of the harmonics, as well as to linearize the amplifier. The performance of the optimized predistortion power amplifier is excellent for an IS-95 code-division-multiple-access signal. Finally, a method for reducing the memory effects of the amplifier is devised to get a good cancellation performance for a wide-band signal, and the performance degradation caused by the memory effects is analyzed. For a forward-link four-carrier WCDMA signal, the predistortion power amplifier delivers an adjacent channel leakage ratio of -46 dBc at a 4-W average output power with a cancellation of 13.4 dB.     

汽车防撞雷达系统功率放大器仿真设计

设计了用于汽车防撞雷达的功率放大器,为了消除在K波段的寄生效应的影响,设计了直流偏置、输入输出匹配网络、耦合隔直和电源滤波的微带网络。通过ADS仿真,得到了噪声系数为2.33,最大输出功率为18.5 dBm,增益为8.5 dB的功率放大器。文中设计的功率放大器适用于FMCW雷达系统。     

Design of an integrated low power high CMRR instrumentation amplifier for biomedical applications

The objective of this paper is to discuss the advantages and drawbacks of using Trapezoidal Association of Transistors (TAT) in the implementation of a low-power high-CMRR CMOS instrumentation amplifier (IA) aimed for biomedical applications. IAs are well suited for biomedical applications due to its high CMRR. For the sake of comparison, two versions of the circuit were designed, prototyped and characterized. The performance of a version with its current mirrors implemented with TAT, where supposedly higher CMRR could be achievable, is compared to another with single-transistor implementation of current mirrors in order to analyze the CMRR performance. The IA circuit was designed in AMIS 1.5 μm technology and manufactured through the MOSIS Service. In addition to the better performance attained by the classic implementation of the amplifier, with CMRR higher than 120 dB, this version of the IA consumed less than one third of the area from the TAT version. Comparison of both versions from same topology indicates no advantages of using TATs in the current mirrors of this type of IA.