版图图形特征对铜电镀工艺的影响

铜电镀工艺后表面的不平整度通常取决于版图关键特征,包括线宽,线间距和金属密度。本文设计了一款测试芯片并在一家半导体厂加工制造。版图特征效应被真正的测试数据所检查和验证。通过分析金属蝶形、介质腐蚀、金属厚度和SEM照片,得出一些结论。线宽是决定表面形貌及产生铜金属蝶形和介质层腐蚀的最关键因素。经过铜电镀工艺发现,铜线越细铜生长的越厚,铜线越宽铜金属蝶形越大,发现了3种典型表面形貌。而且,通过测试数据,量化版图特征的影响并用曲率增强加速剂覆盖率的理论解释,这可以用于开发铜电镀工艺模型和开展可制造性设计研究。     

Effects of pattern characteristics on the copper electroplating process

The non-planarity of a surface post electroplating process is usually dependent on variations of key layout characteristics including line width,line spacing and metal density.A test chip is designed and manufactured in a semiconductor foundry to test the layout dependency of the electroplating process.By checking test data such as field height,array height,step height and SEM photos,some conclusions are made.Line width is a critical factor of topographical shapes such as the step height and height difference.After the electroplating process,the fine line has a thicker copper thickness,while the wide line has the greatest step height.Three typical topographies, conformal-fill,supper-fill and over-fill,are observed.Moreover,quantified effects are found using the test data and explained by theory,which can be used to develop electroplating process modeling and design for manufacturability (DFM) research.     

通孔电镀铜填孔浅析

电子产品朝更轻、更薄、更快方向发展的趋势,使印制电路板在高密度互连技术上面面临挑战。微堆叠孔技术是一种用来产生高密度互连的方法。通孔的填充介质目前主要有三种,分别为导电膏、树脂、纯铜。比较此三种填充方式,纯铜填孔技术工艺流程短,可靠性高。该文介绍了通孔填孔的反应机理,并论述了通孔填孔电镀技术的优势。     

一种基于版图图形相关铜淀积率波动的电镀模型

随着集成电路尺寸缩小到深亚微米,工艺的系统波动变成了影响制造良率和芯片性能提升的障碍。为了进行可制造性设计分析,许多基于模型的方法被不断发展。对于后续的化学机械抛光工艺仿真和基于模型的冗余金属填充,铜电镀工艺仿真则是为其做了一项很重要的准备。本文提出了一种基于电镀工艺物理机制的版图图形特征相关的电镀模型,该模型考虑了工艺过程中铜电镀速率受不同版图图形特征影响所产生的变化,因此较早期模型在精度方面有一定改善,且模拟结果与实际硅数据对比也证实了这一点。     

Effects of pattern characteristics on copper CMP

Copper chemical mechanical polishing(CMP)is influenced by geometric characteristics such as line width and pattern density,as well as by the more obvious parameters such as slurry chemistry,pad type,polishing pressure and rotational speed.Variadons in the copper thickness across each die and across the wafer Can impact the circuit performance and reduce the yield.In this paper,we propose a modeling method to simulate the polishing behavior as a function of layout pattern factors.Under the same process conditions,the pattern density,the line width and the line spacing have a strong influence on copper dishing,dielectric erosion and topography.The test results showed:the wider the copper line or the spacing,the higher the copper dishing;the higher the density,the higher the dielectric erosion;the dishing and erosion increase slowly as a function of increasing density and go into saturation when the density is more than 0.7.     

版图图形特征对铜化学研磨的影响

Copper chemical mechanical polishing （CMP） is influenced by geometric characteristics such as line width and pattern density, as well as by the more obvious parameters such as slurry chemistry, pad type, polishing pressure and rotational speed. Variations in the copper thickness across each die and across the wafer can impact the circuit performance and reduce the yield. In this paper, we propose a modeling method to simulate the polishing behavior as a function of layout pattern factors. Under the same process conditions, the pattern density, the line width and the line spacing have a strong influence on copper dishing, dielectric erosion and topography. The test results showed： the wider the copper line or the spacing, the higher the copper dishing; the higher the density, the higher the dielectric erosion; the dishing and erosion increase slowly as a function of increasing density and go into saturation when the density is more than 0.7.     

An electroplating topography model based on layout-dependent variation of copper deposition rate

A layout-pattern-dependent electroplating model is developed based on the physical mechanism of the electroplating process.Our proposed electroplating model has an advantage over former ones due to a consideration of the variation of copper deposition rate with different layout parameters during the process.The simulation results compared with silicon data demonstrate the improvement in accuracy.     

Fabrication of high aspect ratio copper nanowires using supercritical CO2 fluids electroplating technique in AAO template

This study utilizes the supercritical and post-supercritical electroplating technique, to fabricate copper nano-wires inside ultra-high aspect ratio Anodic Aluminum Oxide templates (AAO templates). Comparisons of the electroplating capabilities and results were made between these methods and the more common traditional electroplating techniques. Under identical experimental conditions and on ultra-high aspect ratio AAO template with thickness of 60 µm (aspect ratio of 1:490), it is evident from the results that the supercritical electroplating process has the fastest electroplating velocity of the three processes (~1.33 µm/min), followed by post-supercritical electroplating (~1 µm/min) and traditional electroplating is the slowest (~0.67 µm/min). This study also discusses the electroplating quality of the copper nano-wires. Samples were sliced along the cross-section, and Field Emission Scanning Electron Microscopy (FESEM) was utilized to observe the copper nano-wires. X-Ray Diffraction (XRD) was used to observe that the crystal structures is polycrystalline, and with the use of equations it is determined that grain size will not be severely affected by changes in current density and supercritical pressure in themselves, but instead the different processes do produce an evident change. The grain size achieved with supercritical electroplating is the smallest, followed by the post-supercritical electroplating, and the largest was given by the traditional electroplating process. Through these results it can be proved that supercritical electroplating process indeed provides grain refinement capabilities. The supercritical fluid-enabled electroplating process utilized for these experiments does not need addition of any surfactants to aid filling of the structures, but only relies on the intrinsic properties of supercritical fluids to achieve complete filling of nano-holes, and because there are no surfactants, we can achieve higher degree of purity in the copper nano-wires.     

The influence of ultrasonic agitation on copper electroplating of blind-vias for SOI three-dimensional integration

Three-dimensional (3D) integration, which employs through-silicon-vias (TSVs) to electrically interconnect multiple-stacked chips, is a promising technology for significant reduction in interconnect delay and for hetero-integration of different technologies. To fabricate void-free TSVs, this paper presents a copper electroplating technique with the assistance of ultrasonic agitation to fill blind-vias, and discusses the influence of ultrasonic agitation on copper electroplating. Blind-vias with an aspect ratio of 3:1 are used for copper electroplating with both direct current (DC) and pulse-reverse current modes, combined with either ultrasonic agitation or mechanical agitation. Experimental results show that blind-vias with small aspect ratio can be completely filled using pulse-reverse current, regardless of the agitation methods. For DC, ultrasonic agitation is superior to mechanical agitation for copper electroplating in filling void-free vias. These results indicate that agitation, though is a secondary control factor to pulse-reverse current, can enhance mass transfer in blind-vias during copper electroplating and can improve the filling capability of copper electroplating.     

Bottom-up copper electroplating using transfer wafers for fabrication of high aspect-ratio through-silicon-vias

Three-dimensional (3D) integration is emerging as an attractive technology to continue Moore’s law through the integration of multi-stacked chips interconnected with through-silicon-vias (TSVs). To address the challenge in filling high aspect-ratio TSVs with copper, this paper reports an improved bottom-up copper electroplating (BCE) technique by introducing a glass transfer wafer, which is temporarily bonded with the device wafer to provide a copper seed layer. As the copper seed layer on the transfer wafer covers the through-holes, copper is electroplated from the bottom seed layer to the top opening of the through-holes without forming any voids or seams. This avoids the time consuming sealing process in conventional BCE, which normally takes 3-5 h. Thanks to the mechanical support of the transfer wafer, the device wafer can be thinned to several tens of micrometers. Using this technique, TSVs with diameter of 5 μm and aspect-ratio of 13:1 have been achieved. Based on the improved BCE technique, a through-via type 3D integration strategy is developed.     

电镀废液回收铜粉的化学镀银工艺及其电磁屏蔽性能

采用高频超声脉冲电解法从电镀铜废液中回收制备枝晶状的铜粉,并在铜粉表面进行化学镀银以制备电磁屏蔽用银包铜粉,采用SEM、EDS、XRD、TEM等对其进行形貌和组分分析,研究了银包铜粉复合涂层的导电性能和电磁屏蔽性能。结果表明,经过表面化学镀银可以有效地避免铜粉的氧化;涂层的电磁屏蔽性能与银包铜粉的添加量紧密相关,当涂层中银包铜粉质量分数为60%时,其电磁屏蔽效率高达52 dB。     

Effects of a magnetic field on the copper metallization using the electroplating process

We investigated the effects of a magnetic field on the electroplated copper films for the ULSI processes. The magnetic field was induced vertical to the electrodes and varied ranging from 0 to 600 G. The electroplating process was performed with on-off square pulse current source. The variation of the magnetic field vertical to the electrodes affected the deposition rate of the electroplated copper film, step coverage and gap filling in trench. As the intensity of the magnetic field increased, the deposition rate of the copper film increased, and also the resistance of electromigration increased. However, the magnetic field did not affect resistivity and surface morphology of the electroplated Cu film. At higher intensity of the magnetic field, good step coverage was obtained.     

铜化学机械抛光中的平坦性问题研究

铜的化学机械抛光(Cu-CMP)技术是ULSI多层金属布线结构制备中不可缺少的平坦化工艺.Cu-CMP后硅片表面的蝶形、侵蚀等平坦性缺陷将降低铜线的最终厚度和增大电阻率,从而降低器件性能和可靠性.而且可能进一步影响硅片的面内非均匀性(WIWUN),在多层布线中导致图案转移的不准确.本文介绍了对Cu-CMP平坦性的仿真、模拟和实验研究,并着重分析了碟形、侵蚀和WlWUN与抛光液、线宽和图案密度、抛光速度和载荷等相关参数的关系.     

硅片上电镀铅锡合金工艺

介绍了硅片上电镀铅锡合金工艺,并对镀液中各成分的作用及影响镀层质量的因素进行了探讨.     

Effects of self-aligned electroplating Cu pillar/Sn-xAg bump on dense Al lines for chip-to-package connection

Self-aligned electroplating is applied to form the Cu pillar/Sn-Ag bump for semiconductor device packaging, while passivation SiN cracks are usually observed at the bump edge on the bump of the array (BOA). In this paper, the simulation method was used to investigate the mechanism of SiN cracks and then, the bump process was optimized to improve the mechanical properties of the Cu pillar/Sn-Ag bump. It was found that higher reflow rounds could improve the shear strength due to the large degree of contact between the rugged scallop-like shape of the Cu₆Sn₅ and the Sn-Ag solder. The fracture plane cleaved between the Sn-Ag and Cu₆Sn₅ interface is consistent with the simulation results. The hardness of the Sn‒Ag solder is proportional to the reflow rounds, and the amount of Ag₃Sn phase precipitation within the Sn-Ag solder contributes to the hardness value. In contrast, the disadvantage is that thermal residual stress could deteriorate the SiN crack, especially for a BOA structure The study concludes that an optimal bump process, including Sn-2%Ag solders at 260 °C for 30 s, could obtain a high shear strength and appropriate solder hardness without passivated SiN cracking.     

龙门式电镀线生产75μm/75μm线镀铜均匀性探究

主要阐述我司通过对佳辉龙门式电镀线进行电镀均匀性的改善和研究,达到可以生产75μm/75μm线的工艺制作能力,以及使用龙门式电镀线制作75μm/75μm线镀铜均匀性控制要点、工艺能力维护等,为我司生产精细线路的产品提供一定的参考和制作依据。     

印制线路板微孔镀铜能力的研究

自20世纪40年代出现印电线路板,经过几十年的研究和生产实践,印制电路产业取得了巨大的发展。近年来,电子产品日趋"轻、薄、短、小",推动着印制线路板设计向着高密度、多功能、高速化的方向发展,缩小孔的设计尺寸成为达到高密度互联的有效手段,但同时也给生产制造带来了一定的难题,"高厚径比"成为湿法工艺面对的最大困难之一,如何在现有技术能力基础上,提升微孔孔化能力,成为湿法工艺研究的主要课题。     

The effects of electroplating parameters on the composition and morphology of Sn-Ag solder

The Sn-Ag solder was electrodeposited from a bath that basically is composed of tin sulfate (SnSO₄), silver nitrate (AgNO₃), and thiourea (CH₄N₂S), acting as a complexing agent to silver. The composition and morphology of electrodeposited Sn-Ag solder were studied in terms of silver concentration in bath current density, duty cycle, and additives. It was possible to control silver content in the electrodeposit by means of varying silver concentration in bath and current density. The microstructure and surface morphology of the electrodeposit become finer and smoother with increasing current density. The pulse-current (PC) plating method was applied to compare to the conventional direct-current (DC) plating. Varying duty cycle in PC plating did not change the microstructure in general, but some improvement in surface roughness was observed compared to DC plating. However, the silver composition in the electrodeposit increased with decreasing the duty cycle at a constant current density. An addition of a surface-active agent helped to reduce the surface roughness and the variation of silver content in the electrodeposit. In an optimum condition, eutectic Sn-Ag solder bumps with a fine pitch of 30 μm and height of 15 μm were successfully electroplated. The composition of Sn-Ag bumps was analyzed by energy dispersive x-ray spectrometry (EDS) and wavelength dispersive x-ray spectrometry (WDS) methods, and the surface morphology was characterized by scanning electron microscopy (SEM) and a three-dimensional surface analyzer.     

Development of different copper seed layers with respect to the copper electroplating process

Two types of copper seed layers deposited by MOCVD and long throw sputtering (LTS) onto a tantalum barrier layer were used for electroplating (EP) of copper in the forward pulsed mode. MOCVD and PVD copper seed layers were compared with respect to step coverage, electrical resistivity, texture and adhesion behaviour. The different properties induce different electroplating fill attributes, including grain size and adhesion behaviour. MOCVD Cu seed layers show high step coverage, but do not adhere to the Ta barrier after the Cu EP. LTS Cu reveal strong (111) texture and excellent adhesion before and after Cu EP. Therefore, a CMP process could only be performed on patterned wafers with PVD/EP copper to obtain electrical data. The fabricated Cu lines show a high yield with respect to opens and shorts and standard deviations of the line resistance across the wafer.     

Effect of copper seed aging on electroplating-induced defects in copper interconnects

Voids in copper thin films, observed after electroplating, have been linked to seed aging that occurs when a wafer is exposed, over time, to clean-room ambient. Oxidation of the copper seed surface prevents wetting during subsequent copper electroplating, leading to voids. Several surface treatments were employed to counteract the seed aging effect, including reduction of the copper oxide film by hydrogen, reverse plating of the copper surface, and rinsing the wafer surface with electrolyte. Each treatment was applied to wafers increasingly aged from 2 to 14 days, just prior to electroplating. Results showed a significant decrease in postelectroplating defects with all three treatments. The reduction of copper oxide by hydrogen exhibited the most marked results. An increase in surface wetting is shown by a decrease in contact angle measurements and an increase in film reflectivity for treated versus untreated copper wafers. This study shows that, although the copper surface exhibits strong aging effects over a short period of time, using proper surface treatments can eliminate such effects and voids.