Simple Analog Complementary Metal Oxide Semiconductor Circuit for Generating Motion Signal

We proposed in this study a novel analog complementary metal oxide semiconductor (CMOS) circuit for generating a motion signal when an object moves, which is a simple structure. The proposed unit circuit was constructed using a previously proposed edge detection circuit and a novel proposed circuit for generating a motion signal which accepts an edge signal. The part for generating the motion signal was constructed using six metal oxide semiconductor (MOS) transistors and one capacitor. Results obtained by the simulation program with integrated circuit emphasis (SPICE) and the measured results of a test circuit constructed with discrete MOS transistors and the test circuit fabricated with a 1.2 μm CMOS process showed that the proposed unit circuit can output pulsed current (motion signal) when an object moves on the circuit. It was clarified from the SPICE results that the two-dimensional network constructed with proposed unit circuits can output motion signals. The size of the novel unit circuit is expected to be about 110 × 110μm² obtained by the 1.2 μm CMOS process. It is possible to arrange 90 × 90 unit circuits on a chip which has an area of 1 × 1cm². The aperture ratio is expected to be about 21%, which is twice as large as that of the previously proposed circuit. An integrated circuit for image processing in real time can thus be realized by applying the two-dimensional network constructed with the proposed circuits.     

Analog Integrated Circuit for Motion Detection against Moving Background Based on the Insect Visual System

A network for displaying the velocity signal of a target edge which has larger velocity than the background was proposed and designed based on an insect visual system. In the insect visual system, the velocity signals generated by the background are inhibited by the signals generated by averaging the velocity signals from each cell and can only display the velocity signals of the target. The proposed network was constructed with simple analog circuits. The measured results of the test chip fabricated with the 1.2$mUm complementary metal-oxide-semiconductor (CMOS) process showed that the edge detection circuit inserted to the first stage of the proposed network can detect the edge position. It was apparent from the measured results of the test circuit constructed with discrete metal-oxide-semiconductor (MOS) transistors that the proposed unit circuit constructing the network can generate the velocity signals by inputting the edge signals. The results with the simulation program with integrated circuit emphasis (SPICE) showed that the proposed network can only display the velocity signals of the target edges but not those of the background. Thus, it was clarified that the various motion directions of the target can be detected independent of the background by using the proposed network.     

Simple analog-digital motion detection circuit and its application to mobile robot

Simple analog-digital circuits for detecting the motion direction based on the information processing of the vertebrate retina were proposed. A network constructed with an array of proposed circuits was applied to a mobile robot. A test circuit was fabricated using discrete metal oxide semiconductor (MOS) transistors on a breadboard. The measured results of the test circuit showed that the unit circuit can output a motion signal. The motion sensor for detecting the movement direction, which consists of an array of unit circuits, was connected to the microcomputer introduced in the mobile robot. It was clarified that the proposed circuits can control the mobile robot.     

Analog vision chip for motion detection of an approaching object against a moving background based on the insect visual system

A network for motion detection of an approaching object without influence of the moving background was proposed based on the insect visual system. The two-dimensional array of the analog complementary metal oxide semiconductor (CMOS) circuits for extracting the edge signals of the approaching object without outputting those of the moving background was inserted at the first stage of the network. At the next stage, analog CMOS circuits for detection of approaching velocity and direction, which accept the extracted edge signals, were inserted based on the locust vision system. A chip of the proposed network was fabricated with the 1.2 mm CMOS process. It was clarified from the measured results and the simulation results with the simulation program with integrated circuit emphasis (SPICE) that the two-dimensional circuits of the first stage can only generate the signals of target edges. The measured results showed that the chip can detect the approaching velocity and direction of the target in the image which contains the moving background.     

Signal Formation of Image-Edge Motion Based on Biological Retinal Networks and Implementation into an Analog Metal-Oxide-Silicon Circuit

A simplified model was proposed for the formation of edge signals and generation of motion signals of a target based on the information processing mechanisms of outer and inner retinas of a vertebrate. Analog metal-oxide-silicon (MOS) integrated circuits were designed based on the model. Simulation program with integrated circuit emphasis (SPICE) simulation results showed the performance of local adaptation over a wide dynamic range in the outer retinal circuit and generation of the velocity signal of a moving edge in the inner retinal circuit. Preliminary experimental results showed local adaptation in a given input range in the outer retinal circuit and the generation of motion pulsed signals in the inner retinal circuit.     

Analog Integrated Circuit for Motion Detection of Approaching Object Based on the Insect Visual System

A network for detection of an approaching object was proposed and fabricated based on the transient response of a descending contralateral movement detector (DCMD) existing in the brain of locusts. The proposed network was constructed with simple analog circuits. The experimental results of a test chip fabricated with a 1.2 $mUm complementary metal-oxide-semiconductor (CMOS) process and the results with a simulation program with integrated circuit emphasis (SPICE) showed that the proposed network is able to detect the approach by generating a peak current just before collision; the peak current allows detection of the approaching velocity and direction without collision. The proposed network could be applied to two-dimensional arrays for three-dimensional motion detection.     

Analog Metal-Oxide-Semiconductor Integrated Circuit Implementation of Approach Detection with Simple-Shape Recognition Based on Visual Systems of Lower Animals

We proposed an analog network for motion detection of an approaching object with simple-shape recognition based on the visual systems of lower animals. Locusts can detect an approaching object by performing a simple process in a descending contralateral motion detector (DCMD) existing in their brain, which senses the increase in size and expansion velocity of the image projected on a retina just before collision. The responses correspond to the approaching velocity and direction. Frogs can recognize a simple shape by performing a simple process in a tectum and thalamus existing in their brain based on retinal information; this is called the Ewert von Seelen model. The proposed network was constructed with simple analog metal-oxide-semiconductor (MOS) circuits. Simulation results with a simulation program with integrated circuit emphasis (SPICE) showed that the network was able to detect the approaching velocity and direction, and also recognized simple shapes such as a circle, square, triangle and rectangle.     

基于金属氧化物半导体晶体管Colpitts混沌振荡电路及其同步研究

用金属氧化物半导体(MOS)晶体管模型取代传统Colpitts混沌振荡电路中的三极管模型, 提出了一种基于MOS管的Colpitts混沌振荡电路. 通过合适的归一化方法, 得到了与基于三极管电路类似的状态模型. 平衡点的指标说明两种结构产生混沌的机理并不相同. 然后, 通过参数反演, 得到了详细的电路参数, 并用Pspice软件仿真得到了混沌吸引子和混沌信号的频谱图, 说明了此结构可在低电压下工作并且能产生高频率的混沌信号. 最后, 用误差反馈的方法实现了这种结构的同步. 关键词： Colpitts混沌 金属氧化物半导体晶体管 低电压 误差反馈同步     

An Integrated Circuit for Two-Dimensional Edge-Detection with Local Adaptation Based on Retinal Networks

We designed an integrated circuit for edge detection of a two-dimensional image based on the vertebrate outer retina, which has wide dynamic range in image processing. The unit circuit is simple, and operates as a current-mode analog metal-oxide-semiconductor (MOS) circuit. In order to extract edges from an image composed of bright and dark domains, the circuit realizes a function called local adaptation in which the sensitivity adapts to local brightness of the image. Simulation results, using the simulation program with integrated circuit emphasis (SPICE), of two-dimensional Gaussian-distributed images in which the intensity ranged over four orders of magnitude, showed the local adaptation. As a result, the intensity of output images was in the range of one order of magnitude. Furthermore, as the simulation result of real images, it was shown that edges in the dark domain, which was five times darker than the bright domain, were successfully detected as the bright domain in which input photocurrents ranged over two orders of magnitude.     

Optimization of fat tree encoder for ultra high speed analog to digital converter using 45 nanometer technology

The design of high speed, compact and low power fat tree encoder circuits using static CMOS gates is presented. In this paper, we propose a modified 3 bit fat tree encoder (FTE) that can operate in high frequency without a sophisticated circuit structure. In addition, the technique of hardware sharing is adopted in this design to reduce the number of transistors. The study uses complementary metal oxide semiconductor (CMOS) 45 nm-technology. The proposed static design has improved delay and power compared to a conventional ROM encoder circuit implementation. The simulation result indicates that it functions successfully and works at 200-MHz speed. The average power consumption of the circuit under room temperature is 20.7 nW. The total core area is 0.011 mm². As expected, the proposed design can be easily integrated in various kind of digital application.     

A Complementary Metal-Oxide-Semiconductor Vision Chip for Edge and Motion Detection with a Function for Output Offset Cancellation

We have designed and fabricated a complementary metal-oxide-semiconductor (CMOS) vision chip by modeling cells of the human retina as hardware that are involved in edge and motion detection. There are several fluctuation factors which affect the characteristics of metal-oxide-semiconductor field effect transistors (MOSFETs) through the CMOS fabrication process and this effect appears as the output offset of the vision chip, which is composed of pixel arrays and readout circuits. The vision chip which detects edge and motion information from an input image is used for the input stage of other systems. Therefore, the output offset of the vision chip determines the efficiency of the entire system. In order to eliminate the offset at the output stage, we designed a vision chip utilizing the correlated double sampling (CDS) technique. The chip has been fabricated using a 0.6 m standard CMOS process. With reliable output characteristics, this chip can be used at the input stage for various applications. © 2005 The Optical Society of Japan     

Analog Integrated Circuit for Motion Detection with Simple-Shape Recognition Based on Frog Vision System

We proposed in this research a novel two-dimensional network based on the frog visual system, with a motion detection function and a newly developed simple-shape recognition function, for use in object discrimination by integrated circuits. Specifically, the network mimics the signal processing of the small-field cell in a frog brain, consisting of the tectum and thalamus, which generates signals of the motion and simple shape of an object. The proposed network is constructed from simple analog complementary metal oxide semiconductor (CMOS) circuits; a test chip of the proposed network was fabricated with a 1.2 μm CMOS process. Measurements on the chip clarified that the proposed network can generate signals of the moving direction, velocity, and simple shape, as well as perform information processing of the small-field cell. Results with the simulation program with integrated circuit emphasis (SPICE) showed that the analog circuits used in the network have low power consumption. Applications of the proposed network are expected to realize advanced vision chips with functions such as object discrimination and target tracking.     

Step-by-step implementation of an amplifier circuit with a graphene field-effect transistor on a printed-circuit board

Power amplifier circuits are implemented with graphene field-effect transistors (FETs), capacitors and inductors, and their gain is improved step-by-step by adjusting the passive components. The transistors are fabricated on a 150-mm wafer using conventional complementary-metal-oxide semiconductor processing along with graphene transferring processes. The completed circuit is implemented on a printed circuit board, which allows for adjustment of the external capacitance and inductance to study the performance of graphene RF FETs. A maximum signal gain of 1.3 dB is achieved at 380 MHz. The device parameters of the transistors are then extracted and the gain is analyzed, and the results show that lowering the source–drain conductance and gate resistance is the key in realizing high performance circuits.     

32 × 32 SOI CMOS image sensor with pinned photodiode on handle wafer

We have fabricated a 32 × 32 silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) active pixel image sensor with a pinned photodiode on a handle wafer. The structure of one pixel is a four-transistor type active pixel sensor (APS) which consists of a reset and a source follower transistor on a seed wafer, and is comprised of a photodiode, a transfer gate, and a floating diffusion on the handle wafer. The photodiode could be optimized for better quantum efficiency and low dark currents because its process on the handle wafer is independent of that of transistors on a seed wafer. Most of the wavelengths are absorbed within the visible range, because the optimized photodiode is located on the handle wafer. The image has been captured by the fabricated 32 × 32 SOI CMOS image sensor with array pixels, vertical scanner, horizontal scanner, and delta-difference sampling circuit.     

纳米器件的制备、表征及其应用

利用建立的常规光刻法的纳米加工工艺系统，研制碳纳米管晶体管，单电子晶体管和单电子晶体集成的纳米器件，研制出了90K的单电子晶体管，实现了两单电子晶体管的电容耦合集成，多个单电子晶体管的串联集成以及单电子晶体管与传统器件的集成。     

基于APD线列的单光子探测计数研究

单光子探测系统可以对单个光子进行探测;探测系统含有探测部分、淬灭电路部分和计数部分;探测部分主要由工作在盖革模式下的雪崩光电二极管组成;在盖革模式下的雪崩光电二极管发生雪崩后不能自然停止,淬灭部分主要为了主动抑制雪崩电流,快速降低雪崩电压,以达到提高探测效率,降低错误计数的目的;APD线列产生多个光子脉冲信号,计数部分的主要功能是对多路光子脉冲信号进行计数、显示并且可以控制每路APD的比较电压,保证每路APD淬灭电路的正常工作。     

Amorphous silicon logic integrated circuits

Amorphous silicon thin-film integrated circuits, with between 4 and 18 transistor functions per chip, have been fabricated on glass substrates. The amorphous silicon and the dielectric layers are deposited by rf glow discharge. The circuits have been designed to realize basic logic functions such as inverters, NAND and NOR gates, and addressable memory cells. For the first time, an amorphous silicon flip flop requiring a supply voltage of only 4.5 V has been manufactured. The logic voltage levels of the flip flop are compatible with standard bipolar TTL circuits. Measurements on an inverter chain show a typical propagation delay time of 70 s and a power-delay-time product of 65 pJ. All of the circuits use n-channel enhancement type load transistors instead of integrated ohmic load resistors. The channel length of the driver transistors is 15 m with a gate source/drain overlap of 7.5 m. Experimental geometry ratios range from =2.25 to =21. Generally, the driver transistors exhibit on/off ratios greater than 10⁶ for supply voltages smaller than 5 V. At these voltages the measured on-currents per unit channel width are in the order of 5...10nA/m.The influence of the geometry ratio on static inverter characteristic and switching speed is discussed by means of a simple model. Two different manufacturing schemes for the fabrication of the integrated circuits are outlined. Mask layouts and experimental transfer characteristics of several integrated circuits are presented.     

High-speed CMOS readout integrated circuit for large-scale and high-resolution microbolometer array

A new CMOS readout integrated circuit (ROIC) for microbolometric focal plane array (FPA) is proposed in this paper. By applying multiple-module parallel working technique, the pixel readout speed of the CMOS ROIC can reach 10 MHz, which is very suitable for large-scale microbolometer array. The CMOS ROIC of each parallel working module consists of three major parts: direct injection (DI) input circuits, column-shared integrating circuits, and common noise-suppressing circuits. The readout structure of the ROIC is simple because of the DI input, shared and common circuits, and this makes the ROIC satisfy the requirements of small-pixel microbolometric FPA. Furthermore, the voltage signals from different working modules can be output according to a certain order through a high-speed output circuit. An experimental readout chip based on the proposed ROIC has been designed and fabricated to verify its readout function and performance. The measurement results of the experimental readout chip have successfully proved that the proposed CMOS ROIC can be applied to high-speed, low-noise, large-scale and high-resolution microbolometric FPA.     

A Bio-Inspired 128 × 128 Complementary Metal–Oxide–Semiconductor Vision Chip for Edge Detection with Signal Processing Circuit Separated from Photo-Sensing Circuit

In this paper, a vision chip for edge detection based on the structure of biological retina is introduced. The key advantage of retinal structure is speed of operation. However, bio-inspired vision chips have suffered from low resolution which is caused by their complex circuit structure. To sufficiently improve the resolution for real application, the circuits for analog processing were separated from circuits for image capturing. In addition, we compensated the low speed problem of operation which is caused by bottleneck of data transfer between photo-sensors and analog processing circuit by adding a reset decoder. The vision chip was fabricated using 0.35 μm 2-poly 4-metal complementary metal---oxide---semiconductor technology. Using the vision chip, we could obtain a contrast-enhanced image without any other cost-increase for fabrication of chips. Then, the edge image was easily achieved by thresholding the previous contrast-enhanced image.     

An improved design approach for thin film solar cells

In this paper an improved design for thin film solar cells is proposed to enhance conversion efficiency. This proposed structure includes two pairs of additional contact to the reversed bias of absorber and buffer layers, directly. The purpose of additional electrodes is to control the carrier distribution in the active region of device. This idea has been implemented on the fabricated Copper indium gallium selenide solar cell with the record efficiency of 22%. The simulations show an improvement of 2% in the conversion efficiency is obtained by direct application of reverse biasing on the absorber and buffer layer. The increase of short circuit current more than 3 mA/cm² is responsible for the improved performance. The open circuit voltage and fill factor of cell can also be increased by the controlling reverse bias.