Investigation of the interface trap density and series resistance of a high-k HfO2-based MOS capacitor: before and after 50 MeV Li3+ ion irradiation

This is the first investigation on the effects of 50 MeV Li³⁺ ions on interface trap density (D _it) and series resistance (R _s), which reveal the improvement of the dielectric properties of RF-sputtered HfO₂-metal oxide semiconductor (MOS) capacitors. The samples were irradiated and characterized at room temperature. The D _it and R _s were determined from the capacitance–voltage (C–V) and conduction–voltage (G–V) characteristics at 1 MHz. The measured capacitance and conductance were corrected for series resistance. It is found that the series resistance of Al/HfO₂/p? Si MOS capacitors increases with ion fluence, calculated at a strong accumulation region before and after irradiation. The interface state density of MOS devices before and after irradiation is found to decrease with increasing ion fluence.     

Temperature-dependent current conduction mechanism and charge trapping in Ta2O5 RF-sputtered on GaN

A gallium nitride (GaN) based Metal-Oxide-Semiconductor (MOS) capacitor was fabricated using radio frequency (RF)-sputtered tantalum oxide (Ta₂O₅) as the high-k gate dielectric. Electrical characteristics of this capacitor were evaluated via capacitance–voltage (C–V), current–voltage (I–V), and interface trap density (D_it) measurements with emphasis on the substrate temperature dependence ranging from 25 °C to 200 °C. Charge trapping and conduction mechanism in Ta₂O₅ were investigated. The experimental results suggested that higher substrate temperature rendered higher oxide capacitance, reduced gate leakage current, and lowered mid-gap interface trap density at the expenses of high border traps and high fixed oxide charges. The gate leakage current through Ta₂O₅ was found to obey the Ohm's conduction at lower gate bias and the Poole–Frenkel conduction at higher gate bias.     

Swift ion irradiation effect on high-k ZrO2- and Al2O3-based MOS devices

This paper describes the heavy ion-induced effects on the electrical characteristics of reactively sputtered ZrO₂ and Al₂O₃ high-k gate oxides deposited in argon plus nitrogen containing plasma. Radiation-induced degradation of sputtered high-k dielectric ZrO₂/Si and Al₂O₃/Si interface was studied using 45?MeV Li³⁺ ions. The devices were irradiated with Li³⁺ ions at various fluences ranging from 5?×?10⁹ to 5?×?10¹²?ions/cm². Capacitance–voltage and current–voltage characteristics were used for electrical characterization. Shift in flat band voltage towards negative value was observed in devices after exposure to ion radiation. Post-deposition annealing effect on the electrical behavior of high-k/Si interface was also investigated. The annealed devices showed better electrical and reliability characteristics. Different device parameters such as flat band voltage, leakage current, interface defect density and oxide-trapped charge have been extracted.The surface morphology and roughness values for films deposited in nitrogen containing plasma before and after ion radiation are extracted from Atomic Force Microscopy.     

Effects of heavy-ion irradiation on the electrical properties of rf-sputtered HfO2 thin films for advanced CMOS devices

HfO₂-based metal-oxide semiconductor (MOS) capacitors were irradiated with high-energy ion beam to study the irradiation effects in these films. HfO₂ thin films deposited by radio frequency (rf)-sputtering were irradiated with 80 MeV O⁶⁺ ions. The samples were irradiated and characterized at room temperature. Devices were characterized via 1 MHz capacitance–voltage (C?V) measurements using the midgap method. The irradiation induced dispersion in accumulation and depletion regions with increasing fluence is observed. After irradiation, the midgap voltage shift (Δ V _mg) of?0.61 to?1.92 V, flat band voltage shift (Δ V _fb) of?0.48 to?2.88 V and threshold voltage shift (Δ V _th) of?0.966 to?1.96 V were observed. The change in interface trap charge and oxide trap charge densities after 80 MeV O⁶⁺ ions irradiation with fluences were determined from the midgap to flat band stretch out of C?V curves. The results are reported and explained in terms of changes in microstructure and dielectric properties of the HfO₂ thin films after irradiation.     

On a current mechanism in Ta2O5 thin films

Electrical conduction in the temperature range of 120–370 K has been studied in sandwiched structures of Al/Ta₂O₅/Si. The tantalum oxide films were prepared by evaporation of tantalum on a p-Si crystal substrate, followed by oxidation at a temperature of 600°C. The temperature-dependent current-voltage (I–V) characteristics are explained on the basis of a phonon-assisted tunnelling model. The same explanation is given for I–V data measured on Ta₂O₅ films by other investigators. From the comparison of experimental data with theory the density of states in the interface layer is derived and the electron-phonon interaction constant is assessed.      

Memory characteristics of platinum nanoparticle-embedded MOS capacitors

The capacitance characteristics of platinum nanoparticle (NP)-embedded metal–oxide–semiconductor (MOS) capacitors with gate Al₂O₃ layers are studied in this work. The capacitance versus voltage (C–V) curves obtained for a representative MOS capacitor exhibit flat-band voltage shifts, demonstrating the presence of charge storages in the platinum NPs. The counterclockwise hysteresis and flat-band voltage shift, observed from the C–V curves imply that electrons are stored in a floating gate layer consisting of the platinum NPs present between the tunneling and control oxide layers in the MOS capacitor and that these stored electrons originate from the Si substrate. Moreover, the charge remains versus time curve for the platinum NP-embedded MOS capacitor is investigated in this work.     

Effects of Y incorporation in TaON gate dielectric on electrical performance of GaAs metal–oxide–semiconductor capacitor

In this study, GaAs metal–oxide–semiconductor (MOS) capacitors using Y‐incorporated TaON as gate dielectric have been investigated. Experimental results show that the sample with a Y/(Y + Ta) atomic ratio of 27.6% exhibits the best device characteristics: high k value (22.9), low interfacestate density (9.0 × 10¹¹ cm^–2 eV^–1), small flatband voltage (1.05 V), small frequency dispersion and low gate leakage current (1.3 × 10^–5A/cm² at V_fb + 1 V). These merits should be attributed to the complementary properties of Y₂O₃ and Ta₂O₅:Y can effectively passivate the large amount of oxygen vacancies in Ta₂O₅, while the positively‐charged oxygen vacancies in Ta₂O₅ are capable of neutralizing the effects of the negative oxide charges in Y₂O₃. This work demonstrates that an appropriate doping of Y content in TaON gate dielectric can effectively improve the electrical performance for GaAs MOS devices.

Capacitance–voltage characteristic of the GaAs MOS capacitor with TaYON gate dielectric (Y content = 27.6%) proposed in this work with the cross sectional structure and dielectric surface morphology as insets.     

Electrical characteristics of Ta2O5 based capacitors with different gate electrodes

Al, W and TiN gate stacks using reactively sputtered thin (15–35 nm) Ta₂O₅ as a high-k dielectric have been investigated. It has been established that the type and the deposition technique of the gate electrode strongly affect the parameters of the structures. RF sputtered tungsten has been established as the most suitable electrode material (giving a nonreactive contact) providing a low leakage current (∼10^-8 A/cm² at 1 MV/cm) through capacitors and a high dielectric constant. The application of Al gate electrodes in the advanced DRAM devices is impeded by the chemical interaction of Al with the Ta₂O₅ films deteriorating the performance of the structures. The radiation-induced defects during the TiN deposition increase the leakage currents for TiN/Ta₂O₅/Si capacitors. A modified Poole–Frenkel conduction mechanism with a tendency for a reduction of the compensation level with increasing Ta₂O₅ thickness was found for W-gate capacitors. Schottky emission at low applied fields and modified Poole–Frenkel mechanism at high fields define the J–V characteristics of Al capacitors. The current through TiN capacitors is governed by ohmic and space charge limited conduction. The post metallization annealing in H₂ reduces the oxide charge but deteriorates both the breakdown fields and the leakage currents for all capacitors studied. The effect is stronger for Al and TiN structures and is accompanied by a reduction of the dielectric constant. PACS 72.80.Sk; 73.40.Qv; 77.55+f; 81.15 Cd     

Stability of La2O3 and GeO2 passivated Ge surfaces during ALD of ZrO2 high-k dielectric

La₂O₃ grown by atomic layer deposition (ALD) and thermally grown GeO₂ are used to establish effective electrical surface passivations on n-type (1 0 0)-Ge substrates for high-k ZrO₂ dielectrics, grown by ALD at 250 °C substrate temperature. The electrical characterization of MOS capacitors indicates an impact of the Ge-surface passivation on the interfacial trap density and the frequency dependent capacitance in the inversion regime. Lower interface trap densities can be obtained for GeO₂ based passivation even though a chemical decomposition of the oxidation states occur during the ALD of ZrO₂. As a consequence the formation of a ZrGeO_x compound inside the ZrO₂ matrix and a decline of the interfacial GeO₂ are observed. The La₂O₃ passivation provides a stable amorphous lanthanum germanate phase at the Ge interface but also traces of Zr germanate are indicated by X-ray-Photoelectron-Spectroscopy and Transmission-Electron-Microscopy.     

Study of radiation damage induced by 12 keV X‐rays in MOS structures built on high‐resistivity n‐type silicon

Imaging experiments at the European X‐ray Free Electron Laser (XFEL) require silicon pixel sensors with extraordinary performance specifications: doses of up to 1 GGy of 12 keV photons, up to 10⁵ 12 keV photons per 200 µm × 200 µm pixel arriving within less than 100 fs, and a time interval between XFEL pulses of 220 ns. To address these challenges, in particular the question of radiation damage, the properties of the SiO₂ layer and of the Si–SiO₂ interface, using MOS (metal‐oxide‐semiconductor) capacitors manufactured on high‐resistivity n‐type silicon irradiated to X‐ray doses between 10 kGy and 1 GGy, have been studied. Measurements of capacitance/conductance–voltage (C/G–V) at different frequencies, as well as of thermal dielectric relaxation current (TDRC), have been performed. The data can be described by a dose‐dependent oxide charge density and three dominant radiation‐induced interface states with Gaussian‐like energy distributions in the silicon band gap. It is found that the densities of the fixed oxide charges and of the three interface states increase up to dose values of approximately 10 MGy and then saturate or even decrease. The shapes and the frequency dependences of the C/G–V measurements can be quantitatively described by a simple model using the parameters extracted from the TDRC measurements.     

Stress-induced leakage currents of the RF sputtered Ta2O5 on N-implanted silicon

The electrical (C-V and I-V) and reliability (constant current stress technique) properties of RF sputtered 30 nm thick Ta₂O₅ on N-implanted Si have been investigated. The dependence on the parameters of both Ta₂O₅ and the implanted interfacial layers on the stress time are discussed. The leakage current characteristics are analyzed by previously proposed comprehensive model. It is established that the reliability of the Ta₂O₅-based capacitors can be effectively improved if the Si substrate is a subject to preliminary N-implantation—markedly smaller stress induced leakage current as compared to the films on bare Si are detected. The stress mainly affects the properties of the interfacial layer and the generation of neutral traps is identified to be the primary cause for the stress-induced degradation. It is concluded that the implantation results in a strengthening of the interfacial layer against stress degradation.     

Physical and electrical characteristics of a high-k Yb2O3 gate dielectric

High-k ytterbium oxide (Yb₂O₃) gate dielectrics were deposited on Si substrate by reactive sputtering. The structural features of these films after postdeposition annealing treatment were studied by X-ray diffraction and X-ray photoelectron spectroscopy. It is found that the Yb₂O₃ gate dielectrics annealed at 700 °C exhibit a larger capacitance value, a lower frequency dispersion and a smaller hysteresis voltage in C-V curves compared with other annealing temperatures. They also show negligible charge trapping under high constant voltage stress. This phenomenon is mainly attributed to the decrease in the amorphous silica thickness.     

Al2O3绝缘层的AlGaN/GaN MOSHEMT器件研究

在研制AlGaN/GaN HEMT器件的基础上,采用ALD法制备了Al₂O₃ AlGaN/GaN MOSHEMT器件.通过X射线光电子能谱测试表明在AlGaN/GaN异质结材料上成功淀积了Al₂O₃薄膜.根据对HEMT和MOSHEMT器件肖特基电容、器件输出以及转移特性的测试进行分析发现：所制备的Al₂O₃薄膜与AlGaN外延层间界面态密度较小,因而MOSHEMT器件呈现出较 关键词： 2O₃')" href="#">Al₂O₃ ALD GaN MOSHEMT     

Characterization of Y2O3 gate dielectric on n-GaAs substrates

Physical and electrical properties of sputtered deposited Y₂O₃ films on NH₄OH treated n-GaAs substrate are investigated. The as-deposited films and interfacial layer formation have been analyzed by using X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS). It is found that directly deposited Y₂O₃ on n-GaAs exhibits excellent electrical properties with low frequency dispersion (<5%), hysteresis voltage (0.24 V), and interface trap density (3 × 10¹² eV⁻¹ cm⁻²). The results show that the deposition of Y₂O₃ on n-GaAs can be an effective way to improve the interface quality by the suppression on native oxides formation, especially arsenic oxide which causes Fermi level pinning at high-k/GaAs interface. The Al/Y₂O₃/n-GaAs stack with an equivalent oxide thickness (EOT) of 2.1 nm shows a leakage current density of 3.6 × 10⁻⁶ A cm⁻² at a V_FB of 1 V. While the low-field leakage current conduction mechanism has been found to be dominated by the Schottky emission, Poole-Frenkel emission takes over at high electric fields. The energy band alignment of Y₂O₃ films on n-GaAs substrate is extracted from detailed XPS measurements. The valence and conduction band offsets at Y₂O₃/n-GaAs interfaces are found to be 2.14 and 2.21 eV, respectively.     

Influence of Si/SiO2 interface properties on electrical performance and breakdown characteristics of ultrathin stacked oxide/nitride dielectric films

In this work, the influence of Si/SiO₂ interface properties, interface nitridation and remote-plasma-assisted oxidation (RPAO) thickness (<1 nm), on electrical performance and TDDB characteristics of sub-2 nm stacked oxide/nitride gate dielectrics has been investigated using a constant voltage stress (CVS). It is demonstrated that interfacial plasma nitridation improves the breakdown and electrical characteristics. In the case of PMOSFETs stressed in accumulation, interface nitridation suppresses the hole traps at the Si/SiO₂ interface evidenced by less negative V_t shifts. Interface nitridation also retards hole tunneling between the gate and drain, resulting in reduced off-state drain leakage. In addition, the RPAO thickness of stacked gate dielectrics shows a profound effect in device performance and TDDB reliability. Also, it is demonstrated that TDDB characteristics are improved for both PMOS and NMOS devices with the 0.6 nm-RPAO layer using Weibull analysis. The maximum operating voltage is projected to be improved by 0.3 V difference for a 10-year lifetime. However, physical breakdown mechanism and effective defect radius during stress appear to be independent of RPAO thickness from the observation of the Weibull slopes. A correlation between trap generation and dielectric thickness changes based on the C-V distortion and oxide thinning model is presented to clarify the trapping behavior in the RPAO and bulk nitride layer during CVS stress.     

Electrical and material characterization of tantalum pentoxide (Ta2O5) charge trapping layer memory

In this experiment, tantalum pentoxide (Ta₂O₅) was used in a metal/oxide/high-k Ta₂O₅/oxide/silicon (MOHOS) novel nanocrystal memory as a trapping layer. Post-annealing treatment, which can passivate defects and improve the material quality of the high-k dielectric, was applied to optimize device performance for a better memory window and faster P/E (program/erase) cycle. Material and electrical characterization techniques including X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM), and electrical measurements were performed to analyze the device under different annealing conditions. The Ta₂O₅ charge trapping layer memory annealed at 900 °C had a higher window of 3.3 V in the current-voltage (C-V) hysteresis loop, and a higher charge retention capability than the samples prepared under various annealing conditions. These higher levels were due to the higher probability of deep-level charge trapping and lower leakage current.     

DLTS and in situ C–V analysis of trap parameters in swift 50 MeV Li3+ ion-irradiated Ni/SiO2/Si MOS capacitors

Ni/SiO₂/Si MOS structures were fabricated on n-type Si wafers and were irradiated with 50 MeV Li³⁺ ions with fluences ranging from 1×10¹⁰ to 1×10¹² ions/cm². High frequency C–V characteristics are studied in situ to estimate the build-up of fixed and oxide charges. The nature of the charge build-up with ion fluence is analyzed. Defect levels in bulk Si and its properties such as activation energy, capture cross-section, trap concentration and carrier lifetimes are studied using deep-level transient spectroscopy. Electron traps with energies ranging from 0.069 to 0.523 eV are observed in Li ion-irradiated devices. The dependence of series resistance, substrate doping and accumulation capacitance on Li ion fluence are clearly explained. The study of dielectric properties (tan δ and quality factor) confirms the degradation of the oxide layer to a greater extent due to ion irradiation.     

Influence of postdeposition annealing on structural properties and electrical characteristics of thin Tm2O3 and Tm2Ti2O7 dielectrics

We describe the structural properties and electrical characteristics of thin thulium oxide (Tm₂O₃) and thulium titanium oxide (Tm₂Ti₂O₇) as gate dielectrics deposited on silicon substrates through reactive sputtering. The structural and morphological features of these films were explored by X-ray diffraction, X-ray photoelectron spectroscopy, secondary ion mass spectrometry, and atomic force microscopy, measurements. It is found that the Tm₂Ti₂O₇ film annealed at 800 °C exhibited a thinner capacitance equivalent thickness of 19.8 Å, a lower interface trap density of 8.37 × 10¹¹ eV⁻¹ cm⁻², and a smaller hysteresis voltage of ∼4 mV than the other conditions. We attribute this behavior to the Ti incorporated into the Tm₂O₃ film improving the interfacial layer and the surface roughness. This film also shows negligible degrees of charge trapping at high electric field stress.     

Metal-oxide-semiconductor characteristics of lanthanum cerium oxide film on Si

Metal-organic decomposed lanthanum cerium oxide (La _x Ce _y O _z ) film had been spin-coated on n-type Si substrate. Effects of post-deposition annealing temperature and time on the metal-oxide-semiconductor (MOS) properties of the film were studied. As temperature increased from 400 to 1000°C for 15 minutes dwell time, La _x Ce _y O _z demonstrated a decrease in interface trap density (D _it) and total interface trap density (D _total), which were related to the formation of SiO _x /silicates interfacial layer (IL). The lowest leakage current density and highest dielectric breakdown voltage (V _B) was obtained in 1000°C-annealed sample. When longer annealing times (30–120 minutes) were studied on the 1000°C-annealed sample, the sample annealed at 1000°C for 120 min showed the best MOS characteristics with V _B of 30 V. Reasons contributing to such observation were discussed.     

Effect of annealing temperature on the electrical properties of Au/Ta2O5/n-GaN metal–insulator–semiconductor (MIS) structure

We report on the effect of an annealing temperature on the electrical properties of Au/Ta₂O₅/n-GaN metal–insulator–semiconductor (MIS) structure by current–voltage (I–V) and capacitance–voltage (C–V) measurements. The measured Schottky barrier height (Φ _bo) and ideality factor n values of the as-deposited Au/Ta₂O₅/n-GaN MIS structure are 0.93 eV (I–V) and 1.19. The barrier height (BH) increases to 1.03 eV and ideality factor decreases to 1.13 upon annealing at 500 ^°C for 1 min under nitrogen ambient. When the contact is annealed at 600 ^°C, the barrier height decreases and the ideality factor increases to 0.99 eV and 1.15. The barrier heights obtained from the C–V measurements are higher than those obtained from I–V measurements, and this indicates the existence of spatial inhomogeneity at the interface. Cheung’s functions are also used to calculate the barrier height (Φ _bo), ideality factor (n), and series resistance (R _s ) of the Au/Ta₂O₅/n-GaN MIS structure. Investigations reveal that the Schottky emission is the dominant mechanism and the Poole–Frenkel emission occurs only in the high voltage region. The energy distribution of interface states is determined from the forward bias I–V characteristics by taking into account the bias dependence of the effective barrier height. It is observed that the density value of interface states for the annealed samples with interfacial layer is lower than that of the density value of interface states of the as-deposited sample.