Performance Analysis for MPEG‐4 Video Codec Based on On‐Chip Network

In this paper, we present a performance analysis for an MPEG‐4 video codec based on the on‐chip network communication architecture. The existing on‐chip buses of system‐on‐a‐chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on‐chip network is introduced to solve the problem of on‐chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG‐4 video codec based on the on‐chip network and Advanced Micro‐controller Bus Architecture (AMBA) on‐chip bus. Experimental results show that the performance of the MPEG‐4 video codec based on the on‐chip network is improved over 50% compared to the design based on a multi‐layer AMBA bus.     

Low‐Power 512‐Bit EEPROM Designed for UHF RFID Tag Chip

In this paper, the design of a low‐power 512‐bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low‐power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage‐up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 μm EEPROM process. Power dissipation is 32.78 μW in the read cycle and 78.05 μW in the write cycle. The layout size is 449.3 μm × 480.67 μm.     

Easily Adaptable On‐Chip Debug Architecture for Multicore Processors

Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time‐consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on‐chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run‐stop mode debugging. Compared with the debug architecture that supports the run‐stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on‐chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.     

On‐Chip Debug Architecture for Multicore Processor

Because of the intrinsic lack of internal‐system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on‐chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run‐stop‐type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG‐based scanning operation. We apply this on‐chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.     

Design Space Exploration for NoC‐Style Bus Networks

With the number of IP cores in a multicore system‐on‐chip increasing to up to tens or hundreds, the role of on‐chip interconnection networks is vital. We propose a networks‐on‐chip‐style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade‐off for the time saving, the time cost (TC) of the searched architecture is increased to up to and , respectively, at each step compared with that of the architecture obtained through full‐case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to when compared with that obtained through full‐case exploration.     

High‐Performance On‐Chip Thermionic Electron Micro‐Emitter Arrays Based on Super‐Aligned Carbon Nanotube Films

An important advancement towards the realization of miniaturized and fully integrated vacuum electronic devices will be the development of on‐chip integrated electron sources with stable and reproducible performances. Here, the fabrication of high‐performance on‐chip thermionic electron micro‐emitter arrays is demonstrated by exploiting suspended super‐aligned carbon nanotube films as thermionic filaments. For single micro‐emitter, an electron emission current up to ≈20 µA and density as high as ≈1.33 A cm^?2 are obtained at a low‐driven voltage of 3.9 V. The turn‐on/off time of a single micro‐emitter is measured to be less than 1 µs. Particularly, stable (±1.2% emission current fluctuation for 30 min) and reproducible (±0.2% driven voltage variation over 27 cycles) electron emission have been experimentally observed under a low vacuum of ≈5 × 10^?4 Pa. Even under a rough vacuum of ≈10^?1 Pa, an impressive reproducibility (±2% driven voltage variation over 20 cycles) is obtained. Moreover, emission performances of micro‐emitter arrays are found to exhibit good uniformity. The outstanding stability, reproducibility, and uniformity of the thermionic electron micro‐emitter arrays imply their promising applications as on‐chip integrated electron sources.     

On‐Chip Fabrication of Paclitaxel‐Loaded Chitosan Nanoparticles for Cancer Therapeutics

The use of solvent‐free microfluidics to fine‐tune the physical and chemical properties of chitosan nanoparticles for drug delivery is demonstrated. Nanoparticle self‐assembly is driven by pH changes in a water environment, which increases biocompatibility by avoiding organic solvent contamination common with traditional techniques. Controlling the time of mixing (2.5–75 ms) during nanoparticle self‐assembly enables us to adjust nanoparticle size and surface potential in order to maximize cellular uptake, which in turn dramatically increases drug effectiveness. The compact nanostructure of these nanoparticles preserves drug potency better than previous nanoparticles, and is more stable during long‐term circulation at physiological pH. However, when the nanoparticles encounter a tumor cell and the associated drop in pH, the drug contents are released. Moreover, the loading efficiency of hydrophobic drugs into the nanoparticles increases significantly from previous work to over 95%. The microfluidic techniques used here have applications not just for drug‐carrying nanoparticle fabrication, but also for the better control of virtually any self‐assembly process.     

New Path‐Setup Method for Optical Network‐on‐Chip

With high bandwidth, low interference, and low power consumption, optical network‐on‐chip (ONoC) has emerged as a highly efficient interconnection for the future generation of multicore system on chips. In this paper, we propose a new path‐setup method for ONoC to mitigate contentions, such as packets, by recycling the setup packet halfway to the destination. A new, strictly non‐blocking optical router is designed to support the new method. The simulation results show the new path‐setup method increases the throughput by 52.03%, 41.94%, and 36.47% under uniform, hotspot‐I, and hotspot‐II traffic patterns, respectively. The end‐to‐end delay performance is also improved.     

A 50‐mA 1‐nF Low‐Voltage Low‐Dropout Voltage Regulator for SoC Applications

In this paper, we present a low‐voltage low‐dropout voltage regulator (LDO) for a system‐on‐chip (SoC) application which, exploiting the multiplication of the Miller effect through the use of a current amplifier, is frequency compensated up to 1‐nF capacitive load. The topology and the strategy adopted to design the LDO and the related compensation frequency network are described in detail. The LDO works with a supply voltage as low as 1.2 V and provides a maximum load current of 50 mA with a drop‐out voltage of 200 mV: the total integrated compensation capacitance is about 40 pF. Measurement results as well as comparison with other SoC LDOs demonstrate the advantage of the proposed topology.     

An Ameliorated Design Method of ML‐AHB BusMatrix

The multi‐layer advanced high‐performance bus (ML‐AHB) BusMatrix proposed by ARM is an excellent architecture for applying embedded systems with low power. However, there is one clock cycle delay for each master in the ML‐AHB BusMatrix of the advanced microcontroller bus architecture (AMBA) design kit (ADK) whenever a master starts new transactions or changes the slave layers. In this letter, we propose an improved design method to remove the one clock cycle delay in the ML‐AHB BusMatrix of an ADK. We also remarkably reduce the total area and power consumption of the ML‐AHB BusMatrix of an ADK with the elimination of the heavy input stages.     

Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.     

A New Automatic Compensation Network for System‐on‐Chip Transceivers

This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.     

Low‐Power Video Decoding on a Variable Voltage Processor for Mobile Multimedia Applications

This paper proposes a novel low‐power video decoding scheme. In the encoded video bitstream, there is quite a large number of non‐coded blocks. When the number of the non‐coded blocks in a frame is known at the start of frame decoding, the workload of the video decoding can be estimated. Consequently, the supply voltage of very large‐scale integration (VLSI) circuits can be lowered, and the power consumption can be reduced. In the proposed scheme, the encoder counts the number of non‐coded blocks and stores this information in the frame header of the bitstream. Simulation results show that the proposed scheme reduces the power consumption to about 1/10 to 1/20.     

Adaptive Standby Mode Scheduling Method Based on Analysis of Activation Pattern for Improving User Experience of Low‐Power Set‐Top Boxes

The lowest power mode (passive‐standby mode) was proposed for reducing the power consumption of set‐top boxes in a standby state when not receiving content. However, low‐power set‐top boxes equipped with the lowest power mode have been rarely commercialized because of their low‐quality user experience. In the lowest power mode, they deactivates almost all of operational modules and processes, and thus require dozens of seconds for activation latency (that is, the latency for activating all modules of the set‐top boxes in a standby state). They are not even updated in a standby state because they deactivate their network interfaces in a standby state. This paper proposes an adaptive standby mode scheduling method for improving the user experience of such boxes. Set‐top boxes using the proposed method can analyze the activation pattern and find the frequently used time period (that is, when the set‐top boxes are frequently activated). They prepare for their activation during this frequently used time period, thereby reducing the activation latency and enabling their update in a standby state.     

Design of 100‐V Super‐Junction Trench Power MOSFET with Low On‐Resistance

Power metal‐oxide semiconductor field‐effect transistor (MOSFET) devices are widely used in power electronics applications, such as brushless direct current motors and power modules. For a conventional power MOSFET device such as trench double‐diffused MOSFET (TDMOS), there is a tradeoff relationship between specific on‐state resistance and breakdown voltage. To overcome the tradeoff relationship, a super‐junction (SJ) trench MOSFET (TMOSFET) structure is studied and designed in this letter. The processing conditions are proposed, and studies on the unit cell are performed for optimal design. The structure modeling and the characteristic analyses for doping density, potential distribution, electric field, width, and depth of trench in an SJ TMOSFET are performed and simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the specific on‐state resistance of 1.2 mΩ‐cm² at the class of 100 V and 100 A is successfully optimized in the SJ TMOSFET, which has the better performance than TDMOS in design parameters.     

High‐Performance Low‐Power FFT Cores

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low‐power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low‐power commutators based on an advanced interconnection, and parallel‐pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel‐pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.     

Voltage‐Mode 1.5 Gbps Interface Circuits for Chip‐to‐Chip Communication

In this paper, interface circuits that are suitable for point‐to‐point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi‐gigabits per‐second between two chips with a point‐to‐point interconnection, the input receiver uses an on‐chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode‐connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 µm dual gate oxide CMOS technology.     

An On‐Chip Break Junction System for Combined Single‐Molecule Conductance and Raman Spectroscopies

Systems that are capable of robustly reproducing single‐molecule junctions are an essential prerequisite for enabling the wide‐spread testing of molecular electronic properties, the eventual application of molecular electronic devices, and the development of single‐molecule based electrical and optical diagnostics. Here, a new approach is proposed for achieving a reliable single‐molecule break junction system by using a microelectromechanical system device on a chip. It is demonstrated that the platform can (i) provide subnanometer mechanical resolution over a wide temperature range (≈77–300 K), (ii) provide mechanical stability on par with scanning tunneling microscopy and mechanically controllable break junction systems, and (iii) operate in a variety of environmental conditions. Given these fundamental device performance properties, the electrical characteristics of two standard molecules (hexane‐dithiol and biphenyl‐dithiol) at the single‐molecule level, and their stability in the junction at both room and cryogenic temperatures (≈77 K) are studied. One of the possible distinctive applications of the system is demonstrated, i.e., observing real‐time Raman scattering in a single‐molecule junction. This approach may pave a way to achieving high‐throughput electrical characterization of single‐molecule devices and provide a reliable platform for the convenient characterization and practical application of single‐molecule electronic systems in the future.     

2.4‐GHz Power Amplifier with Power Detector Using Metamaterial‐Based Transformer‐Type On‐Chip Directional Coupler

This letter presents a power amplifier (PA) with an on‐chip power detector for 2.4‐GHz wireless local area network application. The power detector consists of a clamp circuit, a diode detector, and a coupled line directional coupler. A series inductor for an output matching network in the PA is combined with a through line of the coupler, which reduces the coupling level. Therefore, the coupler employs a metamaterial‐based transformer configuration to increase coupling. The amount of coupling is increased by 2.5 dB in the 1:1 symmetric transformer structure and by 4.5 dB from two metamaterial units along the coupled line.     

Digital Audio Effect System‐on‐a‐Chip Based on Embedded DSP Core

This paper describes the implementation of a digital audio effect system‐on‐a‐chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect algorithms. The audio effect SoC is developed using a software and hardware co‐design method. In the design of the SoC, the embedded DSP and some dedicated hardware blocks are developed as a hardware design, while the audio effect algorithms are realized using a software centric method. Most of the audio effect algorithms are implemented using a C code with primitive functions that run on the embedded DSP, while the equalization effect, which requires a large amount of computation, is implemented using a dedicated hardware block with high flexibility. For the optimized implementation of audio effects, we exploit the primitive functions of the embedded DSP compiler, which is a very efficient way to reduce the code size and computation. The audio effect SoC was fabricated using a 0.18 μm CMOS process and evaluated successfully on a real‐time test board.