Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO7340Q, 7325http://cpb.iphy.ac.cn/CN/10.1088/1674-1056/19/5/057302https://cpb.iphy.ac.cn/CN/article/downloadArticleFile.do?attachType=PDF&id=111774Ge substrate, transistor, HfSiON, hole mobilityProject supported by the National Basic Research Program of China (Grant No.~2006CB302704).Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO$_{x}$ ($1Ge;substrate;transistor;HfSiON;hole;mobilityGe and Si p-channel metal-oxide-semiconductor field-effect-transistors(p-MOSFETs) with hafnium silicon oxynitride(HfSiON) gate dielectric and tantalum nitride(TaN) metal gate are fabricated.Self-isolated ring-type transistor structures with two masks are employed.W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately.Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor(MOS) capacitors may be caused by charge trapping centres in GeOx(1 < x < 2).Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method.The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V.s) and 81.0 cm2/(V.s),respectively.Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.     

Finite-element study of strain field in strained-Si MOSFET

The strain field in the channel of a p-type metal-oxide-semiconductor field effect transistor fabricated by integrating Ge pre-amorphization implantation for source/drain regions is evaluated using a finite-element method combining with large angle convergent-beam electron diffraction (LACBED). The finite-element calculation shows that there is a very large compressive strain in the top layer of the channel region caused by a low dose of Ge ion implantation in the source and drain extension regions. Moreover, a transition region is formed in the bottom of the channel region and the top of the Si substrate. These calculation results are in good agreement with the LACBED experiments.     

堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管二维模型

提出了一种堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管(metal-oxide semiconductor field effect transistor,MOSFET)新器件结构.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,建立了全耗尽条件下的表面势和阈值电压的解析模型.该结构的应变硅沟道有两个掺杂区域,和常规双栅器件(均匀掺杂沟道)比较,沟道表面势呈阶梯电势分布,能进一步提高载流子迁移率;探讨了漏源电压对短沟道效应的影响;分析得到阈值电压随缓冲层Ge组分的提高而降低,随堆叠栅介质高k层介电常数的增大而增大,随源端应变硅沟道掺杂浓度的升高而增大,并解释了其物理机理.分析结果表明:该新结构器件能够更好地减小阈值电压漂移,抑制短沟道效应,为纳米领域MOSFET器件设计提供了指导.     

Direct mapping of strain in a strained silicon transistor by high-resolution electron microscopy

Aberration-corrected high-resolution transmission electron microscopy (HRTEM) is used to measure strain in a strained-silicon metal-oxide-semiconductor field-effect transistor. Strain components parallel and perpendicular to the gate are determined directly from the HRTEM image by geometric phase analysis. Si80Ge20 source and drain stressors lead to uniaxial compressive strain in the Si channel, reaching a maximum value of -1.3% just below the gate oxide, equivalent to 2.2 GPa. Strain maps obtained by linear elasticity theory, modeled with the finite-element method, agree with the experimental results to within 0.1%.     

Hetero-Epitaxy and Self-Adaptive Stressor Based on Freestanding Fin for the 10 nm Node and Beyond

A promising technology named epitaxy on nano-scale freestanding fin(ENFF) is firstly proposed for heteroepitaxy This technology can effectively release total strain energy and then can reduce the probability of generating mismatch dislocations. Based on the calculation, dislocation defects can be eliminated completely when the thickness of the Si freestanding fin is less than 10 nm for the epitaxial Ge layer. In addition, this proposed ENFF process can provide sufficient uniaxial stress for the epitaxy layer, which can be the major stressor for the SiGe or Ge channel fin field-effect transistor or nanowire at the 10 nm node and beyond. According to the results of technology computer-aided design simulation, nanowires integrated with ENFF show excellent electrical performance for uniaxial stress and band offset. The ENFF process is compatible with the state of the art mainstream technology, which has a good potential for future applications.     

Self-Aligned SiGe MOS-Gate FET with Modulation-Doped Quantum Wire Channel for Millimeter Wave Application

This paper describes a self-aligned SiGe MOS-gate field-effect transistor (FET) having a modulation-doped (MOD) quantum wire channel. An analytical model based on modified charge control equations accounting for the quantum wire channel, is presented predicting the transport characteristics of the MOS-gate MODFET structure. In particular, transport characteristics of devices having strained SiGe layers, realized on Si or Ge substrates, are computed. The transconductance g_m and unity-current gain cutoff frequency (f_T) are also computed as a function of the gate voltage V_G. The calculated values of f_T suggest the operation of one-dimensional SiGe MODFETs to be around 200 GHz range at 77°K, and 120 GHz at 300°K.     

An analytical threshold voltage model for dual-strained channel PMOSFET

Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si 1-x Ge x /relaxd Si 1-y Ge y (s-Si/s-SiGe/Si 1-y Ge y) metal-oxide-semiconductor field-effect transistor (PMOSFET),an-alytical expressions of the threshold voltages for buried channel and surface channel are presented.And the maximum allowed thickness of s-Si is given,which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si),because the hole mobility in the buried channel is higher than that in the surface channel.Thus they offer a good accuracy as compared with the results of device simulator ISE.With this model,the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted,such as Ge fraction,layer thickness,and doping concentration.This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si 1-y Ge y metal-oxide-semiconductor field-effect transistor (MOSFET) designs.     

基于能带结构的布里渊区非均匀四面体网格生成技术

基于非局域赝势能带计算及四面体网格单元中能量满足线性关系,提出一种布里渊区非均匀四面体网格产生方法,在满足精度条件下能自动得出数目最少的四面体网格,使布里渊区积分计算的精度和效率大为提高．通过对硅、锗两种金刚石结构半导体简约布里渊区所产生网格的比较,表明该方法可以根据能带结构的特点自动生成优化的非均匀网格．对现有的态密度四面体计算公式进行了补充完善,并根据生成的网格和完善后的公式计算了硅和锗导带第一、二能带的态密度．     

Effect of interface roughness on the carrier transport in germanium MOSFETs investigated by Monte Carlo method

Interface roughness strongly influences the performance of germanium metal--organic--semiconductor field effect transistors (MOSFETs). In this paper, a 2D full-band Monte Carlo simulator is used to study the impact of interface roughness scattering on electron and hole transport properties in long- and short- channel Ge MOSFETs inversion layers. The carrier effective mobility in the channel of Ge MOSFETs and the in non-equilibrium transport properties are investigated. Results show that both electron and hole mobility are strongly influenced by interface roughness scattering. The output curves for 50~nm channel-length double gate n and p Ge MOSFET show that the drive currents of n- and p-Ge MOSFETs have significant improvement compared with that of Si n- and p-MOSFETs with smooth interface between channel and gate dielectric. The $82\%$ and $96\%$ drive current enhancement are obtained for the n- and p-MOSFETs with the completely smooth interface. However, the enhancement decreases sharply with the increase of interface roughness. With the very rough interface, the drive currents of Ge MOSFETs are even less than that of Si MOSFETs. Moreover, the significant velocity overshoot also has been found in Ge MOSFETs.     

多晶SiGe栅量子阱pMOSFET阈值电压模型

本文基于多晶SiGe栅量子阱SiGe pMOSFET器件物理,考虑沟道反型时自由载流子对器件纵向电势的影响,通过求解泊松方程,建立了p+多晶SiGe栅量子阱沟道pMOS阈值电压和表面寄生沟道开启电压模型.应用MATLAB对该器件模型进行了数值分析,讨论了多晶Si_1-yGe_y栅Ge组分、Si_1-xGe_x量子阱沟道Ge组分、栅氧化层厚度、Si帽层厚度、沟道区掺杂浓度和 关键词： 多晶SiGe栅 寄生沟道 量子阱沟道 阈值电压     

Intraband photoresponse of SiGe quantum dot/quantum well multilayers

In this contribution we study the intravalence band photoexcitation of holes from self-assembled Ge quantum dots (QDs) in Si followed by spatial carrier transfer into SiGe quantum well (QW) channels located close to the Ge dot layers. The structures show maximum response in the important wavelength range 3–5 μm. The influence of the SiGe hole channel on photo- and dark current is studied depending on temperature and the spatial separation of QWs and dot layers. Introduction of the SiGe channel in the active region of the structure increases the photoresponsivity by up to about two orders of magnitude to values of 90 mA/W at T=20 K. The highest response values are obtained for structures with small layer separation (10 nm) that enable efficient transfer of photoexcited holes from QD to QW layers. The results indicate that Si/Ge QD structures with lateral photodetection promise very sensitive large area mid-infrared photodetectors with integrated readout microelectronics in Si technology.     

Intermixing-controlled epitaxy for Si–Ge heterostructure devices

To fabricate high quality SiGe/Si heterostructures, control of intermixing between Si and Ge is essential during crystal growth. This paper describes the recent progress of ‘intermixing-controlled epitaxy’. A combined method of MBE (molecular beam epitaxy) and SPE (solid-phase epitaxy) was developed and used to fabricate a new heterostructure (n-Si_0.8Ge_0.2/Si channel/Si_1 − xGe_xbuffer layer/Si substrate). Observation by TEM demonstrated that the hetero-interface obtained by SPE was atomically flat. This interface provides the ultrahigh mobility of a two-dimensional electron gas (2DEG). In addition, the influence of atomic-hydrogen irradiation during MBE on Ge dispersion in the SiGe mixed crystal is examined. Results indicate that the number of Ge–Ge pairings was decreased by hydrogen irradiation. Such a decrease deformed the local symmetry of the Si–Ge bond from tetrahedral symmetry. As a result, photoluminescence intensity was sucessfully increased.     

SiGe optoelectronic metal-oxide semiconductor field-effect transistor

We propose a novel semiconductor optoelectronic switch that is a fusion of a Ge optical detector and a Si metal-oxide semiconductor field-effect transistor (MOSFET). The device operation is investigated with simulations and experiments. The switch can be fabricated at the nanoscale with extremely low capacitance. This device operates in telecommunication standard wavelengths, hence providing the surrounding Si circuitry with noise immunity from signaling. The Ge gate absorbs light, and the gate photocurrent is amplified at the drain terminal. Experimental current gain of up to 1000x is demonstrated. The device exhibits increased responsivity (approximately 3.5x) and lower off-state current (approximately 4x) compared with traditional detector schemes.     

A novel deep submicron SiGe-on-insulator (SGOI) MOSFET with modified channel band energy for electrical performance improvement

In this paper, we present the unique features exhibited by a novel nanoscale SiGe-on-insulator metal-oxide-semiconductor field-effect transistor (MOSFET) with modified channel band energy. The key idea in this work is to modify the band energy in the channel for improving electrical performances. Graded Ge composition profile is employed in the channel that leads to call the proposed structure as GC-SGOI structure. Using two-dimensional two-carrier simulation we demonstrate that the GC-SGOI structure has higher saturation velocity in comparison with stepped (SC-SGOI) and uniform (UC-SGOI) germanium composition due to the high conduction and valence bands slopes by using graded Ge composition profile. Also, our results show that the GC-SGOI exhibit excellent properties not only higher mobility, drain current and saturation velocity but also hot electron degradation improvement and better reliability. Therefore, refer to the results, the GC-SGOI structure has superior performances in comparison with the SC- and UC-SGOI structures which leads to be a good candidate for VLSI circuits.     

A k·p analytical model for valence band of biaxial strained Ge on（001） Si_1-xGe_x

In this paper,the dispersion relationship is derived by using the k·p method with the help of the perturbation theory,and we obtain the analytical expression in connection with the deformation potential.The calculation of the valence band of the biaxial strained Ge/(001)Si1-xGex is then performed.The results show that the first valence band edge moves up as Ge fraction x decreases,while the second valence band edge moves down.The band structures in the strained Ge/(001)Si 0.4 Ge 0.6 exhibit significant changes with x decreasing in the relaxed Ge along the [0,0,k] and the [k,0,0] directions.Furthermore,we employ a pseudo-potential total energy package(CASTEP) approach to calculate the band structure with the Ge fraction ranging from x = 0.6 to 1.Our analytical results of the splitting energy accord with the CASTEP-extracted results.The quantitative results obtained in this work can provide some theoretical references to the understanding of the strained Ge materials and the conduction channel design related to stress and orientation in the strained Ge pMOSFET.     

硅(001)图形衬底上锗硅纳米线的定位生长

纳米线的定位生长是实现纳米线量子器件寻址和集成的前提.结合自上而下的纳米加工和自下而上的自组装技术,通过分子束外延生长方法,在具有周期性凹槽结构的硅(001)图形衬底上首先低温生长硅锗薄膜然后升温退火,实现了有序锗硅纳米线在凹槽中的定位生长,锗硅纳米线的表面晶面为(105)晶面.详细研究了退火温度、硅锗的比例及图形周期对纳米线形成与否,以及纳米线尺寸的影响.     

锗/硅异质纳米结构中空穴存储特性研究

对p沟道锗/硅异质纳米结构存储器空穴隧穿的物理过程作了详细的分析，并对器件的擦写和保留时间特性进行了数值模拟.研究结果表明：由于异质纳米结构的台阶状隧穿势垒和较高价带带边差的影响，与传统的硅纳米结构存储器和n沟道锗/硅异质纳米结构存储器相比，当前器件的保留时间分别提高到10⁸和10⁵s以上，同时器件的擦写时间特性基本保持不变.这种存储器结构单元有效地解决了快速擦写编程和长久存储之间的矛盾，极大地提高了器件的存储性能. 关键词： 锗/硅 纳米结构 存储器 空穴存储 数值模拟     

Charge transfer in the atomic structure of Ge (1 0 5)

The atomic structure and charge transfer on the Ge (1 0 5) surface formed on Si substrates are studied using scanning tunneling microscopy and spectroscopy (STM and STS). The bias-dependent STM images of the whole Ge (1 0 5) facets formed on a Ge “hut” structure on Si (0 0 1) are observed, which are well explained by the recently confirmed structure model. The local surface density of states on the Ge (1 0 5) surface is measured by STS. The localization of the electronic states expected from charge transfer mechanism is observed in the dI/dV spectra. The surface band gap is estimated as 0.8-0.9 eV, which is even wider than the bulk bandgap of Ge, indicating the strong charge transfer effect to make the dangling bonds stable. The shape of normalized tunnel conductance agrees with the theoretical band structure published recently by Hashimoto et al.     

太赫兹互补金属氧化物半导体场效应管探测器理论模型中扩散效应研究

针对基于经典动力学理论传统模型中忽略扩散效应的问题,通过对基于玻尔兹曼理论的场效应管传输线模型的理论分析,建立了包含扩散效应的太赫兹互补金属氧化物半导体(CMOS)场效应管探测器理论模型,研究扩散效应对场效应管电导及响应度的影响.同时,将此模型与忽略了扩散效应的传统模型进行了对比仿真模拟,给出了两种模型下的电流响应度随温度及频率变化的差别.依据仿真结果,并结合3σ原则明确了场效应管传输线模型中扩散部分省略的依据和条件.研究结果表明:扩散部分引起的响应度差异大小主要由场效应管的工作温度及工作频率决定.其中工作频率起主要作用,温度变化对差异大小影响较为微弱;而对于工作频率而言,当场效应管工作频率小于1 THz时,模型中的扩散部分可以忽略不计;而当工作频率大于1 THz时,扩散部分不可省略,此时场效应管模型需同时包含漂移、散射及扩散三个物理过程.本文的研究结果为太赫兹CMOS场效应管理论模型的精确建立及模拟提供了理论支持.     

纳米尺度下Si/Ge界面应力释放机制的分子动力学研究

采用分子动力学方法研究了纳米尺度下硅(Si)基锗(Ge)结构的Si/Ge界面应力分布特征,以及点缺陷层在应力释放过程中的作用机制.结果表明:在纳米尺度下, Si/Ge界面应力分布曲线与Ge尺寸密切相关,界面应力下降速度与Ge尺寸存在近似的线性递减关系;同时,在Si/Ge界面处增加一个富含空位缺陷的缓冲层,可显著改变Si/Ge界面应力分布,在此基础上对比分析了点缺陷在纯Ge结构内部引起应力变化与缺陷密度的关系,缺陷层的引入和缺陷密度的增加可加速界面应力的释放.参考对Si/Ge界面结构的研究结果,可在Si基纯Ge薄膜生长过程中引入缺陷层,并对其结构进行设计,降低界面应力水平,进而降低界面处产生位错缺陷的概率,提高Si基Ge薄膜质量,这一思想在研究报道的Si基Ge膜低温缓冲层生长方法中初步得到了证实.