Exploiting bounds optimization for the semi-formal verification of analog circuits

This paper proposes a semi-formal methodology for modeling and verification of analog circuits behavioral properties using multivariate optimization techniques. Analog circuit differential models are automatically extracted and their qualitative behavior is computed for interval-valued parameters, inputs and initial conditions. The method has the advantage of guaranteeing the rough enclosure of any possible dynamical behavior of analog circuits. The circuit behavioral properties are then verified on the generated transient response bounds. Experimental results show that the resulting state variable envelopes can be effectively employed for a sound verification of analog circuit properties, in an acceptable run-time.     

Test generation for specification test of analog circuits using efficient test response observation methods

In this paper, a new automated test generation methodology for specification testing of analog circuits using test point selection and efficient analog test response waveform capture methods for enhancing the test accuracy is proposed. The proposed approach co-optimizes the construction of a multi-tone sinusoidal test stimulus and the selection of the best set of test response observation points. For embedded analog circuits, it uses a subsampling-based digitization method compatible with IEEE 1149.1 to accurately digitize the analog test response waveforms. The proposed specification approach uses ‘alternate test’ framework, in which the specifications of the analog circuit-under-test are computed (predicted) using statistical regression models that are constructed based on process variations and corresponding variations of test responses captured from different test observation points. The test generation process and the test point selection process aim to maximize the accuracy of specification prediction. Experimental results validating the proposed specification test approach are presented.     

Multi-gigabit analog equalizers for plastic opticalfibers

Two new CMOS analog continuous-time equalizers for high-speed short-haul optical fiber communications are presented in this paper. The proposed structures compensate the limited bandwidth-length product of 1-mm SI-POF channels (45 MHz·100 m) and have been designed in a standard 0.18-μm CMOS process. The equalizers are aimed for multi-gigabit short-range applications, targeting up to 2 Gb/s through a 50-m SI-POF. The prototypes operate with a single supply voltage of only 1 V and overcome the severe limitations suffered by the widely used degenerated differential pair due to the low supply voltage.     

Optimization-based multifrequency test generation for analog circuits

A robust test set for analog circuits has to detect faults under maximal masking effects due to variations of circuit parameters in their tolerance box. In this paper we propose an optimization based multifrequency test generation method for detecting parametric faults in linear analog circuits. Given a set of performances and a frequency range, our approach selects the test frequencies that maximize the observability on a circuit performance of a parameter deviation under the worst masking effects of normal variations of the other parameters. Experimental results are provided and validated by HSpice simulations to illustrate the proposed approach.     

A CMOS Analog Cell and its applications in analog signal processing

This paper presents a core cell that can be reconfigured and combined with current mirrors to implement exponential, logarithmic, multiplier, divider and raise-to-power function circuits. The proposed circuit uses CMOS transistors operating in the strong inversion. The proposed circuits has been verified with the 0.8?µm CMOS technology by HSPICE simulations. The simulations results confirm the functionality of the proposed circuits. The proposed circuits paves the way for designing analog signal processors.     

A novel test compression algorithm for analog circuits to decrease production costs

Minimizing the manufacturing test time for ICs is one of the main keys to reducing the product cost. We introduce a methodology for automated test compression for electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functional of the transient response. We present a random tree based approach to find the minimum for these computationally hard integrals, which corresponds to the optimally compressed analog test. We demonstrate with an op-amp, VCO, and CMOS inverter that the method consistently reduces the length of each test by an average of 93%. Our technology can compress tests in the presence of process variation and utilize parallel processing to speed up the compression algorithm.     

Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies

The conventional practice for testing analog or RF integrated circuits is specification-based testing, which relies on the direct measurement of the circuit performance parameters. This approach offers good test quality but at the price of extremely high testing costs. In order to reduce test costs, a promising approach, called indirect or alternate testing has been proposed. Its basic principle consists in using the correlation between the conventional analog/RF performances and some low-cost measurements, called Indirect Measurements (IMs), in order to estimate the analog/RF parameters without measuring them directly. In this paper, we perform efficiency evaluation of this strategy, and in particular we perform a comparative analysis of different IM selection strategies in order to define efficient alternate testing implementation. Efficiency is evaluated in terms of model accuracy by using classical metrics such as average and maximal prediction errors, and in terms of prediction reliability by introducing a new metric called Failing Prediction Rate (FPR). Results are illustrated on two case studies for which we have experimental test data.     

On minimal set of test nodes for fault dictionary of analog circuit fault diagnosis

A method is proposed to obtain a minimal set of test nodes of an analog circuit for isolating all faulty conditions in the fault dictionary approach. Relevant theorem along with the proof is also given. Proposed method is extremely fast. This method is illustrated with an active filter circuit example.     

Stochastic-based placement template generator for analog IC layout-aware synthesis

In this paper, a methodology for automatic generation of placement templates for analog integrated circuit design targeted to state-of-the-art optimization-based layout-aware circuit-sizing flows, is proposed. The multi-objective optimization-based placement template generator inputs a Pareto set of sizing solutions and outputs a set of optimal sizing-independent non-slicing B*-tree floorplan representations, i.e., placement templates. Those templates fit the current state of the optimization process and are used within the layout-aware synthesis methodology to generate the floorplan of the following candidate solutions. This innovative methodology combines the advantages of template-based placement approaches, due to its fast packing, with the optimization-based ones, presenting floorplan solutions with improved compactability through the complete evolution of the Pareto set, completely eliminating the template setup effort. Moreover, as the placement template generator runs in parallel with the layout-aware loop, it has no impact on the overall execution time. Experimental results show that the proposed methodology outperforms state-of-the-art multi-template layout-aware synthesis approaches by achieving smaller placement areas for the same performances earlier in the optimization, and further, with a strongly reduced setup effort.     

Fuzzy particle swarm algorithm for function optimization

在传统粒子群算法的基础上运用模糊规则表加入了新的扰动因子,提出了一种新的算法--模糊粒子群算法。算法结合了模糊控制器中输入输出的模糊化处理和粒子群寻优的特点,为实际问题提供了新的解决手段。将模糊粒子群算法应用于函数优化的问题上,通过多组实例数据进行测试,验证表明了本算法具有良好的有效性和鲁棒性。     

Two-stage fuzzy inference system for symbolic simplification of analog circuits

This paper presents a knowledge-based fuzzy approach to symbolic circuit simplification in an effort to imitate human reasoning and knowledge of circuit designer experts. The fuzzy approach differs from the conventional simplification techniques in that it can efficiently combine different input variables to obtain optimal simplified expressions. Additionally, this method was chosen due to its adjustability and interpretability, as well as its ability to manage very complex symbolic expressions. The proposed algorithm uses fuzzy logic to simplify the symbolic circuit transfer functions in two stages. In the first stage, a fuzzy system is applied to directly eliminate nonessential circuit components, resulting simplified circuit topology which also yields simpler transfer function. In the second stage, another fuzzy system is used to further simplify the symbolic transfer function from the already simplified circuit, such that deeper insight into the circuit behavior can be obtained. Symbolic and numerical results show that the fuzzy approach outperforms the conventional techniques in terms of accuracy, expression complexity, and CPU running time.     

Verification and revision of the power-down mode for hierarchical analog circuits

Specialized power-down circuitry can switch off an analog circuit when not required for system operation. When interconnecting sub-circuits with power-down functionality, new design errors, i.e. short-circuit paths, floating nodes and asymmetrical voltages at matched structures, may emerge in the power-down mode of the resulting hierarchical circuit. This paper presents a new method for the verification of the power-down mode of hierarchical analog circuits. In contrast to flat verification approaches, intermediate results are reused during computation. The obtained verification results can be used to revise and correct detected errors. Experimental results for a high input impedance differential amplifier are given.     

Length matching in detailed routing for analog and mixed signal circuits

Heterogeneous integration in modern System-On-Chips (SOCs) drives the design automation process for analog and mixed signal circuit components, where matching constraints for certain analog signals are critical for correct functionality. This paper presents a detailed routing solution for analog nets with the single-layer length matching constraint called LEMAR, i.e., a single-layer LEngth MAtching Router.     

Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications

We present in this work an analysis of the low temperature operation of Graded-Channel fully depleted Silicon-On-Insulator (SOI) nMOSFETs for analog applications, in the range of 100-300 K. This analysis is supported by a comparison between the results obtained by two-dimensional numerical simulations and measurements in the whole temperature range under study. The Graded-Channel transistor presents higher Early voltage if compared to the conventional fully depleted SOI nMOSFET, without degrading the transconductance over drain current, at all studied temperatures, leading to a gain larger than 20 dB compared to the conventional SOI. The resulting higher gain lies in the improvement of the electric field distribution and impact ionization rate by the graded-channel structure.     

Localization of temperature sensitive areas on analog circuits

We introduce a novel easy to apply method to detect critical temperature sensitive areas on analog circuits. Our method is based on heat diffusion on a silicon micro-chip: the corners of a temperature sensitive micro-chip are heated up directly by ESD diodes or infrared laser light. This heat stimulus at the corners results in an inhomogeneous temperature distribution. Thus, the temperature is a function in time and space. The elapsed time to change the chip status from “fail” to “pass” as a reaction to the heat stimulus correlates with the distance to the heat source. This correlation is extracted from COMSOL simulations and experimental results. A numerical program based on that correlation succeeded in localization of the temperature sensitive chip module.Micro-chips affected by corner MOSFETs in the subthreshold regime are used to demonstrate our method.     

Design methodology for configurable analog to digital conversion using support vector machines

We apply a support vector machine (SVM) classifier to the design of analog to digital converters. Each output bit of the converter is the output of a binary classifier, which is a nonlinear SVM. The classifier effectively learns a folding characteristic for each bit, which is realized as the weighted sum of a set of kernel functions. In our proposal, the kernel does not need to be symmetric or positive definite, unlike in the case of a conventional SVM. This makes the approach more amenable to VLSI design, where such constraints are hard to satisfy. The SVM uses a set of binary weights, which allows the folding characteristics to be digitally corrected after fabrication. This facility is of considerable value in analog design in a deep sub micron era, where simulation models do not adequately capture the behavior of devices, or their variations. The proposed methodology reduces design time, can be automated and calibrated for process variations and ageing, by changing a set of digital scaling coefficients.     

A new hybrid algorithm for analog ICs optimization based on the shrinking circles technique

This paper presents a novel technique named the Shrinking Circles to enhance the performance of optimization algorithms embedded in automated sizing tools of analog ICs. This technique creates a balance between the exploration and exploitation capabilities when the optimization algorithm is converging to a possible optimum point. With the help of the shrinking circles concept, we upgrade a hybridization version of Gravitational Search Algorithm with Particle Swarm Optimization (Advanced GSA_PSO). Accordingly, a developed tool for the automation of analog ICs sizing is proposed. The performance of this tool is evaluated by two cases: minimizing the power consumption of a two-stage CMOS op-amp and simultaneous minimizing the circuit area and power consumption of a folded-cascode op-amp. In this paper, the corners analysis is also incorporated into the proposed circuit sizing tool based on a straightforward procedure by which this tool not only can obtain the solutions being robust against process, voltage, and temperature (PVT) variations, but also it alleviates the computational burden. Comparisons with available methods show that the proposed tool performs much better in terms of efficiency.     

Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements

The greedy specification testing remains mandatory for analog and radio frequency (RF) integrated circuits because of the accuracy of the sorting based on these measurements. Unfortunately, to be implemented, this kind of testing method often incurs very high costs (expensive instruments, long test time…). A common approach, in the literature, is the so-called indirect/alternate test strategy. This strategy consists in deriving targeted specifications from low-cost Indirect Measurements (IMs). During the industrial test phase, the estimation of regular specifications using IMs is based on a correlation model that has been built previously, during a training phase. Despite the substantial test cost reduction offered by this strategy, its deployment in industry is limited, mainly because of a lack of confidence in the accuracy of estimations made by the correlation model. A solution to increase the confidence in the estimation of specifications using the indirect approach is to implement redundancy in the prediction phase. In this paper, we demonstrate that the redundancy implementation brings more than identifying rare misjudged circuits from a high-correlated model. Indeed redundancy massively increases the accuracy despite of the lack of accurate models that have been assumed in previous implementations of redundant indirect testing. This approach is illustrated on a real case study for which we have experimental measurements on a set of 10,000 devices.     

Power efficient asynchronous multiplexer for X-ray sensors in medical imaging analog front-end electronics

This paper presents a new power efficient asynchronous multiplexer (MUX) for application in analog front-end electronics (AFE) used in X-ray medical imaging systems. Contrary to typical synchronous MUXes that have to be controlled by a clock, this circuit features a simple structure, as the clock is not required. The circuit dissipates power only while detecting the active signals and then automatically turns back to the power down mode. Medical imaging systems usually consist of several dozen to even several hundreds of channels that operate asynchronously. The proposed MUX enables an unambiguous choice of the active channel. In case of two or more channels that become active at the same time the MUX serializes the reading out data from particular channels. This characteristic leads to 100% effectiveness in data processing and no impulses’ loss. The proposed MUX together with an experimental readout ASIC has been implemented in the CMOS 0.18 μm process and occupies 1100 μm²/channel area. It works properly in a wide range of the voltage supply in between 0.8 and 1.8 V. Energy consumed during the detection of one active channel is below 1 pJ, while the detection time is about 1 ns.