结终端采用JTE保护技术的4H-SiC PiN二极管模拟和研制

利用二维器件模拟软件ISE-TCAD 10.0,对结终端采用结扩展保护技术的4H-SiC PiN二极管平面器件进行反向耐压特性的模拟,并获得许多有价值的模拟数据.依据所得的模拟数据进行此种二极管器件的研制.实验测试表明,此二极管的模拟优化数据与实验测试的结果一致性较好,4H-SiC PiN二极管所测得到的反向电压达1600 V,该反向耐压数值达到理想平面结的击穿耐压90%以上.     

Research on high-voltage 4H-SiC P-i-N diode with planar edge junction termination techniques

The planar edge termination techniques of junction termination extension (JTE) and offset field plates and field-limiting rings for the 4H-SiC P-i-N diode were investigated and optimized by using a two-dimensional device simulator ISE-TCAD10.0. By experimental verification, a good consistency between simulation and experiment can be observed. The results show that the reverse breakdown voltage for the 4H-SiC P-i-N diode with optimized JTE edge termination can accomplish near ideal breakdown voltage and much lower leakage current. The breakdown voltage can be near 1650 V, which achieves more than 90 percent of ideal parallel plane junction breakdown voltage and the leakage current density can be near 3 × 10-5 A/cm2.     

Experimental and numerical analyses of high voltage 4H-SiC junction barrier Schottky rectifiers with linearly graded field limiting ring

This paper describes the successful fabrication of 4H-SiC junction barrier Schottky(JBS) rectifiers with a linearly graded field limiting ring(LG-FLR). Linearly variable ring spacings for the FLR termination are applied to improve the blocking voltage by reducing the peak surface electric field at the edge termination region, which acts like a variable lateral doping profile resulting in a gradual field distribution. The experimental results demonstrate a breakdown voltage of 5 kV at the reverse leakage current density of 2 mA/cm2(about 80% of the theoretical value). Detailed numerical simulations show that the proposed termination structure provides a uniform electric field profile compared to the conventional FLR termination, which is responsible for 45% improvement in the reverse blocking voltage despite a 3.7% longer total termination length.     

套刻偏差对4H-SiC 浮动结结势垒肖特基二极管的影响研究

4H-SiC浮动结结势垒肖特基二极管与常规结势垒肖特基二极管相比在 相同的导通电阻条件下具有更高的击穿电压. 由p⁺埋层形成的浮动结与主结p⁺区 之间的套刻对准是实现该结构的一项关键技术. 二维模拟软件ISE的模拟结果表明, 套刻偏差的存在会明显影响器件的击穿特性, 随着偏差的增大击穿电压减小. 尽管主结和埋层的交错结构与对准结构具有相似的击穿特性, 但是当正向电压大于2 V后, 交错结构的串联电阻更大.     

Influence of geometrical parameters on the behaviour of SiC merged PiN Schottky rectifiers with junction termination extension

This paper investigates the behaviours of 4H--SiC merged PiN Schottky (MPS) rectifiers with junction termination extension (JTE) by extensive numerical simulations. The simulated results show that the present model matches the experimental data very well. The influences of the JTE design parameters such as the doping concentration and length of the JTE on the breakdown characteristics are discussed in detail. Then the temperature sensitivity of the forward behaviour is studied in terms of the different designs of 4H--SiC MPS with JTE, which provides a particularly useful guideline for the optimal design of MPS rectifiers with JTE.     

4H-SiC pn结型二极管击穿特性中隧穿效应影响的模拟研究

基于4H-SiC材料特性，建立了4H-SiC pn结型二极管的击穿模型.该模型在碳化硅器件中引入 雪崩倍增效应和隧穿效应.利用该模型，分析了隧穿效应对器件击穿特性的影响；解释了不 同的温度和掺杂条件下，器件的击穿机理.该模型较好地反映了实际器件的击穿特性. 关键词： 4H-SiC 二极管 击穿特性 隧穿效应 碰撞离化 模型     

A 4H-SiC merged P-I-N Schottky with floating back-to-back diode

A novel 4H-SiC merged P-I-N Schottky (MPS) with floating back-to-back diode (FBD), named FBD-MPS, is proposed and investigated by the Sentaurus technology computer-aided design (TCAD) and analytical model. The FBD features a trench oxide and floating P-shield, which is inserted between the P+/N-(PN) junction and Schottky junction to eliminate the shorted anode effect. The FBD is formed by the N-drift/P-shield/N-drift and it separates the PN and Schottky active region independently. The FBD reduces not only the V_turn to suppress the snapback effect but also the V_on at bipolar operation. The results show that the snapback can be completely eliminated, and the maximum electric field (E_max) is shifted from the Schottky junction to the FBD in the breakdown state.     

用边界元素法模拟FP-JTE终端结构

提出了一种无须进行电离积分的用于高压结终端模拟的边界元素法,分析了界面电荷对FP-JTE终端结构击穿电压的影响,结果表明击穿电压几乎与界面电荷浓度呈线性关系,场板可减弱界面电荷对击穿电压的影响。     

Fabrication of ZnO nanorod-based p–n heterojunction on SiC substrate

Due to the special properties of ZnO and numerous envisaged areas of application of its nanostructures, much effort has been made in fabricating ZnO nanostructures. The next challenging step seems to be the processing and hence realisation of devices based on the nanostructure. We have grown ZnO nanorods of high crystal quality and good optical properties on 6H-SiC and 4H-SiC substrates. Considering the p–n junction as a basis for electronic and optoelectronic devices, we realised ohmic contacts on p-type 4H-SiC and fabricated ZnO nanorod-based p–n heterojunctions with the p-type 4H-SiC serving as the hole-conducting region. Nanorod-based p–n diodes with a turn-on voltage of 1.8 V and relatively large reverse-bias breakdown voltage were obtained, thus suggesting both the possibility of ZnO nanorod-based ultraviolet photodetectors and light-emitting devices, and the miniaturisation of device scales.     

Experimental and numerical analysis of the multi-recessed gate structure for microwave silicon carbide power MESFETs

This paper reports that multi-recessed gate 4H-SiC MESFETs (metal semiconductor filed effect transistors) with a gate periphery of 5-mm are fabricated and characterized. The multi-recessed region under the gate terminal is applied to improve the gate--drain breakdown voltage and to alleviate the trapping induced instabilities by moving the current path away from the surface of the device. The experimental results demonstrate that microwave output power density, power gain and power-added efficiency for multi-finger 5-mm gate periphery SiC MESFETs with multi-recessed gate structure are about 29%, 1.1dB and 7% higher than those of conventional devices fabricated in this work using the same process.     

Study of 4H-SiC junction barrier Schottky diode using field guard ring termination

This paper reports that the 4H-SiC Schottky barrier diode, PiN diode and junction barrier Schottky diode terminated by field guard rings are designed, fabricated and characterised. The measurements for forward and reverse characteristics have been done, and by comparison with each other, it shows that junction barrier Schottky diode has a lower reverse current density than that of the Schottky barrier diode and a higher forward drop than that of the PiN diode. High-temperature annealing is presented in this paper as well to figure out an optimised processing. The barrier height of 0.79 eV is formed with Ti in this work, the forward drop for the Schottky diode is 2.1 V, with an ideality factor of 3.2, and junction barrier Schottky diode with blocking voltage higher than 400 V was achieved by using field guard ring termination.     

Design of vertical diamond Schottky barrier diode with junction terminal extension structure by using the n-Ga2O3/p-diamond heterojunction

A novel junction terminal extension structure is proposed for vertical diamond Schottky barrier diodes (SBDs) by using an n-Ga₂O₃/p-diamond heterojunction. The depletion region of the heterojunction suppresses part of the forward current conduction path, which slightly increases the on-resistance. On the other hand, the reverse breakdown voltage is enhanced obviously because of attenuated electric field crowding. By optimizing the doping concentration, length, and depth of n-Ga₂O₃, the trade-off between on-resistance and breakdown voltage with a high Baliga figure of merit (FOM) value is realized through Silvaco technology computer-aided design simulation. In addition, the effect of the work functions of the Schottky electrodes is evaluated. The results are beneficial to realizing a high-performance vertical diamond SBD.     

Simulation research on offset field-plate used as edge termination in 4H-SiC merged PiN-Schottky diodes

A new structure of 4H--silicon carbide (SiC) merged PiN-Schottky (MPS) diodes with offset field-plate (FP) as edge termination is developed. To understand the influences of 4H--SiC MPS diodes with offset FP on the characteristics, simulations have been done by using ISE TCAD. Related factors of offset FP have been studied as well to optimise the reverse characteristics of 4H--SiC MPS diodes. The simulation results show that the device using offset FP can create a higher blocking voltage under reverse bias as compared with that using field guard rings. Besides, the offset FP does not cause any extra steps in the manufacture of MPS diodes.     

Study and optimal simulation of 4H-SiC floating junction Schottky barrier diodes’ structures and electric properties

This paper stuides the structures of 4H-SiC floating junction Schottky barrier diodes. Some structure parameters of devices are optimized with commercial simulator based on forward and reverse electrical characteristics. Compared with conventional power Schottky barrier diodes, the devices are featured by highly doped drift region and embedded floating junction layers, which can ensure high breakdown voltage while keeping lower specific on-state resistance, and solve the contradiction between forward voltage drop and breakdown voltage. The simulation results show that with optimized structure parameter, the breakdown voltage can reach 4.36 kV and the specific on-resistance is 5.8 mΩ·cm2 when the Baliga figure of merit value of 13.1 GW/cm2 is achieved.     

Nanoscale avalanche photodiode with self-quenching and ultrahigh ultraviolet/visible rejection ratio

A 4H-SiC based separate-absorption-multiplication (SAM) avalanche photodiode with a nanoscale multiplication region and a bulk absorption region is proposed and its optoelectronic performance is modeled. The results show that the avalanche breakdown voltage of the device is found to be dependent on the illumination condition. This is attributed to the existence of an illumination-dependent hole potential well in the upper center of the absorption region. Based on the illumination-dependence of avalanche breakdown voltage, a self-quenching and an ultrahigh UV/visible rejection ratio have been realized in this structure.     

电荷失配对SiC半超结垂直双扩散金属氧化物半导体场效应管击穿电压的影响

Si C半超结垂直双扩散金属氧化物半导体场效应管(VDMOSFET)相对于常规VDMOSFET在相同导通电阻下具有更大击穿电压.在N型外延层上进行离子注入形成半超结结构中的P柱是制造Si C半超结VDMOSFET的关键工艺.本文通过二维数值仿真研究了离子注入导致的电荷失配对4H-Si C超结和半超结VDMOSFET击穿电压的影响,在电荷失配程度为30%时出现半超结VDMOSFET的最大击穿电压.在本文的器件参数下,P柱浓度偏差导致击穿电压降低15%时,半超结VDMOSFET柱区浓度偏差范围相对于超结VDMOSFET可提高69.5%,这意味着半超结VDMOSFET对柱区离子注入的控制要求更低,工艺制造难度更低.     

Modeling of 4H--SiC multi-floating-junction Schottky barrier diode

This paper develops a new and easy to implement analytical model for the specific on-resistance and electric field distribution along the critical path for 4H-SiC multi-floating junction Schottky barrier diode. Considering the charge compensation effects by the multilayer of buried opposite doped regions, it improves the breakdown voltage a lot in comparison with conventional one with the same on-resistance. The forward resistance of the floating junction Schottky barrier diode consists of several components and the electric field can be understood with superposition concept, both are consistent with MEDICI simulation results. Moreover, device parameters are optimized and the analyses show that in comparison with one layer floating junction, multilayer of floating junction layer is an effective way to increase the device performance when specific resistance and the breakdown voltage are traded off. The results show that the specific resistance increases 3.2 mΩ·cm 2 and breakdown voltage increases 422 V with an additional floating junction for the given structure.     

Injection modulation of p~+-n emitter junction in 4H-SiC light triggered thyristor by double-deck thin n-base

To overcome hole-injection limitation of p~+-n emitter junction in 4H-SiC light triggered thyristor, a novel highvoltage 4H-SiC light triggered thyristor with double-deck thin n-base structure is proposed and demonstrated by twodimensional numerical simulations. In this new structure, the conventional thin n-base is split to double-deck. The holeinjection of p~+-n emitter junction is modulated by modulating the doping concentration and thickness of upper-deck thin nbase. With double-deck thin n-base, the current gain coefficient of the top pnp transistor in 4H-SiC light triggered thyristor is enhanced. As a result, the triggering light intensity and the turn-on delay time of 4H-SiC light triggered thyristor are both reduced. The simulation results show that the proposed 10-kV 4H-SiC light triggered thyristor is able to be triggered on by500-m W/cm~2 ultraviolet light pulse. Meanwhile, the turn-on delay time of the proposed thyristor is reduced to 337 ns.     

A novel 4H-SiC lateral bipolar junction transistor structure with high voltage and high current gain

In this paper, a novel structure of a 4H-SiC lateral bipolar junction transistor (LBJT) with a base field plate and double RESURF in the drift region is presented. Collector-base junction depletion extension in the base region is restricted by the base field plate. Thin base as well as low base doping of the LBJT therefore can be achieved under the condition of avalanche breakdown. Simulation results show that thin base of 0.32 μm and base doping of 3×1017 cm-3 are obtained, and corresponding current gain is as high as 247 with avalanche breakdown voltage of 3309 V when the drift region length is 30 μm. Besides, an investigation of a 4H-SiC vertical BJT (VBJT) with comparable breakdown voltage (3357 V) shows that the minimum base width of 0.25 μm and base doping as high as 8×1017 cm-3 contribute to a maximum current gain of only 128.     

栅漏间表面外延层对4H-SiC功率MESFET击穿 特性的改善机理与结构优化

本文提出了一种带栅漏间表面p型外延层的新型MESFET结构并整合了能精确描述4H-SiC MESFET工作机理的数值模型,模型综合考虑了高场载流子饱和、雪崩碰撞离化以及电场调制等效应. 利用所建模型分析了表面外延层对器件沟道表面电场分布的改善作用,并采用突变结近似法对p型外延层参数与器件输出电流(I_ds)和击穿电压(V_B)的关系进行了研究.结果表明,通过在常规MESFET漏端处引入新的电场峰来降低栅极边缘的强电场峰并在栅漏之间的沟道表面引入p-n结内建电场进一步降低电场峰值,改善了表面电场沿电流方向的分布.通过与常规结构以及场板结构SiC MESFET的特性对比表明,本文提出的结构可以明显改善SiC MESFET的功率特性.此外,针对文中给定的器件结构,获得了优化的设计方案,选择p型外延层厚度为0.12 μupm,掺杂浓度为5× 10¹⁵ cm^-3,可使器件的V_B提高33%而保持I_ds基本不变.