Degradation of gate-recessed MOS-HEMTs and conventional HEMTs under DC electrical stress

The performance degradation of gate-recessed metal–oxide–semiconductor high electron mobility transistor(MOSHEMT) is compared with that of conventional high electron mobility transistor(HEMT) under direct current(DC) stress,and the degradation mechanism is studied. Under the channel hot electron injection stress, the degradation of gate-recessed MOS-HEMT is more serious than that of conventional HEMT devices due to the combined effect of traps in the barrier layer, and that under the gate dielectric of the device. The threshold voltage of conventional HEMT shows a reduction under the gate electron injection stress, which is caused by the barrier layer traps trapping the injected electrons and releasing them into the channel. However, because of defects under gate dielectrics which can trap the electrons injected from gate and deplete part of the channel, the threshold voltage of gate-recessed MOS-HEMT first increases and then decreases as the conventional HEMT. The saturation phenomenon of threshold voltage degradation under high field stress verifies the existence of threshold voltage reduction effect caused by gate electron injection.     

Effect of heavy ion irradiation on the interface traps of AlGaN/GaN high electron mobility transistors

AlGaN/GaN high electron mobility transistors (HEMTs) were irradiated with heavy ions at various fluences. After irradiation by 2.1 GeV¹⁸¹ Ta³²⁺ ions, the electrical characteristics of the devices significantly decreased. The threshold voltage shifted positively by approximately 25% and the saturation currents decreased by approximately 14%. Defects were induced in the band gap and the interface between the gate and barrier acted as tunneling sites, which increased the gate current tunneling probability. According to the pulsed output characteristics, the amount of current collapse significantly increased and more surface state traps were introduced after heavy ion irradiation. The time constants of the induced surface traps were mainly less than 10 μs.     

AlGaN/GaN高电子迁移率晶体管肖特基高温退火机理研究

在不同应力条件下,研究了AlGaN/GaN高电子迁移率晶体管高温退火前后的电流崩塌、栅泄漏电流以及击穿电压的变化.结果表明,AlGaN/GaN高电子迁移率晶体管通过肖特基高温退火以后,器件的特性得到很大的改善.利用电镜扫描(SEM)和X射线光电子能谱(XPS)对高温退火前、后的肖特基接触界面进行深入分析,发现器件经过高温退火后,Ni和AlGaN层之间介质的去除,并且AlGaN材料表面附近的陷阱减少,使得肖特基有效势垒提高,从而提高器件的电学特性. 关键词： AlGaN/GaN高电子迁移率晶体管 肖特基接触 界面陷阱     

电压应力下超薄栅氧化层n-MOSFET的击穿特性

研究了90nm工艺下栅氧化层厚度为1.4nm的n-MOSFET的击穿特性，包括V-ramp(斜坡电压)应力下器件栅电流模型和CVS(恒定电压应力)下的TDDB(经时击穿)特性，分析了电压应力下器件的失效和退化机理.发现器件的栅电流不是由单一的隧穿引起，同时还有电子的翻越和渗透.在电压应力下，SiO₂中形成的缺陷不仅降低了SiO₂的势垒高度，而且等效减小了SiO₂的厚度(势垒宽度).另外，每一个缺陷都会形成一个导电通道，这些导电通道的形成增大了栅电流，导致器件性能的退化，同时栅击穿时间变长. 关键词： 超薄栅氧化层 斜坡电压 经时击穿 渗透     

Dispersion effect on the current voltage characteristic of AlGaN/GaN high electron mobility transistors

The current voltage (IV) characteristics are greatly influenced by the dispersion effects in AlGaN/GaN high electron mobility transistors. The direct current (DC) IV and pulsed IV measurements are performed to give a deep investigation into the dispersion effects, which are mainly related to the trap and self-heating mechanisms. The results show that traps play an important role in the kink effects, and high stress can introduce more traps and defects in the device. With the help of the pulsed IV measurements, the trapping effects and self-heating effects can be separated. The impact of time constants on the dispersion effects is also discussed. In order to achieve an accurate static DC IV measurement, the steady state of the bias points must be considered carefully to avoid the dispersion effects.     

High temperature characteristics of bilayer epitaxial graphene field-effect transistors on SiC Substrate

In this paper,high temperature direct current(DC) performance of bilayer epitaxial graphene device on SiC substrate is studied in a temperature range from 25℃ to 200℃.At a gate voltage of-8 V(far from Dirac point),the drainsource current decreases obviously with increasing temperature,but it has little change at a gate bias of +8 V(near Dirac point).The competing interactions between scattering and thermal activation are responsible for the different reduction tendencies.Four different kinds of scatterings are taken into account to qualitatively analyze the carrier mobility under different temperatures.The devices exhibit almost unchanged DC performances after high temperature measurements at 200℃ for 5 hours in air ambience,demonstrating the high thermal stabilities of the bilayer epitaxial graphene devices.     

Effect of overdrive voltage on PBTI trapping behavior in GaN MIS-HEMT with LPCVD SiN_x gate dielectric

The effect of high overdrive voltage on the positive bias temperature instability(PBTI)trapping behavior is investigated for GaN metal–insulator–semiconductor high electron mobility transistor(MIS-HEMT)with LPCVD-SiNx gate dielectric.A higher overdrive voltage is more effective to accelerate the electrons trapping process,resulting in a unique trapping behavior,i.e.,a larger threshold voltage shift with a weaker time dependence and a weaker temperature dependence.Combining the degradation of electrical parameters with the frequency–conductance measurements,the unique trapping behavior is ascribed to the defect energy profile inside the gate dielectric changing with stress time,new interface/border traps with a broad distribution above the channel Fermi level are introduced by high overdrive voltage.     

AlGaN/GaN 高电子迁移率晶体管漏电流退化机理研究

本文首先制备了与AlGaN/GaN高电子迁移率晶体管 (HEMT) 结构与特性等效的AlGaN/GaN异质结肖特基二极管, 采用步进应力测试比较了不同栅压下器件漏电流的变化情况, 然后基于电流-电压和电容-电压测试验证了退化前后漏电流的传输机理, 并使用失效分析技术光发射显微镜 (EMMI) 观测器件表面的光发射, 研究了漏电流的时间依赖退化机理. 实验结果表明: 在栅压高于某临界值后, 器件漏电流随时间开始增加, 同时伴有较大的噪声. 将极化电场引入电流与电场的依赖关系后, 器件退化前后的 log(I_FT/E)与√E 都遵循良好的线性关系, 表明漏电流均由电子Frenkel-Poole (FP) 发射主导. 退化后 log(I_FT/E)与√E 曲线斜率的减小, 以及利用EMMI在栅边缘直接观察到了与缺陷存在对应关系的“热点”, 证明了漏电流退化的机理是: 高电场在AlGaN层中诱发了新的缺陷, 而缺陷密度的增加导致了FP发射电流I_FT的增加. 关键词： AlGaN/GaN 高电子迁移率晶体管 漏电流 退化机理     

增强型AlGaN/GaN高电子迁移率晶体管高温退火研究

深入研究了两种增强型AlGaN/GaN高电子迁移率晶体管(HEMT)高温退火前后的直流特性变化.槽栅增强型AlGaN/GaN HEMT在500 ℃ N₂中退火5 min后,阈值电压由0.12 V正向移动到0.57 V,器件Schottky反向栅漏电流减小一个数量级.F注入增强型AlGaN/GaN HEMT在 400 ℃ N₂中退火2 min后,器件阈值电压由0.23 V负向移动到-0.69 V,栅泄漏电流明显增大.槽栅增强型器件退火过程中Schottky有效势垒     

基于脉冲方法的超短栅长GaN基高电子迁移率晶体管陷阱效应机理

陷阱效应导致的电流崩塌是制约GaN基微波功率电子器件性能提高的一个重要因素,研究深能级陷阱行为对材料生长和器件开发具有非常重要的意义.随着器件频率的提升,器件尺寸不断缩小,对小尺寸器件中深能级陷阱的表征变得越发困难.本文制备了超短栅长（L_g=80 nm）的AlGaN/GaN金属氧化物半导体高电子迁移率晶体管（MOSHEMT）,并基于脉冲I-V测试和二维数值瞬态仿真对器件的动态特性进行了深入研究,分析了深能级陷阱对AlGaN/GaN MOSHEMT器件动态特性的影响以及相关陷阱效应的内在物理机制.结果表明,AlGaN/GaN MOSHEMT器件的电流崩塌随着栅极静态偏置电压的增加呈非单调变化趋势,这是由栅漏电注入和热电子注入两种陷阱机制共同作用的结果.根据研究结果推断,可通过改善栅介质的质量以减小栅漏电或提高外延材料质量以减少缺陷密度等措施达到抑制陷阱效应的目的,从而进一步抑制电流崩塌.     

Snapback应力引起的90 nm NMOSFET's栅氧化层损伤研究

实验结果发现突发击穿(snapback)，偏置下雪崩热空穴注入NMOSFET栅氧化层，产生界面态，同时空穴会陷落在氧化层中.由于栅氧化层很薄，陷落的空穴会与隧穿入氧化层中的电子复合形成大量中性电子陷阱，使得栅隧穿电流不断增大.这些氧化层电子陷阱俘获电子后带负电，引起阈值电压增大、亚阈值电流减小.关态漏泄漏电流的退化分两个阶段：第一阶段亚阈值电流是主要成分，第二阶段栅电流是主要成分.在预加热电子(HE)应力后，HE产生的界面陷阱在snapback应力期间可以屏蔽雪崩热空穴注入栅氧化层，使器件snapback开态和关态特性退化变小. 关键词： 突发击穿 软击穿 应力引起的泄漏电流 热电子应力     

Investigating the effects of the interface defects on the gate leakage current in MOSFETs

The effects of the interface defects on the gate leakage current have been numerically modeled. The results demonstrate that the shallow and deep traps have different effects on the dependence relation of the stress-induced leakage current on the oxide electric field in the regime of direct tunneling, whereas both traps keep the same dependence relation in the regime of Fowler-Nordheim tunneling. The results also shows that the stress-induced leakage current will be the largest at a moderate oxide voltage for the electron interface traps but it increases with the decreasing oxide voltage for the hole interface traps. The results illustrate that the stress-induced leakage current strongly depends on the location of the electron interface traps but it weakly depends on the location of the hole interface traps. The increase in the gate leakage current caused by the electron interface traps can predict the increase, then decrease in the stress-induced leakage current, with decreasing oxide thickness, which is observed experimentally. And the electron interface trap level will have a large effect on the peak height and position.     

Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and V_h degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.     

Non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor with high breakdown voltage

A non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor(quasi-EDHEMT) with a thin barrier, high breakdown voltage and good performance of drain induced barrier lowering(DIBL)was presented. Due to the metal organic chemical vapor deposition(MOCVD) grown 9-nm undoped AlGaN barrier, the effect that the gate metal depleted the two-dimensiomal electron gas(2DEG) was greatly impressed. Therefore, the density of carriers in the channel was nearly zero. Hence, the threshold voltage was above 0 V. Quasi-E-DHEMT with 4.1-μm source-to-drain distance, 2.6-μm gate-to-drain distance, and 0.5-μm gate length showed a drain current of 260 mA/mm.The threshold voltage of this device was 0.165 V when the drain voltage was 10 V and the DIBL was 5.26 mV/V. The quasi-E-DHEMT drain leakage current at a drain voltage of 146 V and a gate voltage of-6 V was below 1 mA/mm. This indicated that the hard breakdown voltage was more than 146 V.     

高电子迁移率晶体管微波损伤仿真与实验研究

针对AlGaAs/InGaAs型高电子迁移率晶体管,利用TCAD半导体仿真工具,从器件内部空间电荷密度、电场强度、电流密度和温度分布变化分析出发,研究了从栅极注入1 GHz微波信号时器件内部的损伤过程与机理。研究表明,器件的损伤过程发生在微波信号的正半周,负半周器件处于截止状态;器件内部损伤过程与机理在不同幅值的注入微波信号下是不同的。当注入微波信号幅值较低时,器件内部峰值温度出现在栅极下方靠源极侧栅极与InGaAs沟道间,由于升温时间占整个周期的比例太小,峰值温度很难达到GaAs的熔点;但器件内部雪崩击穿产生的栅极电流比小信号下栅极泄漏电流高4个量级,栅极条在如此大的电流下很容易烧毁熔断。当注入微波信号幅值较高时,在信号正半周的下降阶段,在栅极中间偏漏极下方发生二次击穿,栅极电流出现双峰现象,器件内部峰值温度转移到栅极中间偏漏极下方,峰值温度超过GaAs熔点。利用扫描电子显微镜对微波损伤的高电子迁移率晶体管器件进行表面形貌失效分析,仿真和实验结果符合较好。     

高功率微波作用下高电子迁移率晶体管的损伤机理

本文针对高电子迁移率晶体管在高功率微波注入条件下的损伤过程和机理进行了研究,借助SentaurusTCAD仿真软件建立了晶体管的二维电热模型,并仿真了高功率微波注入下的器件响应.探索了器件内部电流密度、电场强度、温度分布以及端电流随微波作用时间的变化规律.研究结果表明,当幅值为20 V,频率为14.9 GHz的微波信号由栅极注入后,器件正半周电流密度远大于负半周电流密度,而负半周电场强度高于正半周电场.在强电场和大电流的共同作用下,器件内部的升温过程同时发生在信号的正、负半周内.又因栅极下靠近源极侧既是电场最强处,也是电流最密集之处,使得温度峰值出现在该处.最后,对微波信号损伤的高电子迁移率晶体管进行表面形貌失效分析,表明仿真与实验结果符合良好.     

Negative transconductance effect in p-GaN gate AlGaN/GaN HEMTs by traps in unintentionally doped GaN buffer layer

We investigate the negative transconductance effect in p-GaN gate AlGaN/GaN high-electron-mobility transistor(HEMT) associated with traps in the unintentionally doped GaN buffer layer. We find that a negative transconductance effect occurs with increasing the trap concentration and capture cross section when calculating transfer characteristics.The electron tunneling through AlGaN barrier and the reduced electric field discrepancy between drain side and gate side induced by traps are reasonably explained by analyzing the band diagrams, output characteristics, and the electric field strength of the channel of the devices under different trap concentrations and capture cross sections.     

AlGaAs/InGaAs PHEMT栅电流参数退化模型研究

为定量研究在PHEMT栅电流退化过程中, 不同失效机理对应的参数退化时间常数及退化比例, 本文基于退化过程中物理化学反应中反应量浓度与反应速率的关系, 建立了PHEMT栅电流参数退化模型. 利用在线实验的方法获得PHEMT电学参数的退化规律, 分析参数随时间的退化规律, 得到不同时间段内影响栅电流退化的失效机理, 并基于栅电流参数退化模型, 得到了不同的失效机理对应的参数退化时间常数及退化比例. 关键词： PHEMT 栅电流 肖特基接触 退化模型     

γ射线总剂量辐照对单轴应变Si纳米n型金属氧化物半导体场效应晶体管栅隧穿电流的影响

基于γ射线辐照条件下单轴应变Si纳米n型金属氧化物半导体场效应晶体管(NMOSFET)载流子的微观输运机制,揭示了单轴应变Si纳米NMOSFET器件电学特性随总剂量辐照的变化规律,同时基于量子机制建立了小尺寸单轴应变Si NMOSFET在γ射线辐照条件下的栅隧穿电流模型,应用Matlab对该模型进行了数值模拟仿真,探究了总剂量、器件几何结构参数、材料物理参数等对栅隧穿电流的影响.此外,通过实验进行对比,该模型仿真结果和总剂量辐照实验测试结果基本符合,从而验证了模型的可行性.本文所建模型为研究纳米级单轴应变Si NMOSFET应变集成器件可靠性及电路的应用提供了有价值的理论指导与实践基础.     

Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation

The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10¹⁸ cm^-3 and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.