几种CMOS VLSI的低功耗BIST技术

在分析全扫描内建自测试(BIST)较高测试功耗的基础上,总结出几种CMOS VLSI的低功耗BIST技术方案,包括减少待测电路(CUT)输入端的翻转次数、简化线性反馈移位寄存器(LFSR)结构、部分扫描低功耗BIST方法等.分析结果表明,这些方法不但在保证测试覆盖率的条件下,降低了测试平均功耗和峰值功耗,而且综合应用这几种方法将会使系统功耗指标达到最佳.     

基于LFSR优化的BIST低功耗设计

在BIST(内建自测试)过程中,线性反馈移位寄存器作为测试矢量生成器,为保障故障覆盖率,会产生很长的测试矢量,从而消耗了大量功耗.在分析BIST结构和功耗模型的基础上,针对test-per-scan和test-per-clock两大BIST类型,介绍了几种基于LFSR(线性反馈移位寄存器)优化的低功耗BIST测试方法,设计和改进可测性设计电路,研究合理的测试策略和测试矢量生成技术,实现测试低功耗要求.     

大规模集成电路的可测性技术研究

集成电路测试和设计技术是集成电路的主要核心技术，而可测性设计技术是集成电路测试和设计这两大核心技术的复合技术或边缘技术，本文主要介绍了大规模集成电路的可测性设计技术。     

基于LFSR优化的BIST低功耗设计

在BIST(内建自测试)过程中,线性反馈移位寄存器作为测试矢量生成器,为保障故障覆盖率,会产生很长的测试矢量,从而消耗了大量功耗。在分析BIST结构和功耗模型的基础上,针对test-per-scan和test-per-clock两大BIST类型,介绍了几种基于LFSR(线性反馈移位寄存器)优化的低功耗BIST测试方法,设计和改进可测性设计电路,研究合理的测试策略和测试矢量生成技术,实现测试低功耗要求。     

一种低功耗BIST测试产生器方案

低功耗设计呼唤低功耗的测试策略。文章提出了一种在不损失固定型故障覆盖率的前提下降低测试功耗的内建自测试测试产生器方案，该方案在原始线性反馈移位寄存器的基础上添加简单的控制逻辑，对LFSR的输出和时钟进行调整，从而得到了准单输入跳变的测试向量集，使得待测电路的平均功耗大大降低，给出了以ISCAS'85/89部分基准电路为对象的实验结果，电路的平均测试功耗降幅在54．4％－98．0％之间，证明了该方案的有效性。     

面向功耗优化的伪随机测试矢量生成

随着集成电路设计复杂度和工艺复杂度的提高，集成电路的测试面临越来越多的挑战，内建自测试作为一种新的可测性设计方法，能显著提高电路中随机逻辑的可测性，解决一系列测试难题，但它同时也引起了测试功耗问题，本文提出了一种面向功耗优化的伪随机测试向量生成方法，在保证故障覆盖率的条件下，大大降低了测试功耗。     

基于双模式LFSR的低功耗BIST结构

传统的BIST结构中,由于LFSR产生大量的测试矢量在测试过程中消耗了大量的功耗。为了减少测试矢量的数目而不影响故障覆盖率,我们提出了一种新的基于双模式LFSR的低功耗BIST结构。首先介绍了功耗模型和延迟模型的基础知识,然后给出了用于生成双模式LFSR的矩阵,并介绍了解矩阵方程式的算法。随后说明了新的BIST结构和用于矢量分组的模拟退火算法。最后,基于Benchmark电路的实验证明这种结构可以在不降低故障覆盖率的同时减少70％的功耗。     

基于模块划分方法的MPEG-2解码芯片可测性设计

以MPEG-2解码芯片为研究对象,采用基于模块划分方法进行可测性设计,包括边界扫描(JTAG)和内建自测试(BIST).根据MPEG-2系统结构的特点,把模块划分为存储器类型、信号不相关类型和信号相关类型.针对模块特性,设计不同的测试向量生成器,3种类型模块之间并行测试.测试结果表明,与未加入可测试设计的系统比较,固定故障覆盖率由81%提升到95.1%,而硬件开销仅为3%.     

VLSI可测性设计研究

从可测性设计与VLSI测试、VLSI设计之间的关系出发，将与可测性设计相关的VLSI测试方法学、设计方法学的内容有机地融合在一起。文中简要地介绍了VLSI可测性设计的理论基础和技术种类，简明地评述了可测性设计的现状和发展趋势，并且探讨了可测性设计的实现方法。     

大规模集成电路可测性设计及其应用策略

随着集成电路的规模不断增大,集成电路的可测性设计正变得越来越重要.综述了可测性设计方案扫描通路法、内建自测试法和边界扫描法,并分析比较了这几种设计方案各自的特点及应用策略.     

An Accumulator-Based BIST Approach for Two-Pattern Testing

Two-pattern tests target the detection of most common failure mechanisms in cmos vlsi circuits, which are modeled as stuck-open or delay faults. In this paper the Accumulator-Based Two-pattern generation (ABT) algorithm is presented, that generates an exhaustive n-bit two-pattern test within exactly 2 ⁿ × (2 ⁿ – 1) + 1 clock cycles, i.e. within the theoretically minimum time. The ABT algorithm is implemented in hardware utilizing an accumulator whose inputs are driven by either a binary counter (counter-based implementation) or a Linear Feedback Shift Register (LFSR-based implementation). With the counter-based implementation different modules, having different number of inputs, can be efficiently tested using the same generator. For circuits that do not contain counters, the LFSR-based implementation can be implemented, since registers (that typically drive the accumulator inputs into dapatapath cores) can be easily modified to LFSRS with small increase in the hardware overhead. The great advantage of the presented scheme is that it can be implemented by augmening existing datapath components, rather than building a new pattern generation structure.     

Design for Low Power Testing of Computation Modules with Contiguous Subspace in VLSI

A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very large scale integration （VLSI）, especially in digital signal processors （DSP）. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced, and the decrease of the test power consumption is resulted in. Results of experimentation based on FPGA show that the test approach can reduce dynamic power consumption by an average of 17.40% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Because of the reuse of adders, introduction of additional XOR logic gates is avoided successfully. The design minimizes additional hardware overhead for test and needs no adjustment of circuit structure. The low power test can detect any combinational stuck-at fault within the basic building block without any degradation of original circuit performance.     

低成本BIST映射电路的设计与优化

低成本BIST利用映射电路对自测试线形反馈移位寄存器进行优化,将对故障覆盖率无贡献的测试向量屏蔽掉,有效提高了故障覆盖率,降低了测试功耗。映射电路的设计是低成本BIST设计的关键,为了降低其硬件开销和功耗、提高参数性能,该映射逻辑电路对测试向量的种子进行映射,并通过相容逻辑变量合并、布尔代数化简等方法对映射电路进行优化,有效地降低了测试应用时间、测试功耗和硬件开销。     

基于可配置LFSR的低功耗确定性矢量生成技术的研究

针对组合电路内建自测试过程中的功耗和故障覆盖率等问题,提出了一种能获得较高故障覆盖率的低功耗测试矢量生成方案。该方案先借助A talanta测试矢量生成工具,针对不同的被测电路生成故障覆盖率较高的测试矢量,再利用插入单跳变测试矢量的方法以及可配置线性反馈移位寄存器生成确定性测试向量的原理,获得低功耗测试矢量。通过对组合电路集ISCAS’85的实验,证实了这种测试生成方案的有效性。     

A Low Power Pseudo-Random BIST Technique

Peak power consumption during testing is an important concern. For scan designs, a high level of switching activity is created in the circuit during scan shifts, which increases power consumption considerably. In this paper we propose a pseudo-random BIST scheme for scan designs, which reduces the peak power consumption as well as the average power consumption as measured by the switching activity in the circuit. The method reduces the switching activity in the scan chains and the activity in the circuit under test by limiting the scan shifts to a portion of the scan chain structure using scan chain disable. Experimental results on various benchmark circuits demonstrate that the technique reduces the switching activity caused by scan shifts.     

Low Cost BIST for Static and Dynamic Testing of ADCs

This paper presents a low cost test method for the static and dynamic characterization of analog-to-digital converters. The method is suitable for implementation in a SoC environment, as a built-in self test (BIST) solution. In the proposed approach, noise is used as the test signal. Theory of operation and practical results demonstrating the effectiveness of the method for INL, DNL, THD and SINAD characterization are presented. The BIST surface overhead caused by the noise generator is only 7.4% of the ADC total area. The reduced number of data samples required allows a reduction of about 7.5× in test time, in comparison to the histogram method.Maria da Gloria Cataldi Flores was born in Santa Maria, Brazil, in 1978. She received the electrical engineering degree in 2000 from Universidade Federal de Santa Maria (UFSM) and the M.S. degree engineering in 2003 from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then, she has been working as a design engineer in an EAS Supply brazilian company. Her main research interests include mixed-signal and analog testing and digital signal processing.Marcelo Negreiros was born in Porto Alegre, Brazil, in 1969. He received the electrical engineering degree in 1992 and the M.S. degree engineering in 1994, both from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then he was been working as an associate researcher in the Signal Processing Lab. (LaPSI) of the Electrical Engineering Department at UFRGS. Since 2000 he also works toward a Ph.D. in Computer Science from UFRGS. His main research interests include mixed-signal and analog testing and digital signal processing.Luigi Carro was born in Porto Alegre, Brazil, in 1962. He received the Electrical Engineering and the M.Sc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1985 and 1989, respectively. From 1989 to 1991 he worked at ST-Microelectronics, Agrate, Italy, in the R&D group. In 1996 he received the Ph.D. degree in the area of Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design and Digital Signal processing disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in Embedded Systems, Digital Signal Processing, and VLSI Design. His primary research interests include mixed-signal design, digital signal processing, mixed-signal and analog testing, and fast system prototyping. He has published more than 90 technical papers in those topics and is the author of the book Digital Systems Design and Prototyping (in portuguese).Altamiro A Susin was born in Vacaria-RS, Brazil, in 1945. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1972 and 1977, respectively. Since 1968 he worked in the start up of Computer Centers of two local Universities. In 1981 he got his Dr. Eng degree from Institut National Polytechnique de Grenoble-France. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible by courses in VLSI Architecture and is also thesis director. His main research interests are Integrated Circuit Architecture, Embedded Systems, Signal Processing with more than 50 technical papers published in those domains. He is/was responsible for several R&D projects either funded with public and/or industry resources.Felipe Ricardo Clayton received the B.S. degree in Electrical Engineering from State University of Campinas (UNICAMP), Brazil, in 1986. He worked at CPqD (Brazilian PTT R&D Center) till 1996 designing analog and mixed signal circuits for telecom and automotive applications. From 1997 to the second half of 1998, he worked at Instituto Superior Técnico (IST), Lisbon, Portugal, under the guidance of Prof. Carlos Azeredo Leme on development of CMOS RF circuits. Since October 1998 he had worked for Motorola SPS. Now he is head of the Power Managment Group at Freescale.Cristiano Benevento received his B.S. degree in Electrical Engineering from Universidade Estadual de Campinas (Unicamp), Brazil, in 1997. He worked at Motorola Cellular Infrastructure Group until August 2000 as a Systems Engineer. He joined Motorola Semiconductor Product Sector in August 2000 as IC Designer for Power Management Group and is now at Freescale.     

SoC中低峰值功耗的BIST调度算法

本文提出了一种系统芯片(SoC)中用于降低内建自测试(Built-in Self-test，BIST)峰值功耗的调度算法。首先本文提出了基于扫描BIST的精简功耗模型，在此模型的基础上，提出了通过调整扫描周期和扫描起动时间的办法来避免过高的SoC测试峰值功耗。实验结果表明，该算法可以有效地避免BIST并行执行可能带来的过高峰值功耗。     

A Gated Clock Scheme for Low Power Testing of Logic Cores

Test power is now a big concern in large core-based systems. In this paper, we present a general approach for minimizing power consumption during test of integrated circuits or embedded cores. The proposed low power/energy technique is based on a gated clock scheme that can be used in a test-per-scan or a test-per-clock environment. The idea is to reduce the clock rate on the scan path (test-per-scan) or the test pattern generator (test-per-clock) without increasing the test time. Numerous advantages can be found in applying such a technique.     

Low Power BIST by Filtering Non-Detecting Vectors

In this paper, two techniques to reduce the energy and the average power consumption of the system are proposed. They are based on the fact that as the test progresses, the detection efficiency of the pseudo-random vectors decreases very quickly. Many of the pseudo-random vectors will not detect faults in spite of consuming a significant amount of energy from the power supply. In order to prevent this energy consumption, a filtering of the non-detecting vectors and a reseeding strategy are proposed.These techniques are evaluated on the set of ISCAS-85 benchmark circuits. Extensive simulations have been made using the SAIL energy simulator showing that, in large circuits, the energy consumption and the average power savings reach 90.0% with a mean value of 74.2% with the filtering technique, and 97.2% with an average value of 90.9% with the reseeding strategy.