Wet-chemical passivation of atomically flat and structured silicon substrates for solar cell application

Special sequences of wet-chemical oxidation and etching steps were optimised with respect to the etching behaviour of differently oriented silicon to prepare very smooth silicon interfaces with excellent electronic properties on mono- and poly-crystalline substrates. Surface photovoltage (SPV) and photoluminescence (PL) measurements, atomic force microscopy (AFM) and scanning electron microscopy (SEM) investigations were utilised to develop wet-chemical smoothing procedures for atomically flat and structured surfaces, respectively. Hydrogen-termination as well as passivation by wet-chemical oxides were used to inhibit surface contamination and native oxidation during the technological processing. Compared to conventional pre-treatments, significantly lower micro-roughness and densities of surface states were achieved on mono-crystalline Si(100), on evenly distributed atomic steps, such as on vicinal Si(111), on silicon wafers with randomly distributed upside pyramids, and on poly-crystalline EFG (Edge-defined Film-fed-Growth) silicon substrates.The recombination loss at a-Si:H/c-Si interfaces prepared on c-Si substrates with randomly distributed upside pyramids was markedly reduced by an optimised wet-chemical smoothing procedure, as determined by PL measurements. For amorphous-crystalline hetero-junction solar cells (ZnO/a-Si:H(n)/c-Si(p)/Al) with textured c-Si substrates the smoothening procedure results in a significant increase of short circuit current I_sc, fill factor and efficiency η. The scatter in the cell parameters for measurements on different cells is much narrower, as compared to conventional pre-treatments, indicating more well-defined and reproducible surface conditions prior to a-Si:H emitter deposition and/or a higher stability of the c-Si surface against variations in the a-Si:H deposition conditions.     

Stability of hydrogen-terminated vicinal Si(1 1 1) surface under ambient atmosphere

In this paper a comparative study of different wet-chemical etching procedures of vicinal Si(1 1 1) surface passivation is presented. The stability against oxidation under ambient atmosphere was studied by X-ray photoelectron spectroscopy and atomic force microscopy. The best results were achieved by the buffered HF etching and the final smoothing of the surface by hot (72 °C) NH₄F. The procedures consisting of a large number of etching steps were unsatisfactory, since the probability of contamination during each step was increasing. The passivated surface was stable against oxidation for at least 3 h under ambient atmosphere.     

Passivation of defect states in Si-based and GaAs structures

Formation of defect states on semiconductor surfaces, at its interfaces with thin films and in semiconductor volumes is usually predetermined by such parameters as semiconductor growth process, surface treatment procedures, passivation, thin film growth kinetics, etc. This paper presents relation between processes leading to formation of defect states and their passivation in Si and GaAs related semiconductors and structures. Special focus is on oxidation kinetics of yttrium stabilized zirconium/SiO₂/Si and Sm/GaAs structures. Plasma anodic oxidation of yttrium stabilized zirconium based structures reduced size of polycrystalline silicon blocks localised at thin film/Si interface. Samarium deposited before oxidation on GaAs surface led to elimination of EL2 and/or ELO defects in MOS structures. Consequently, results of successful passivation of deep traps of interface region by CN⁻ atomic group using HCN solutions on oxynitride/Si and double oxide layer/Si structures are presented and discussed. By our knowledge, we are presenting for the first time the utilization of X-ray reflectivity method for determination of both density of SiO₂ based multilayer structure and corresponding roughnesses (interfaces and surfaces), respectively.     

Preparation of atomically clean and flat Si(1 0 0) surfaces by low-energy ion sputtering and low-temperature annealing

Si(1 0 0) surfaces were prepared by wet-chemical etching followed by 0.3–1.5 keV Ar ion sputtering, either at elevated or room temperature (RT). After a brief anneal under ultrahigh vacuum (UHV) conditions, the resulting surfaces were examined by scanning tunneling microscopy. We find that wet-chemical etching alone cannot produce a clean and flat Si(1 0 0) surface. However, subsequent 300 eV Ar ion sputtering at room temperature followed by a 700 °C anneal yields atomically clean and flat Si(1 0 0) surfaces suitable for nanoscale device fabrication.     

Flattening of micro-structured Si surfaces by hydrogen annealing

We report atomic scale flattening of surfaces of microstructures formed on Si wafers by furnace annealing. To avoid thermal deformation of the fabricated structures, advantage was taken of hydrogen annealing, which enables us to decrease the relaxation rate of Si surfaces due to surface hydrogenation. We examined cross-sectional shape and sidewall morphology of 3 μm deep trenches on Si(0 0 1) substrates after annealing at 1000 °C under various H₂ pressures of 40-760 Torr. We successfully formed Si trenches with flat surfaces composed of terraces and steps while preserving the designed trench profile by increasing H₂ pressure to 760 Torr.     

Imaging of ferroelectric vinylidene fluoride and trifluoroethylene copolymer films by scanning tunneling microscopy

In this paper, we reported the possibility to image non-conducting P(VDF-TrFE) copolymer films by STM. The films had the thickness of ∼25.0 nm and were spin-coated onto Au or graphite substrates. For films deposited on Au substrates, STM images showed grain structures of ∼100 nm, much larger than the grains of bare Au substrate. With increased scan rate, the film surface was damaged by STM tip and extreme protrusions and holes were observed. For films deposited on graphite substrates, we only obtained an image of very flat plane and could not observe the topography of the film surface. It seemed that the tip had pierced through the uppermost P(VDF-TrFE) layers and only imaged the layers nearest to the substrate. Asymmetrical current-voltage curves were observed from copolymer films deposited on HOPG. Experimental results were discussed.     

Si cleaning method without surface morphology change by cyanide solutions

Hydrogen cyanide (HCN) aqueous solutions can remove copper contaminants from Si surfaces more effectively than hydrochloric acid/hydrogen peroxide mixture (HPM) and sulfuric acid/hydrogen peroxide mixture (SPM). When pH of the HCN solutions is adjusted at 9, Si surface morphology is not changed, while when pH exceeds 10, the Si surfaces are considerably roughed. AFM measurements show that Cu contaminants are present in the form of particles on the bare Si surfaces. XPS measurements show that the particles consist of metallic Cu. The Cu particle height decreases almost linearly with the cleaning time, and the Cu surface concentration decreases exponentially with it. It is concluded that Cu particles gradually dissolve into the HCN aqueous solutions by the direct reaction with cyanide ions at the surface of the Cu particles.     

Self-assembly of silanated poly(ethylene glycol) on silicon and glass surfaces for improved haemocompatibility

Surface immobilization of poly(ethylene glycol) (PEG) is an effective method to produce a material surface with protein repulsive property. This property could be made permanent by using covalent grafting of the PEG molecules onto material surfaces. In this study, self-assembled monolayers (SAMs) of PEG on silicon-containing materials (silicon chip and glassplate) were obtained through a one-step coating procedure of one kind of silanated PEG molecules made through the reaction between monomethoxy PEG and 3-isocyanatopropyltriethoxysilane. Atomic force microscopy (AFM) and water static contact angle measurement were employed to investigate the surface topography and wettability of the PEGylated material surfaces. The changes in the topography and the water contact angle of the surfaces with time of incubation in PBS solution were also measured. The results revealed that stable and uniform self-assembled monolayers of PEG could be formed on silicon or glass surfaces by simply soaking the substrates in the solution of silanated PEGs. The covalent coupling of PEGs to the substrates was also confirmed. In order to evaluate the stability of the SAMs, blood compatibility of the modified glassplate surface was evaluated by measuring full blood activated partial thromboplastin time (APTT), prothrombin time (PT), and thrombin time (TT), as well as by scanning electron microscopy (SEM) analysis of the appearance of adherence and denaturation of blood platelets onto the glassplate. The silanated PEGs were shown to have good effect on the protein-repulsion as well as haemocompatibility of the substrates.     

Chemical Structures of the SiO2Si Interface

As a result of considerable progress in microfabrication technology for ultra-large scale integration (ULSI), it has become necessary to control oxide formation on an atomic scale in order to produce defect-free SiO₂/Si interfaces. However, the possibility of forming an atomically flat interface by oxidizing an atomically flat silicon surface without introducing structural defects is not yet clarified. In this article the present understanding of chemical structures of SiO₂/Si interfaces and initial stage of oxidation of silicon surfaces are reviewed.     

Structural studies of evaporated CoxCr1−x/Si (1 0 0) and CoxCr1−x/glass thin films

Series of Co_xCr_1−x thin films have been evaporated under vacuum onto Si (1 0 0) and glass substrates. Chemical composition and interface properties have been studied by modelling Rutherford backscattering spectra (RBS) using SIMNRA programme. Thickness ranges from 17 to 220 nm, and x from 0.80 to 0.88. Simulation of the energy spectra shows an interdiffusion profile in the thickest films, but no diffusion is seen in thinner ones. Microscopic characterizations of the films are done with X-ray diffraction (XRD) measurements. All the samples are polycrystalline, with an hcp structure and show a 〈0 0 0 1〉 preferred orientation. Atomic force microscopies (AFM) reveal very smooth film surfaces.     

Nanoporous carbon spheres and their application in dispersing silver nanoparticles

Monodisperse nanoporous carbon spheres (NCS) were synthesized in large quantities via a facile hydrothermal synthesis. It is found that the NCS have rough surfaces with a large quantity of uniformly distributed protruding and concaving zones. Large quantities of nanopores of about 0.3 nm in diameter are distributed uniformly on the whole sphere surfaces. The effects of reaction parameters on the surface roughness, sphere diameter and pore size of NCS were investigated. Taking the NCS as substrates, silver nanoparticles (NPs) were deposited onto their surfaces using a one-step ultrasonic electrodeposition procedure. The deposited silver NP has a uniform distribution, a high particle density and a narrow size range of 12-16 nm in diameter. This study demonstrates an efficient approach to fabricate noble-metal/carbon nanocomposites.     

Hydrogen on Si: Ubiquitous surface termination after wet-chemical processing

The manufacture of microelectronic devices based on silicon technology is largely dominated by wet chemical processes. By ultraclean sample preparation in air and a fast transfer into UltraHigh Vacuum (UHV) we open up a way for the atomic-scale structural and chemical characterization of silicon surfaces immediately after wet-chemical processing. Using Scanning Tunneling Microscopy (STM), ThermoDesorption (TDS) and InfraRed Spectroscopy (IRS), we find that a surface termination predominantly by hydrogen results from all the different wet-chemical treatments investigated (etching with hydrofluoric acid, rinsing with hot water, chemomechanical polishing)-despite the different chemical ambients and process parameters involved. Microscopically, a crystallographically preferential attack of the silicon is observed in all these processes which results, to a different extent, in anisotropic defect structures on the surfaces. This is explained by an interplay of aqueous reaction kinetics and sterical hindrance on the silicon surface. It is pointed out how a UHV surface analysis of the micromorphology of wet-chemically treated silicon surfaces, so far carried out mostly on Si(111) due to its easier preparation and experimental accessability, may help to provide the in-depth understanding of the atomic-scale mechanisms during wet-chemical processing demanded by the progressing miniaturization of microelectronic devices. The atomically smoother and chemically more homogeneous Si(111) obtained after preferential etching with NH₄F suggests that in future applications Si(111) may gain importance over Si(100), which still dominates in today's semiconductor technology, since future devices increasingly rely on tailor-made and ideal properties on an atomic scale. Due to their structural and chemical simplicity and well-controlable characteristics, H-teminated surfaces after wet-chemical preparation also form ideal substrates for conventional UHV surface studies such as absorption and MBE-growth experiments.     

Nitric acid method for fabrication of gate oxides in TFT

We have developed low temperature formation methods of SiO₂ layers which are applicable to gate oxide layers in thin film transistors (TFT) by use of nitric acid (HNO₃). Thick (>10 nm) SiO₂ layers with good thickness uniformity (i.e., ±4%) can be formed on 32 cm × 40 cm substrates by the two-step nitric acid oxidation method in which initial and subsequent oxidation is performed using 40 and 68 wt% (azeotropic mixture) HNO₃ aqueous solutions, respectively. The nitric acid oxidation of polycrystalline Si (poly-Si) thin films greatly decreases the height of ridge structure present on the poly-Si surfaces. When poly-Si thin films on 32 cm × 40 cm glass substrates are oxidized at azeotropic point (i.e., 68 wt% HNO₃ aqueous solutions at 121 °C), ultrathin (i.e., 1.1 nm) SiO₂ layers with a good thickness uniformity (±0.05 nm) are formed on the poly-Si surfaces. When SiO₂/Si structure fabricated using plasma-enhanced chemical vapor deposition is immersed in 68 wt% HNO₃, oxide fixed charge density is greatly decreased, and interface states are eliminated. The fixed charge density is further decreased by heat treatments at 200 °C, and consequently, capacitance-voltage characteristics which are as good as those of thermal SiO₂/Si structure are achieved.     

Surface morphology and reaction at Cu/Si interface—Effect of native silicon suboxide

Copper thin films are deposited by thermal evaporation on unetched and etched monocrystalline silicon. The study by alpha particles backscattering (RBS) raises a strong diffusion of copper in silicon substrates with and without native suboxide layer. On the other hand, the X-rays diffraction shows the formation and the growth of Cu₃Si and Cu₄Si silicides. Whereas the scanning microscopy underlines large crystallites growth surrounded by black zones of silicon coming from the uncovered substrate, independently to the surface state of the substrate, after annealing at high temperature. The presence of native silicon suboxide at Cu/Si interface, influences in a drastic way the minimal temperature to which the interfacial reaction occurs. The oxygen impurities detected by microanalysis, after heat treatment under vacuum, are closely related to the growth of silicides crystallites.     

Structural and electrical properties of zinc oxides thin films prepared by thermal oxidation

We report on zinc oxide (ZnO) thin films (d = 55-120 nm) prepared by thermal oxidation, at 623 K, of metallic zinc films, using a flash-heating method. Zinc films were deposited in vacuum by quasi-closed volume technique onto unheated glass substrates in two arrangements: horizontal and vertical positions relative to incident vapour. Depending on the preparation conditions, both quasi-amorphous and (0 0 2) textured polycrystalline ZnO films were obtained. The surface morphologies were characterized by atomic force microscopy and scanning electron microscopy. By in situ electrical measurements during two heating-cooling cycles up to a temperature of 673 K, an irreversible decrease of electrical conductivity of as flash-oxidized Zn films was revealed. The influence of deposition arrangement and oxidation conditions on the structural, morphological and electrical properties of the ZnO films is discussed.     

Pre-treatments applied to oxidized aluminum surfaces to modify the interfacial bonding with bis-1,2-(triethoxysilyl)ethane (BTSE): Part I. High-purity Al with native oxide

A remote microwave-generated H₂ plasma and heating to 250 °C were separately used to modify high-purity oxidized aluminum surfaces and to assess whether these treatments can help enhance adhesion with bis-1,2-(triethoxysilyl)ethane (BTSE) coatings. Different initial oxide surfaces were considered, corresponding to the native oxide and to surfaces formed by the Forest Products Laboratory (FPL) treatment applied for either 15 or 60 min. BTSE is applied from solution at pH 4, and competing processes of etching, protonation (to form OH groups) and coupling (to form AlOSi interfacial bonds) occur at the solid-liquid interface. Scanning electron microscopy (SEM) was used to determine how the topographies of the modified Al surfaces changed with the different pre-treatments and with exposure to a buffer solution of pH 4. Secondary-ion mass spectrometry (SIMS) was used to determine the direct amount of AlOSi interfacial bonds by measuring the ratio of peak intensities 71-70 amu, while X-ray photoelectron spectroscopy (XPS) was used to determine the overall strength of the silane coating adhesion by measuring the Si 2p signals before and after application of an ultrasonic rinse to the coated sample. Measured Al 2p and O 1s spectra helped assess how the different pre-treatments modified the various Al oxidized surfaces prior to BTSE coating. Pre-treated samples that showed increased AlOSi bonding after BTSE coating corresponded to surfaces, which did not show evidence of significant etching after exposure to a pH 4 environment. This suggests that such surfaces are more receptive to the coupling reaction during exposure to the BTSE coating solution. These surfaces include all H₂ plasma-treated samples, the heated native oxide and the sample that only received the 15 min FPL treatment. In contrast, other surfaces that show evidence of etching in pH 4 environments are samples that received lower amounts of AlOSi interfacial bonding. Overall, heating improved the BTSE adhesive bonding for the native Al oxide, while H₂ plasma treatment improved the BTSE bonding for surfaces that had initially been FPL-treated for 15 and 60 min.     

Crystalline Si thin-film solar cells: a review

The present review summarizes the results of research efforts in the field of crystalline silicon thin-film solar cells on foreign substrates. The large number of competing approaches can be broadly classified according to the grain size of the crystalline Si films and the doping of the crystalline absorber. Currently, solar cells based on microcrystalline Si films on glass with an intrinsic or moderately doped absorber film achieve efficiencies around 10%, whereas thin-film cells fabricated from large-grained polycrystalline Si on high-temperature-resistant substrates have efficiencies in the range of 15%. The paper discusses the limitations of various approaches and describes recent developments in the area of thin, monocrystalline Si films that may open the way towards 20% efficient thin-film Si solar cells. Received: 1 March 1999 / Accepted: 28 March 1999 / Published online: 24 June 1999     

Fabrication of high Ge content SiGe-on-insulator with low dislocation density by modified Ge condensation

A SiGe-on-insulator (SGOI) structure with high Ge content and low density of dislocations is fabricated by a modified Ge condensation technique. The formation and elimination of stacking faults during condensation process are analyzed by transmission electron microscopy. A Si_0.19Ge_0.81OI substrate is fabricated utilizing two steps of oxidation and intermittent annealing. The time of oxidation or annealing at 900 °C is essential for the elimination of stacking faults in high Ge content SGOI substrate. The surface morphology of SGOI is investigated by atomic force microscopy and the defect density is evaluated from wet etching method. After the final condensation, the surface root-mean-square roughness (rms) of SiGe layer is kept below 1 nm and the threading defect density is controlled around 10⁴ cm⁻². The smooth surface and integrated lattice structure of SiGe layer indicate that the SGOI is suitable for heteroepitaxial growth of strained Ge, GaAs and III-V compounds.     

Wet-chemical treatment and electronic interface properties of silicon solar cell substrates

On textured n-type silicon substrates for solar cell manufacturing, the relation between light trapping behavior, structural imperfections, energetic distribution of interface state densities and interface recombination losses were investigated by applying surface sensitive techniques. The field-modulated surface photovoltage (SPV), in-situ photoluminescence (PL) measurements, total hemispherical UV-NIR-reflectance measurements and electron microscopy (SEM) were employed to yield detailed information on the influence of wet-chemical treatments on preparation induced micro-roughness and electronic properties of polished and textured silicon substrates. It was shown that isotropic as well as anisotropic etching of light trapping structures result in high surface micro-roughness and density of interface states. Removing damaged surface layers in the nm range by wet-chemical treatments, the density of these states and the related interface recombination loss can be reduced. In-situ PL measurements were applied to optimise HF-treatment times aimed at undamaged, oxide-free and hydrogen-terminated substrate surfaces as starting material for subsequent solar cell preparations.      

C-V characterization of Schottky- and MIS-gate SiGe/Si HEMT structures

Electrical properties of Schottky- and metal-insulator-semiconductor (MIS)-gate SiGe/Si high electron mobility transistors (HEMTs) were investigated with capacitance-voltage (C-V) measurements. The MIS-gate HEMT structure was fabricated using a SiN gate insulator formed by catalytic chemical vapor deposition (Cat-CVD). The Cat-CVD SiN thin film (5 nm) was found to be an effective gate insulator with good gate controllability and dielectric properties. We previously investigated device characteristics of sub-100-nm-gate-length Schottky- and MIS-gate HEMTs, and reported that the MIS-gate device had larger maximum drain current density and transconductance (g_m) than the Schottky-gate device. The radio frequency (RF) measurement of the MIS-gate device, however, showed a relatively lower current gain cutoff frequency f_T compared with that of the Schottky-gate device. In this study, C-V characterization of the MIS-gate HEMT structure demonstrated that two electron transport channels existed, one at the SiGe/Si buried channel and the other at the SiN/Si surface channel.