Memory characteristics of platinum nanoparticle-embedded MOS capacitors

The capacitance characteristics of platinum nanoparticle (NP)-embedded metal–oxide–semiconductor (MOS) capacitors with gate Al₂O₃ layers are studied in this work. The capacitance versus voltage (C–V) curves obtained for a representative MOS capacitor exhibit flat-band voltage shifts, demonstrating the presence of charge storages in the platinum NPs. The counterclockwise hysteresis and flat-band voltage shift, observed from the C–V curves imply that electrons are stored in a floating gate layer consisting of the platinum NPs present between the tunneling and control oxide layers in the MOS capacitor and that these stored electrons originate from the Si substrate. Moreover, the charge remains versus time curve for the platinum NP-embedded MOS capacitor is investigated in this work.     

Stress-induced leakage currents of the RF sputtered Ta2O5 on N-implanted silicon

The electrical (C-V and I-V) and reliability (constant current stress technique) properties of RF sputtered 30 nm thick Ta₂O₅ on N-implanted Si have been investigated. The dependence on the parameters of both Ta₂O₅ and the implanted interfacial layers on the stress time are discussed. The leakage current characteristics are analyzed by previously proposed comprehensive model. It is established that the reliability of the Ta₂O₅-based capacitors can be effectively improved if the Si substrate is a subject to preliminary N-implantation—markedly smaller stress induced leakage current as compared to the films on bare Si are detected. The stress mainly affects the properties of the interfacial layer and the generation of neutral traps is identified to be the primary cause for the stress-induced degradation. It is concluded that the implantation results in a strengthening of the interfacial layer against stress degradation.     

Physical and electrical characteristics of a high-k Yb2O3 gate dielectric

High-k ytterbium oxide (Yb₂O₃) gate dielectrics were deposited on Si substrate by reactive sputtering. The structural features of these films after postdeposition annealing treatment were studied by X-ray diffraction and X-ray photoelectron spectroscopy. It is found that the Yb₂O₃ gate dielectrics annealed at 700 °C exhibit a larger capacitance value, a lower frequency dispersion and a smaller hysteresis voltage in C-V curves compared with other annealing temperatures. They also show negligible charge trapping under high constant voltage stress. This phenomenon is mainly attributed to the decrease in the amorphous silica thickness.     

The effect of interface states, excess capacitance and series resistance in the Al/SiO2/p-Si Schottky diodes

The current-voltage (I-V) characteristics of Al/SiO₂/p-Si metal-insulator-semiconductor (MIS) Schottky diodes were measured at room temperature. In addition the capacitance-voltage (C-V) and conductance-voltage (G-V) measurements are studied at frequency range of 10 kHz-1 MHz. The higher value of ideality factor of 3.25 was attributed to the presence of an interfacial insulator layer between metal and semiconductor and the high density of interface states localized at Si/SiO₂ interface. The density of interface states (N_ss) distribution profile as a function of (E_ss − E_v) was extracted from the forward bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_e) at room temperature for the Schottky diode on the order of ≅4 × 10¹³ eV⁻¹ cm⁻²_. These high values of N_ss were responsible for the non-ideal behaviour of I-V and C-V characteristics. Frequency dispersion in C-V and G-V can be interpreted only in terms of interface states. The N_ss can follow the ac signal especially at low frequencies and yield an excess capacitance. Experimental results show that the I-V, C-V and G-V characteristics of SD are affected not only in N_ss but also in series resistance (R_s), and the location of N_ss and R_s has a significant on electrical characteristics of Schottky diodes.     

Al2O3绝缘层的AlGaN/GaN MOSHEMT器件研究

在研制AlGaN/GaN HEMT器件的基础上,采用ALD法制备了Al₂O₃ AlGaN/GaN MOSHEMT器件.通过X射线光电子能谱测试表明在AlGaN/GaN异质结材料上成功淀积了Al₂O₃薄膜.根据对HEMT和MOSHEMT器件肖特基电容、器件输出以及转移特性的测试进行分析发现：所制备的Al₂O₃薄膜与AlGaN外延层间界面态密度较小,因而MOSHEMT器件呈现出较 关键词： 2O₃')" href="#">Al₂O₃ ALD GaN MOSHEMT     

Dielectric properties of ferroelectric/DMS heterointerface using YMnO3 and Ce doped Si

Bottom gate type Al/Si:8.2 at%Ce/YMnO₃/Pt capacitor was fabricated. Although it was polycrystalline, we successfully obtained Si:8.2 at%Ce film on ferroelectric YMnO₃. The dielectric properties of the capacitor were carefully investigated. Although the capacitance shows frequency dispersion, the capacitor exhibits a ferroelectric type C-V hysteresis loop. From the PUND and P-V measurements, ferroelectric polarization was distinguished from the another polarization, Based on these dielectric measurements, effect of polarization induced by the ferroelectric YMnO₃ on the carrier modulation in the diluted magnetic semiconductor, Ce doped Si film was discussed.     

Al2O3介质层厚度对AlGaN/GaN金属氧化物半导体-高电子迁移率晶体管性能的影响

在蓝宝石衬底上采用原子层淀积法制作了三种不同Al₂O₃介质层厚度的绝缘栅高电子迁移率晶体管.通过对三种器件的栅电容、栅泄漏电流、输出和转移特性的测试表明：随着Al₂O₃介质层厚度的增加,器件的栅控能力逐渐减弱,但是其栅泄漏电流明显降低,击穿电压相应提高.通过分析认为薄的绝缘层能够提供大的栅电容,因此其阈值电压较小,但是绝缘性能较差,并不能很好地抑制栅电流的泄漏;其次随着介质厚度的增加,可以对栅极施加更高的正偏压,因此获 关键词： 2O₃')" href="#">Al₂O₃ 金属氧化物半导体-高电子迁移率晶体管 介质层厚度 钝化     

Characteristics of sandwich-structured Al2O3/HfO2/Al2O3 gate dielectric films on ultra-thin silicon-on-insulator substrates

Sandwich-structure Al₂O₃/HfO₂/Al₂O₃ gate dielectric films were grown on ultra-thin silicon-on-insulator (SOI) substrates by vacuum electron beam evaporation (EB-PVD) method. AFM and TEM observations showed that the films remained amorphous even after post-annealing treatment at 950 °C with smooth surface and clean silicon interface. EDX- and XPS-analysis results revealed no silicate or silicide at the silicon interface. The equivalent oxide thickness was 3 nm and the dielectric constant was around 7.2, as determined by electrical measurements. A fixed charge density of 3 × 10¹⁰ cm⁻² and a leakage current of 5 × 10⁻⁷A/cm² at 2 V gate bias were achieved for Au/gate stack /Si/SiO₂/Si/Au MIS capacitors. Post-annealing treatment was found to effectively reduce trap density, but increase in annealing temperature did not made any significant difference in the electrical performance.     

Effect of UV lamp irradiation during oxidation of Zr/Pt/Si structure on electrical properties of Pt/ZrO2/Pt/Si structure

Metal-insulator-metal (MIM) capacitors were fabricated using ZrO₂ films and the effects of structural and native defects of the ZrO₂ films on the electrical and dielectric properties were investigated. For preparing ZrO₂ films, Zr films were deposited on Pt/Si substrates by ion beam deposition (IBD) system with/without substrate bias voltages and oxidized at 200 °C for 60 min under 0.1 MPa O₂ atmosphere with/without UV light irradiation (λ = 193 nm, Deep UV lamp). The ZrO₂(∼12 nm) films on Pt(∼100 nm)/Si were characterized by X-ray diffraction pattern (XRD), field emission scanning electron microscopy (FE-SEM) and high-resolution transmission electron microscopy (HRTEM), capacitance-voltage (C-V) and current-voltage (I-V) measurements were carried out on MIM structures. ZrO₂ films, fabricated by oxidizing the Zr film deposited with substrate bias voltage under UV light irradiation, show the highest capacitance (784 pF) and the lowest leakage current density. The active oxygen species formed by UV irradiation are considered to play an important role in the reduction of the leakage current density, because they can reduce the density of oxygen vacancies.     

The effect of Si surface nitridation on the interfacial structure and electrical properties of (La2O3)0.5(SiO2)0.5 high-k gate dielectric films

Thermal stability, interfacial structures and electrical properties of amorphous (La₂O₃)_0.5(SiO₂)_0.5 (LSO) films deposited by using pulsed laser deposition (PLD) on Si (1 0 0) and NH₃ nitrided Si (1 0 0) substrates were comparatively investigated. The LSO films keep the amorphous state up to a high annealing temperature of 900 °C. HRTEM observations and XPS analyses showed that the surface nitridation of silicon wafer using NH₃ can result in the formation of the passivation layer, which effectively suppresses the excessive growth of the interfacial layer between LSO film and silicon wafer after high-temperature annealing process. The Pt/LSO/nitrided Si capacitors annealed at high temperature exhibit smaller CET and EOT, a less flatband voltage shift, a negligible hysteresis loop, a smaller equivalent dielectric charge density, and a much lower gate leakage current density as compared with that of the Pt/LSO/Si capacitors without Si surface nitridation.     

Influence of Si/SiO2 interface properties on electrical performance and breakdown characteristics of ultrathin stacked oxide/nitride dielectric films

In this work, the influence of Si/SiO₂ interface properties, interface nitridation and remote-plasma-assisted oxidation (RPAO) thickness (<1 nm), on electrical performance and TDDB characteristics of sub-2 nm stacked oxide/nitride gate dielectrics has been investigated using a constant voltage stress (CVS). It is demonstrated that interfacial plasma nitridation improves the breakdown and electrical characteristics. In the case of PMOSFETs stressed in accumulation, interface nitridation suppresses the hole traps at the Si/SiO₂ interface evidenced by less negative V_t shifts. Interface nitridation also retards hole tunneling between the gate and drain, resulting in reduced off-state drain leakage. In addition, the RPAO thickness of stacked gate dielectrics shows a profound effect in device performance and TDDB reliability. Also, it is demonstrated that TDDB characteristics are improved for both PMOS and NMOS devices with the 0.6 nm-RPAO layer using Weibull analysis. The maximum operating voltage is projected to be improved by 0.3 V difference for a 10-year lifetime. However, physical breakdown mechanism and effective defect radius during stress appear to be independent of RPAO thickness from the observation of the Weibull slopes. A correlation between trap generation and dielectric thickness changes based on the C-V distortion and oxide thinning model is presented to clarify the trapping behavior in the RPAO and bulk nitride layer during CVS stress.     

A model for the electrical characteristics of metal-ferroelectric-insulator-semiconductor field-effect transistor

An improved theoretical model on the electrical characteristics of metal-ferroelectric-insulator-semiconductor field-effect transistor (MFIS-FET) has been proposed by considering the history-dependent electric field effect and the mobility model. The capacitance-voltage (C-V) characteristics of MFIS structure is evaluated by combining the switching physics of ferroelectric with the silicon physics, and the drain current-gate voltage (I_D-V_GS) and drain current-drain voltage (I_D-V_DS) characteristics of MFIS-FET are modeled by combining the switching physics of ferroelectric with Pao and Sah’s double integral. For two MFIS-FETs with SrBi₂Ta₂O₉ and (Bi,La)₄Ti₃O₁₂ ferroelectric layers, the C-V, I_D-V_GS and I_D-V_DS characteristics are simulated by using the improved model, and the results are more consistent with the previous experiment than those based on Lue model, indicating that the improved model is suitable for simulating the electrical characteristics of MFIS-FET. This work is expected to provide some guidance to the design and performance improvement of MFIS structure devices.     

Ionizing radiation effects on electrical and reliability characteristics of sputtered Ta2O5/Si interface

This paper describes the effect of ionizing radiation on the interface properties of Al/Ta₂O₅/Si metal oxide semiconductor (MOS) capacitors using capacitance–voltage (C–V) and current–voltage (I–V) characteristics. The devices were irradiated with X-rays at different doses ranging from 100?rad to 1?Mrad. The leakage behavior, which is an important parameter for memory applications of Al/Ta₂O₅/Si MOS capacitors, along with interface properties such as effective oxide charges and interface trap density with and without irradiation has been investigated. Lower accumulation capacitance and shift in flat band voltage toward negative value were observed in annealed devices after exposure to radiation. The increase in interfacial oxide layer thickness after irradiation was confirmed by Rutherford Back Scattering measurement. The effect of post-deposition annealing on the electrical behavior of Ta₂O₅ MOS capacitors was also investigated. Improved electrical and interface properties were obtained for samples deposited in N₂ ambient. The density of interface trap states (D_it) at Ta₂O₅/Si interface sputtered in pure argon ambient was higher compared to samples reactively sputtered in nitrogen-containing plasma. Our results show that reactive sputtering in nitrogen-containing plasma is a promising approach to improve the radiation hardness of Ta₂O₅/Si MOS devices.     

Effect of Ti doping on Ta2O5 stacks with Ru and Al gates

The Ti-doped Ta₂O₅ thin films (<10 nm) obtained by rf sputtering are studied with respect to their composition, dielectric and electrical properties. The incorporation of Ti is performed by two methods - a surface doping, where a thin Ti layer is deposited on the top of Ta₂O₅ and a bulk doping where the Ti layer is sandwiched between two layers of Ta₂O₅. The effect of the process parameters (the method and level of doping) on the elemental distribution in-depth of the films is investigated by the time of flight secondary ion mass spectroscopy (ToF-SIMS). The Ti and Ta₂O₅ are intermixed throughout the whole thickness but the layers are very inhomogeneous. Two sub-layers exist in all the samples — a near interfacial region which is a mixture of Ta-, Ti-, Si-oxides as well as TaSiO, and an upper Ti-doped Ta₂O₅ sub-layer. For both methods of doping, Ti tends to pile-up at the Si interface. The electrical characterisation is performed on capacitors with Al- and Ru-gate electrodes. The two types of MIS structures exhibit distinctly different electrical behavior: the Ru gate provides higher dielectric permittivity while the stacks with Al electrode are better in terms of leakage currents. The specific metal-dielectric reactions and metal-induced electrically active defects for each metal electrode/high-k dielectric stack define its particular electrical behavior. It is demonstrated that the Ti doping of Ta₂O₅ is a way of remarkable improvement of leakage characteristics (the current reduction with more than four orders of magnitude as compared with undoped Ta₂O₅) of Ru-gated capacitors which originates from Ti induced suppression of the oxygen vacancy related defects.     

Inhomogeneities in 130 MeV Au ion irradiated Au/n-Si (1 0 0) Schottky structure

The electrical characteristics of Au/n-Si (1 0 0) Schottky rectifier have been studied in a wide irradiation fluence range using conventional current-voltage (I-V) and capacitance-voltage (C-V) measurements. The I-V characteristics showed an abnormal increase in forward current at low voltage. The device shows a bend in forward I-V and reverses bias C-V characteristics due to extra current, suggesting that there are two independent contributions to thermionic current, corresponding to two levels of the Schottky barrier. It is shown that the excess current at low voltage can be explained by taking into account the role of heavy ion irradiation induced defects at the metal semiconductor interface.     

氮化硅介质中双层纳米硅薄膜的两级电荷存储

研究镶嵌在超薄非晶氮化硅(a-SiN_x)层之间的双层纳米硅(nc-Si)的电荷存储现象.利用等离子体增强化学气相淀积(PECVD)技术在硅衬底上制备a-SiN_x/a-Si/a-SiN_x/a-Si/a-SiN_x多层薄膜结构.采用常规热退火方法使非晶硅(a-Si)层晶化，形成包含双层nc-Si的金属-氮化物-半导体(MIS)结构.通过电容电压(C-V)特性测量，观测到该结构中由于电荷存储引起的C-V回滞现象，并在室温下成功观察到载流子基于Fowler-Nordheim(F-N)隧穿注入到第一层、第二层nc-Si的两级电荷存储状态.结合电流电压(I-V)特性的测量，对电荷存储的机理进行了深入分析. 关键词： 纳米硅 氮化硅 电容电压法 电流电压法     

Trap-controlled behavior in ultrathin Lu2O3 high-k gate dielectrics

Amorphous Lu₂O₃ high-k gate dielectrics were grown directly on n-type (100) Si substrates by the pulsed laser deposition (PLD) technique. High-resolution transmission electron microscope (HRTEM) observation illustrated that the Lu₂O₃ film has amorphous structure and the interface with Si substrate is free from amorphous SiO₂. An equivalent oxide thickness (EOT) of 1.1 nm with a leakage current density of 2.6×10⁻⁵ A/cm² at 1 V accumulation bias was obtained for 4.5 nm thick Lu₂O₃ thin film deposited at room temperature followed by post-deposition anneal (PDA) at 600 °C in oxygen ambient. The effects of PDA process and light illumination were studied by capacitance-voltage (C-V) and current density-voltage (J-V) measurements. It was proposed that the net fixed charge density and leakage current density could be altered significantly depending on the post-annealing conditions and the capability of traps to trap and release charges.     

Preparation and characterization of ferroelectric SrBi2Ta2O9 thin films on Si using Al2O3 buffer layers

SrBi₂Ta₂O₉ (SBT) thin films were prepared on p-type Si(100) substrates with Al₂O₃ buffer layers. Both the SBT films and the Al₂O₃ buffer layers were deposited by a pulsed laser deposition technique using a KrF excimer laser. An Al prelayer was used to prevent Si surface oxidization in the initial growth stage. It is shown that Al₂O₃ buffer layers effectively prevented interdiffusion between SBT and Si substrates. Furthermore, the capacitance–voltage (C-V) characteristics of the SBT/Al₂O₃/Si heterostructures show a hysteresis loop with a clockwise trace, demonstrating the ferroelectric switching properties of SBT films and showing a memory window of 1.6 V at 1 MHz. Received: 17 July 2000 / Accepted: 16 August 2000 / Published online: 30 November 2000     

Influence of lithium phosphate concentration and temperature on the electrical conduction of (76V2O5-24P2O5)1−X (Li3PO4)X glasses

Characterization of the (76V₂O₅-24P₂O₅)_1−X (Li₃PO₅)_X, where X=0.0,0.01,0.02,0.10 and 0.15, glass has been done using X-ray diffraction and differential thermal analysis (DTA). The dc conductivity of the glass samples was studied over a temperature range from 300 to 593 K. The temperature dependence of dc conductivity shows two regions. One at relatively high temperature range, above θ_D/2, and the other at relatively low temperature range, below θ_D/2. The I-V characteristics of the glasses have been studied as a function of both temperature and Li₃PO₄ content. The I-V characteristics exhibits threshold switching with differential negative resistance. It's found that both the threshold voltage (V_th) and threshold current (I_th) are dependent on the temperature and lithium phosphate concentration.     

Controlling the electrical characteristics of Al/p-Si structures through Bi4Ti3O12 interfacial layer

In this study, the effects of high permittivity interfacial Bi₄Ti₃O₁₂ (BTO) layer deposition on the main electrical parameters; such as barrier height, series resistance, rectifying ratio, interface states and shunt resistance, of Al/p-Si structures are investigated using the current–voltage (I–V) and admittance measurements (capacitance–voltage, C–V and conductance–voltage, G/ω–V) at 1 MHz and room temperature. I–V characteristics revealed that, due to BTO layer deposition, series resistance values that were calculated by both Ohm's law and Cheung's method decreased whereas shunt resistance values increased. Therefore, leakage current value decreased significantly by almost 35 times as a result of high permittivity interfacial BTO layer. Moreover, rectifying ratio was improved through BTO interfacial layer deposition. I–V data indicated that high permittivity interfacial BTO layer also led to an increase in barrier height. Same result was also obtained through C–V data. Obtained results showed that the performance of the device is considerably dependent on high permittivity BTO interfacial layer.