Variation aware intuitive clock gating to mitigate on-chip power supply noise

With the advent of semiconductor process technology, both the dynamic and static power consumption have become major concerns for the circuit designers. Though clock gating (CG) is a potentially accomplished technique to minimise the dynamic power, it generally fails to cut down the static power dissipation. To address the same, we have unveiled a new CG scheme incorporating leakage control transistor, which simultaneously curbs the static and dynamic power along with the alleviation of power supply noise (PSN) in silicon chips by smartly controlling the current ramp (di/dt) and average current i(t): the main contributors to PSN. The proposed CG does not only save average, dynamic and static power by 84.34%, 90.33% and 66.73%, respectively, but also reduces PSN by 84.44% with respect to its non-gated counterpart when simulated using Cadence Virtuoso® for 90 nm Generic Process Design Kit at a switching frequency of 5 GHz and power supply voltage of 1.1 V.     

Power supply noise in accurate delay model for the sub-threshold domain

Ultra-Low-Power circuits demand has dramatically increased in the last few years. One of the main challenges in designing these circuits is that transistors often run in the sub-threshold regime and their on current is exponentially dependent on the gate-to-source voltage, thus making sub-threshold gates extremely susceptible to power and ground noise phenomena. This paper provides a complete mathematical model in closed form for the delay of sub-threshold CMOS inverters. The novel model can predict the behavior of inverters output signal and therefore it can be extremely useful in the design phase to analyze the variations caused by noise on the output over/undershoot and the gate delay. The proposed model has a general validity since it considers the ground and supply noises completely uncorrelated both in frequency and in amplitude. When a commercial CMOS 45 nm process technology is referenced, the proposed model exhibits a maximum error of only ~16% under different conditions in terms of output load capacitance, input signal rising/falling time, noise phase and frequency.     

Statistical power supply dynamic noise prediction in hierarchical power grid and package networks

One of the most crucial high performance systems-on-chip design challenge is to front their power supply noise sufferance due to high frequencies, huge number of functional blocks and technology scaling down. Marking a difference from traditional post physical-design static voltage drop analysis, a priori dynamic voltage drop evaluation is the focus of this work. It takes into account transient currents and on-chip and package RLC parasitics while exploring the power grid design solution space: Design countermeasures can be thus early defined and long post physical-design verification cycles can be shortened. As shown by an extensive set of results, a carefully extracted and modular grid library assures realistic evaluation of parasitics impact on noise and facilitates the power network construction; furthermore statistical analysis guarantees a correct current envelope evaluation and Spice simulations endorse reliable results.     

彩色电视机中开关电源的输出噪声及抑制

对影响彩电开关电源输出噪声的主要因素进行分析,提出了抑制噪声的常用方法,并给出了实用输出噪声抑制电路。     

A 0.65-V process variation and supply noise insensitive ring VCO

A low-voltage feedforward ring voltage-controlled oscillator (FRVCO) withstanding process variation and supply-voltage noise is proposed in this paper. In this design, the variation of transistors’ threshold voltages and supply voltage noise are detected by a compensating voltage generated circuit, and the load capacitance of the FRVCO is tuned by the compensating voltage to reduce the variation of oscillating frequency. Simulation results demonstrate that the centre oscillating frequency difference between ‘FF’ and ‘SS’ corners is reduced from 38.3% to 1.5% by tuning the voltage from 0 to 650 mV. Moreover, with a supply voltage change of ±0.5%, the frequency variation is smaller than ±0.06%. The 0.65-V 600-MHz FRVCO has been fabricated using the TSMC 130-nm CMOS process.     

Jitter and phase noise of ADPLL due to PSN with deterministic frequency

In this article, jitter and phase noise of all-digital phase-locked loop due to power supply noise (PSN) with deterministic frequency are analysed. It leads to the conclusion that jitter and phase noise heavily depend on the noise frequency. Compared with jitter, phase noise is much less affected by the deterministic PSN. Our method is utilised to study a CMOS ADPLL designed and simulated in SMIC 0.13?µm standard CMOS process. A comparison between the results obtained by our method and those obtained by simulation and measurement proves the accuracy of the predicted model. When the digital controlled oscillator was corrupted by PSN with 100?mVpk-pk, the measured jitters were 33.9?ps at the rate of f_G?=?192?MHz and 148.5?ps at the rate of f_G?=?40?MHz. However, the measured phase noise was exactly the same except for two impulses appearing at 192 and 40?MHz, respectively.     

A new burst assembly scheme based on the average packet delay and its performance for TCP traffic

We propose and evaluate a new burst assembly algorithm based on the average delay of the packets comprising a burst. This method fixes the average delay of the packets belonging to an assembled burst to a desired value $T_{\mathrm{AVE}}$ that may be different for each forwarding equivalence class (FEC). We show that the proposed method significantly improves the delay jitter experienced by the packets during the burst assembly process, when compared to that of timer-based and burst length-based assembly policies. Minimizing packet delay jitter is important in a number of applications, such as real-audio and streaming-video applications. We also find that the improvement in the packet delay jitter yields a corresponding significant improvement in the performance of TCP, whose operation depends critically on the ability to obtain accurate estimates of the round-trip times (RTT).     

New differential difference stage and its application to band-pass filter at 10.7 MHz with high quality factor

In this study, we present a new NMOS implementation of differential difference stage containing only eight transistors. The introduced new differential difference stage has high input impedance and low output impedance; accordingly, it can be directly cascaded without loading effect. In addition, a detailed study on the input referred noise voltage density of the proposed differential difference stage is performed and low noise design possibility is investigated. As an example, to show performance of differential difference stage, a modified band-pass filter with high quality factor is presented for intermediate frequency stage of FM receiver. Furthermore, the non-ideal, parasitic and stability analyses of the presented filter having high quality factor are surveyed and its working boundaries are determined.