Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation

The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10¹⁸ cm^-3 and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.     

Scaling properties of phase-change line memory

Phase-change line memory cells with different line widths are fabricated using focused-ion-beam deposited C-Pt as a hard mask. The electrical performance of these memory devices was characterized. The current-voltage (I-V ) and resistance-voltage (R-V ) characteristics demonstrate that the power consumption decreases with the width of the phase-change line. A three-dimensional simulation is carried out to further study the scaling properties of the phase-change line memory. The results show that the resistive amorphous (RESET) power consumption is proportional to the cross-sectional area of the phase-change line, but increases as the line length decreases.     

A simple and accurate method for measuring program/erase speed in a memory capacitor structure

With the merits of a simple process and a short fabrication period, the capacitor structure provides a convenient way to evaluate memory characteristics of charge trap memory devices. However, the slow minority carrier generation in a capacitor often makes an underestimation of the program/erase speed. In this paper, illumination around a memory capacitor is proposed to enhance the generation of minority carriers so that an accurate measurement of the program/erase speed can be achieved. From the dependence of the inversion capacitance on frequency, a time constant is extracted to quantitatively characterize the formation of the inversion layer. Experimental results show that under a high enough illumination, this time constant is greatly reduced and the measured minority carrier-related program/erase speed is in agreement with the reported value in a transistor structure.     

A simple and accurate method to measure program/erase speed in a memory capacitor structure

With the merits of simple process and short fabrication period, the capacitor structure provides a convenient way to evaluate memory characteristics of charge trap memory devices. However, the slow minority carrier generation in a capacitor often makes an underestimation of the program/erase speed. In this paper, illumination around a memory capacitor is proposed to enhance the generation of minority carriers so that an accurate measurement of the program/erase speed can be achieved. From the dependence of the inversion capacitance on frequency, a time constant is extracted to quantitatively characterize the formation of the inversion layer. Experimental results show that under a high enough illumination, this time constant is greatly reduced and the measured minority carrier related program/erase speed is in agreement with the reported value in a transistor structure.     

Performance improvement of charge trap flash memory by using a composition-modulated high-k trapping layer

A composition-modulated （HfO2）x（Al2O3）1-x charge trapping layer is proposed for charge trap flash memory by controlling the A1 atom content to form a peak and valley shaped band gap. It is found that the memory device using the composition-modulated （HfO2）x（Al2O3）l-x as the charge trapping layer exhibits a larger memory window of 11.5 V, improves data retention even at high temperature, and enhances the program/erase speed. Improvements of the memory characteristics are attributed to the special band-gap structure resulting from the composition-modulated trapping layer. Therefore, the composition-modulated charge trapping layer may be useful in future nonvolatile flash memory device application.     

Atomic crystals resistive switching memory

Facing the growing data storage and computing demands, a high accessing speed memory with low power and non volatile character is urgently needed. Resistive access random memory with 4F~2 cell size, switching in sub-nanosecond cycling endurances of over 10~(12) cycles, and information retention exceeding 10 years, is considered as promising nex generation non-volatile memory. However, the energy per bit is still too high to compete against static random acces memory and dynamic random access memory. The sneak leakage path and metal film sheet resistance issues hinder th further scaling down. The variation of resistance between different devices and even various cycles in the same device hold resistive access random memory back from commercialization. The emerging of atomic crystals, possessing fin interface without dangling bonds in low dimension, can provide atomic level solutions for the obsessional issues. Moreove the unique properties of atomic crystals also enable new type resistive switching memories, which provide a brand-new direction for the resistive access random memory.     

Charging/discharging kinetics in LPCVD silicon nanocrystal MOS memory structures

The paper focuses on the peculiarities of charging/discharging kinetics and write/erase (W/E) window formation in nanocrystal metal-oxide semiconductor (MOS) non-volatile memory (NVM) structures prepared by low-pressure chemical vapor deposition (LPCVD) of amorphous silicon, followed by solid phase crystallization and thermal oxidation. It is generally known that the W/E window formation via pulse injection depends on the kinetics of carriers trapping (electrons and/or holes) in the nanocrystal NVM structure and consequently on the cumulative time of recharging bias application, i.e. pulse duration and number of applied pulses. In this work, we have shown that with the same cumulative time biasing but different charging pulse durations, the resulting W/E window width can be rather different, demonstrating a staircase window formation. This phenomenon is interpreted by a model of partial fast charge draining from the trapping sites in the vicinity of Si nanoclusters into the Si substrate. The detailed experimental investigation of charging/discharging kinetics of the considered structures in combination with computer simulations lead to the conclusion that there is a single process of negative charge trapping with a time constant of 235±35 ms and at least four processes of positive charge trapping with time constants distributed in the range from <10 ms to >10 s.     

Hafnia-based resistive switching devices for non-volatile memory applications and effects of gamma irradiation on device performance

Non-volatile memory (NVM) devices were fabricated as a Metal– Insulator–Metal (MIM) structures by sandwiching Hafnium dioxide (HfO₂) thin film in between two metal electrodes. The top and bottom metal electrodes were deposited by using the thermal evaporation, and the oxide layer was deposited by using the RF magnetron sputtering technique. The Resistive Random Access Memory (RRAM) device structures such as Ag/HfO₂/Au/Si were fabricated and I-V characteristics for the pristine and gamma-irradiated devices with a dose 24?kGy were measured. Further we have studied the thermal annealing effects, in the range of 100°–400°C in a tubular furnace for the HfO₂/Au/Si samples. The X-ray diffraction (XRD), Rutherford Backscattering Spectrometry (RBS), field emission-scanning electron microscopy (FESEM) analysis measurements were performed to determine the thickness, crystallinity and stoichiometry of these films. The electrical characteristics such as resistive switching, endurance, retention time and switching speed were measured by a semiconductor device analyser. The effects of gamma irradiation on the switching properties of these RRAM devices have been studied.     

A 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain

As the scaling of CMOS transistors extends to the sub-20 nm regime, the most challenging aspect of device design is the control of the off-state current. The traditional methods for controlling leakage current via the substrate doping profile will be difficult to implement at these dimensions. A promising method for controlling leakage in sub-20 nm transistors is the reduction in source-to-drain leakage paths through the use of a body region which is significantly thinner then the gate length, with either a single or a double gate. In this paper we present ultra-thin body PMOS transistors with gate lengths down to 20 nm fabricated using a low-barrier silicide as the source and drain. Calixarene-based electron-beam lithography was used to define critical device dimensions. These transistors show 260 μ A μ m ^{− 1}on-current and on/off current ratios of 10⁶, for a conservative oxide thickness of 40 Å and | V_g − V_t| = 1.2 V. Excellent short-channel effect, with only 0.2 V reduction in | V_t| is obtained in devices with gate lengths ranging from 100 to 20 nm.     

Numerical simulation study of organic nonvolatile memory with polysilicon floating gate

A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated,in which polysilicon is sandwiched between oxide layers as a floating gate.Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed.The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing(P/E) operations at various P/E voltages are discussed.The simulated results show that present memory exhibits a large memory window of 57.5 V,and a high read current on/off ratio of ≈ 10~3.Compared with the reported experimental results,these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects,which shows great promise in device designing and practical application.     

Influence of excess Si distribution in the gate oxide on the memory characteristics of MOSFETs

In this work, Si ions are implanted into the gate oxide of MOSFETs with different implantation schemes, followed by a high-temperature annealing. The memory characteristics of the MOSFETs have been investigated for the following two excess Si distributions: (1) the excess Si is distributed in a narrow layer in the gate oxide near the Si substrate; and (2) the excess Si is distributed throughout the gate oxide. It is observed that both the excess Si distributions have good endurance of up to 10⁶ program/erase cycles. The second excess Si distribution exhibits a better retention characteristic with less than 50% charge loss after 10 years. In contrast, the first excess Si distribution shows a complete charge loss after 1 year. PACS 73.22.-f; 73.63.Bd; 81.07.Bc     

Ferroelectric memory

The current status of developments in the field of ferroelectric memory devices has been considered. The rapidly growing market of non-volatile memory devices has been analyzed, and the current state of the art and prospects for the scaling of parameters of non-volatile memory devices of different types have been considered. The basic constructive and technological solutions in the field of the design of ferroelectric memory devices, as well as the ??roadmaps?? of the development of this technology, have been discussed.     

LaTiON/LaON as band-engineered charge-trapping layer for nonvolatile memory applications

Charge-trapping characteristics of stacked LaTiON/LaON film were investigated based on Al/Al₂O₃/LaTiON-LaON/SiO₂/Si (band-engineered MONOS) capacitors. The physical properties of the high-k films were analyzed by X-ray diffraction, transmission electron microscopy and X-ray photoelectron spectroscopy. The band profile of this band-engineered MONOS device was characterized by investigating the current-conduction mechanism. By adopting stacked LaTiON/LaON film instead of LaON film as charge-trapping layer, improved electrical properties can be achieved in terms of larger memory window (5.4 V at ±10-V sweeping voltage), higher program speed with lower operating gate voltage (2.1 V at 100-μs +6 V), and smaller charge loss rate at 125 °C, mainly due to the variable tunneling path of charge carriers under program/erase and retention modes (realized by the band-engineered charge-trapping layer), high trap density of LaTiON, and large barrier height at LaTiON/SiO₂ (2.3 eV).     

Cobalt metal nanoparticles embedded in SiO2 dielectric layer for the application of nonvolatile memory

Metal–oxide–semiconductor structures (MOS) with the embedded Co nanoparticles (NPs) were efficiently fabricated by utilizing an external laser irradiation technique for the application of nonvolatile memory. Images of high resolution transmission electron microscopy measurements exhibited that the Co NPs of 5 nm in diameter were clearly embedded in SiO₂ gate oxide. Capacitance–voltage measurements certainly exhibited flat-band voltage shift of 2.2 V from 2 V to −8 V in sweeping range. The retention characteristics of MOS capacitors with the embedded Co NPs were also studied as a function of tunnel oxide thickness to confirm the suitability of nonvolatile memory devices with metal NPs. The experimental results reveal that our unique laser process will give possible promise for experimental efficient formation or insertion of metal NPs inside the gate oxide.     

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO₂ layer and are then fully covered by a HfO₂ layer. The HfO₂ is a high-k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance–voltage and conductance–voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.     

Memory characteristics and tunneling mechanism of Pt nano-crystals embedded in HfAlOx films for nonvolatile flash memory devices

A non-volatile flash memory device based on metal oxide semiconductor (MOS) capacitor structure has been fabricated using platinum nano-crystals(Pt–NCs) as storage units embedded in HfAlO_x high-k tunneling layers. Its memory characteristics and tunneling mechanism are characterized by capacitance–voltage(C–V) and flat-band voltage-time(ΔV_FB-T) measurements. A 6.5 V flat-band voltage (memory window) corresponding to the stored charge density of 2.29 × 10¹³ cm⁻² and about 88% stored electron reserved after apply ±8 V program or erase voltage for 10⁵ s at high frequency of 1 MHz was demonstrated. Investigation of leakage current–voltage(J–V) indicated that defects-enhanced Pool-Frenkel tunneling plays an important role in the tunneling mechanism for the storage charges. Hence, the Pt–NCs and HfAlO_x based MOS structure has a promising application in non-volatile flash memory devices.     

On the optically transparent WDM ATM multicast (3M) switches

We describe an architecture design and implementation of the optically transparent wavelength-division-multiplexed (WDM) asynchronous-transfer-mode (ATM) multicast (3M) switch for all optical high-speed networks. By using the WDM techniques, the wire complexity in both the switch fabric and the concentrator can be reduced from O(N²) to O(N). By using integrated photonic devices and highly parallel processing and pipeline control electronic circuits the switch is handling signals at the cell level (53 bytes) instead of at the bit level and can achieve very high speed and high throughput operation. Several key components, including a cell synchronizer, a photonic VCI over-writting unit, a wavelength converter, an optical concentrator, and a WDM memory, have also been proposed to realize this 3M switch. All of the photonic devices are highly integratable and are very suitable for building future large-scale, low-cost photonic ATM switches. A combination of both the ATM and WDM techniques will provide an ultimate version for optical networking with almost unlimited capacity.     

Selective floating gate non‐volatile paper memory transistor

Here we report the performance of a selective floating gate (V_GS) n‐type non‐volatile memory paper field‐effect transistor. The paper dielectric exhibits a spontaneous polarization of about 1 mCm^–2 and GIZO and IZO amorphous oxides are used respectively as the channel and the gate layers. The drain and source regions are based in continuous conductive thin films that promote the integration of fibres coated with the active semiconductor. The floating memory transistor writes, reads and erases the stored information with retention times above 14500 h, and is selective (for V_GS > 5 ± 0.1 V). That is, to erase stored information a symmetric pulse to the one used to write must be utilized, allowing to store in the same space different information. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Ultrathin gate dielectrics for silicon nanodevices

This paper reviews recent progress in structural and electronic characterizations of ultrathin SiO₂thermally grown on Si(100) surfaces and applications of such nanometer-thick gate oxides to advanced MOSFETs and quantum-dot MOS memory devices. Based on an accurate energy band profile determined for the n ⁺ -poly- Si/SiO₂/Si(100) system, the measured tunnel current through ultrathin gate oxides has been quantitatively explained by theory. From the detailed analysis of MOSFET characteristics, the scaling limit of gate oxide thickness is found to be 0.8 nm. Novel MOSFETs with a silicon quantum-dot floating gate embedded in the gate oxide have indicated the multiple-step electron injection to the dot, being interpreted in terms of Coulombic interaction among charged dots.