Improvement of the high-k/Ge interface thermal stability using an in-situ ozone treatment characterized by conductive atomic force microscopy

In this work, an in-situ ozone treatment is carried out to improve the interface thermal stability of HfO_2/Al_2O_3 gate stack on germanium(Ge) substrate. The micrometer scale level of HfO_2/Al_2O_3 gate stack on Ge is studied using conductive atomic force microscopy(AFM) with a conductive tip. The initial results indicate that comparing with a non insitu ozone treated sample, the interface thermal stability of the sample with an in-situ ozone treatment can be substantially improved after annealing. As a result, void-free surface, low conductive spots, low leakage current density, and relative high breakdown voltage high-κ/Ge are obtained. A detailed analysis is performed to confirm the origins of the changes.All results indicate that in-situ ozone treatment is a promising method to improve the interface properties of Ge-based three-dimensional(3D) devices in future technology nodes.     

Evidence of GeO volatilization and its effect on the characteristics of HfO2 grown on a Ge substrate

HfO2 films are deposited by atomic layer deposition(ALD) using tetrakis ethylmethylamino hafnium(TEMAH) as the hafnium precursor,while O3 or H2O is used as the oxygen precursor.After annealing at 500℃ in nitrogen,the thickness of Ge oxide's interfacial layer decreases,and the presence of GeO is observed at the H2 O-based HfO2 interface due to GeO volatilization,while it is not observed for the O3-based HfO2.The difference is attributed to the residue hydroxyl groups or H2 O molecules in H2 O-based HfO2 hydrolyzing GeO2 and forming GeO,whereas GeO is only formed by the typical reaction mechanism between GeO2 and the Ge substrate for O3-based HfO2 after annealing.The volatilization of GeO deteriorates the characteristics of the high-κ films after annealing,which has effects on the variation of valence band offset and the C-V characteristics of HfO2 /Ge after annealing.The results are confirmed by X-ray photoelectron spectroscopy(XPS) and electrical measurements.     

Wet thermal annealing effect on TaN/HfO2/Ge metal-oxide-semiconductor capacitors with and without a GeO2 passivation layer

Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor(MOS) structures with and without a GeO2 passivation layer are investigated.The physical and the electrical properties are characterized by X-ray photoemission spectroscopy,high-resolution transmission electron microscopy,capacitance-voltage(C-V) and current-voltage characteristics.It is demonstrated that wet thermal annealing at relatively higher temperature such as 550℃ can lead to Ge incorporation in HfO2 and the partial crystallization of HfO2,which should be responsible for the serious degradation of the electrical characteristics of the TaN/HfO2/Ge MOS capacitors.However,wet thermal annealing at 400℃ can decrease the GeO x interlayer thickness at the HfO2/Ge interface,resulting in a significant reduction of the interface states and a smaller effective oxide thickness,along with the introduction of a positive charge in the dielectrics due to the hydrolyzable property of GeO x in the wet ambient.The pre-growth of a thin GeO2 passivation layer can effectively suppress the interface states and improve the C-V characteristics for the as-prepared HfO2 gated Ge MOS capacitors,but it also dissembles the benefits of wet thermal annealing to a certain extent.     

Fabricating GeO2passivation layer by N2O plasma oxidation for Ge NMOSFETs application

In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that1.0-nm GeO2is achieved after 120-s N2O plasma oxidation at 300?C. The GeO2/Ge interface is atomically smooth. The interface state density of Ge surface after N2O plasma passivation is about ～ 3 × 1011cm-2·eV-1. With GeO2passivation,the hysteresis of metal–oxide–semiconductor(MOS) capacitor with Al2O3serving as gate dielectric is reduced to ～ 50 mV,compared with ～ 130 mV of the untreated one. The Fermi-level at GeO2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage.     

Fabricating GeO2 passivation layer by N20 plasma oxidation for Ge NMOSFETs application

In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that 1.0-nm GeO2 is achieved after 120-s N20 plasma oxidation at 300 ℃. The GeO2/Ge interface is atomically smooth. The interface state density of Ge surface after N20 plasma passivation is about - 3 × 1011 cm-2.eV-1. With GeO2 passivation, the hysteresis of metal-oxide-semiconductor （MOS） capacitor with A1203 serving as gate dielectric is reduced to - 50 mV, compared with - 130 mV of the untreated one. The Fermi-level at GeO2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage.     

Effect of interface roughness on the carrier transport in germanium MOSFETs investigated by Monte Carlo method

Interface roughness strongly influences the performance of germanium metal--organic--semiconductor field effect transistors (MOSFETs). In this paper, a 2D full-band Monte Carlo simulator is used to study the impact of interface roughness scattering on electron and hole transport properties in long- and short- channel Ge MOSFETs inversion layers. The carrier effective mobility in the channel of Ge MOSFETs and the in non-equilibrium transport properties are investigated. Results show that both electron and hole mobility are strongly influenced by interface roughness scattering. The output curves for 50~nm channel-length double gate n and p Ge MOSFET show that the drive currents of n- and p-Ge MOSFETs have significant improvement compared with that of Si n- and p-MOSFETs with smooth interface between channel and gate dielectric. The $82\%$ and $96\%$ drive current enhancement are obtained for the n- and p-MOSFETs with the completely smooth interface. However, the enhancement decreases sharply with the increase of interface roughness. With the very rough interface, the drive currents of Ge MOSFETs are even less than that of Si MOSFETs. Moreover, the significant velocity overshoot also has been found in Ge MOSFETs.     

Suppressing the hot carrier injection degradation rate in total ionizing dose effect hardened nMOSFETs

Annular gate nMOSFETs are frequently used in spaceborne integrated circuits due to their intrinsic good capability of resisting total ionizing dose (TID) effect. However, their capability of resisting the hot carrier effect (HCE) has also been proven to be very weak. In this paper, the reason why the annular gate nMOSFETs have good TID but bad HCE resistance is discussed in detail, and an improved design to locate the source contacts only along one side of the annular gate is used to weaken the HCE degradation. The good TID and HCE hardened capability of the design are verified by the experiments for I/O and core nMOSFETs in a 0.18 μm bulk CMOS technology. In addition, the shortcoming of this design is also discussed and the TID and the HCE characteristics of the replacers (the annular source nMOSFETs) are also studied to provide a possible alternative for the designers.     

Effect of interface-roughness scattering on mobility degradation in SiGe p-MOSFETs with a high-k dielectric/SiO2 gate stack＊

A physical model for mobility degradation by interface-roughness scattering and Coulomb scattering is proposed for SiGe p-MOSFET with a high-k dielectric/SiO2 gate stack. Impacts of the two kinds of scatterings on mobility degradation are investigated. Effects of interlayer （SiO2） thickness and permittivities of the high-k dielectric and interlayer on carrier mobility are also discussed. It is shown that a smooth interface between high-k dielectric and interlayer, as well as moderate permittivities of high-k dielectrics, is highly desired to improve carriers mobility while keeping alow equivalent oxide thickness. Simulated results agree reasonably with experimental data.     

Molecular beam epitaxy growth of GaAs on an offcut Ge substrate

Molecular beam epitaxy growth of GaAs on an offcut Ge (100) substrate has been systemically investigated. A high quality GaAs/Ge interface and GaAs film on Ge have been achieved. High temperature annealing before GaAs deposition is found to be indispensable to avoid anti-phase domains. The quality of the GaAs film is found to strongly depend on the GaAs/Ge interface and the beginning of GaAs deposition. The reason why both high temperature annealing and GaAs growth temperature can affect epitaxial GaAs film quality is discussed. High quality In_0.17Ga_0.83As/GaAs strained quantum wells have also been achieved on a Ge substrate. Samples show flat surface morphology and narrow photoluminescence line width compared with the same structure sample grown on a GaAs substrate. These results indicate a large application potential for III--V compound semiconductor optoelectronic devices on Ge substrates.     

High-Mobility P-Type MOSFETs with Integrated Strained-Si_(0.73)Ge_(0.27) Channels and High-κ/Metal Gates

Strained-Si_(0.73)Ge_(0.27) channels are successfully integrated with high-κ/metal gates in p-type metal-oxide- semiconductor field effect transistors(pMOSFETs) using the replacement post-gate process.A silicon cap and oxide inter layers are inserted between Si_(0.73)Ge_(0.27) and high-κ dielectric to improve the interface.The fabricated Si_(0.73) Ge_(0.27) pMOSFETs with gate length of 30 nm exhibit good performance with high drive current(~428μA/μm at V_(DD) = 1 V) and suppressed short-channel effects(DIBL~77mV/V and SS~90mV/decade).It is found that the enhancement of effective hole mobility is up to 200%in long-gate-length Si_(0.73) Ge_(0.27)-channel pMOSFETs compared with the corresponding silicon transistors.The improvement of device performance is reduced due to strain relaxation as the gate length decreases,while 26%increase of the drive current is still obtained for 30-nm-gate-length Si_(0.73)Ge_(0.27) devices.     

Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-κ gate dielectric

By solving Poisson’s equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal–oxide semiconductor field-effect transistor (MOSFET) with a high-κ gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-κ dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.     

The study on two-dimensional analytical model for gate stack fully depleted strained Si on silicon-germanium-on-insulator MOSFETs

Based on the exact resultant solution of two-dimensional Poisson's equation in strained Si and Si_{1 - X}Ge_X layer, a simple and accurate two-dimensional analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator (SGOI) MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects (SCE), the drain-induced barrier-lowering (DIBL) and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.     

Effect of ultrathin GeO_x interfacial layer formed by thermal oxidation on Al_2O_3 capped Ge

We propose a modified thermal oxidation method in which an Al2O3 capping layer is used as an oxygen blocking layer （OBL） to form an ultrathin GeOx interracial layer, and obtain a superior Al2O3/GeOx/Ge gate stack. The GeOx interfacial layer is formed in oxidation reaction by oxygen passing through the Al2O3 OBL, in which theAl2O3 layer could restrain the oxygen diffusion and suppress the GeO desorption during thermal treatment. The thickness of the GeOx interfacial layer would dramatically decrease as the thickness of Al2O3 OBL increases, which is beneficial to achieving an ultrathin GeOx interfacial layer to satisfy the demand for small equivalent oxide thickness （EOT）. In addition, the thickness of the GeOx interfacial layer has little influence on the passivation effect of the Al2O3/Ge interface. Ge （100） p-channel metal- oxide-semiconductor field-effect transistors （pMOSFETs） using the Al2O3/GeOx/Ge gate stacks exhibit excellent electrical characteristics; that is, a drain current on-off （Ionloft） ratio of above 1 104, a subthreshold slope of - 120 mV/dec, and a peak hole mobility of 265 cm2/V.s are achieved.     

Investigation of a 4H-SiC metal-insulation-semiconductor structure with an Al2O3/SiO2 stacked dielectric

Atomic layer deposited(ALD) Al2O3 /dry-oxidized ultrathin SiO2 films as a high-k gate dielectric grown on 8°off-axis 4H-SiC(0001) epitaxial wafers are investigated in this paper.The metal-insulation-semiconductor(MIS) capacitors,respectively with different gate dielectric stacks(Al2O3/SiO2,Al2O3,and SiO2) are fabricated and compared with each other.The I-V measurements show that the Al2O3/SiO2 stack has a high breakdown field(≥12 MV/cm) comparable to SiO2,and a relatively low gate leakage current of1×10-7A/cm2 at an electric field of4 MV/cm comparable to Al2O3.The 1-MHz high frequency C-V measurements exhibit that the Al2O3/SiO2 stack has a smaller positive flat-band voltage shift and hysteresis voltage,indicating a less effective charge and slow-trap density near the interface.     

High-mobility germanium p-MOSFETs by using HCl and(NH_4)_2S surface passivation

To achieve a high-quality high-κ/Ge interfaces for high hole mobility Ge p-MOSFET applications,a simple chemical cleaning and surface passivation scheme is introduced,and Ge p-MOSFETs with effective channel hole mobility up to665 cm2/V·s are demonstrated on a Ge(111) substrate.Moreover,a physical model is proposed to explain the dipole layer formation at the metal–oxide–semiconductor(MOS) interface by analyzing the electrical characteristics of HCl- and(NH4)2S-passivated samples.     

A data readout approach for physics experiments

With increasing physical event rates and the number of electronic channels, traditional readout schemes meet the challenge of improving readout speed caused by the limited bandwidth of the crate backplane. In this paper, a high-speed data readout method based on the Ethernet is presented to make each readout module capable of transmitting data to the DAQ. Features of explicitly parallel data transmitting and distributed network architecture give the readout system the advantage of adapting varying requirements of particle physics experiments. Furthermore, to guarantee the readout performance and flexibility, a standalone embedded CPU system is utilized for network protocol stack processing. To receive the customized data format and protocol from front-end electronics, a field programmable gate array (FPGA) is used for logic reconfiguration. To optimize the interface and to improve the data throughput between CPU and FPGA, a sophisticated method based on SRAM is presented in this paper. For the purpose of evaluating this high-speed readout method, a simplified readout module is designed and implemented. Test results show that this module can support up to 70 Mbps data throughput from the readout module to DAQ.     

Closed-form breakdown voltage/specific on-resistance model using charge superposition technique for vertical power double-diffused metal–oxide–semiconductor device with high-κ insulator

An improved vertical power double-diffused metal–oxide–semiconductor(DMOS) device with a p-region(P1) and high-κ insulator vertical double-diffusion metal–oxide–semiconductor(HKP-VDMOS) is proposed to achieve a better performance on breakdown voltage(BV)/specific on-resistance(Ron,sp) than conventional VDMOS with a high-κ insulator(CHK-VDMOS).The main mechanism is that with the introduction of the P-region,an extra electric field peak is generated in the drift region of HKP-VDMOS to enhance the breakdown voltage.Due to the assisted depletion effect of this p-region,the specific on-resistance of the device could be reduced because of the high doping density of the N-type drift region.Meanwhile,based on the superposition of the depleted charges,a closed-form model for electric field/breakdown voltage is generally derived,which is in good agreement with the simulation result within 10% of error.An HKP-VDMOS device with a breakdown voltage of 600 V,a reduced specific on-resistance of 11.5 m?·cm~2 and a figure of merit(FOM)(BV~2/Ron,sp)of 31.2 MW·cm~(-2) shows a substantial improvement compared with the CHK-VDMOS device.     

Electromagnetic scattering from two-layered rough interfaces with a PEC object: vertical polarization

Electromagnetic(EM) scattering from a stack of two rough interfaces separating a homogeneous medium with a perfectly electric conducting(PEC) object has been calculated through the method of moments for vertical polarization.Theoretical formulations of EM scattering from multi-layered rough interfaces with a PEC object have been derived in detail and the total fields and their normal derivatives on the rough interfaces are solved.The two-layered model is a special case.In this work,a Gaussian rough surface was applied to simulate the rough interface.A cylinder was located above,between or below the two-layered rough interfaces.Through numerical simulations,the validity of this work is demonstrated by comparing it with existing scattering models,which are special cases that include a PEC object located above/below a single-layered rough interface and two-layered rough interfaces without an object.Subsequently,the influences of characteristic parameters,such as the relative permittivity of the medium,as well as the average height between the two rough surfaces,on the bistatic scattering coefficient are discussed.     

Development of pressure-modulated EXAFS method

Many modulation techniques have been widely applied to improve the quality of conventional spectra. Here a pressure-modulated EXAFS method is proposed to detect the small changes of local structure induced by the modulation of high pressure. In the experiment a dynamic diamond anvil cell was used to put a periodic load on the sample and lock-in amplifier to measure the modulated EXAFS signals. We have applied this technique to ZnSe and revealed a sensitivity to atomic displacement of 0.1 pm that is about ten times better than that of traditional EXAFS.     

Detailed study of NBTI characterization in 40-nm CMOS process using comprehensive models

The impact of negative bias temperature instability(NBTI) can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps(?V_(HT)) in gate insulator, generated traps(?V_(OT)) in bulk insulator, and interface trap generation(?V_(IT)). In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal–oxide semiconductor(CMOS) process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction–diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed.