Collector optimization for tradeoff between breakdown voltage and cut-off frequency in SiGe HBT

As is well known, there exists a tradeoff between the breakdown voltage BVCEOand the cut-off frequency fTfor a standard heterojunction bipolar transistor(HBT). In this paper, this tradeoff is alleviated by collector doping engineering in the SiGe HBT by utilizing a novel composite of P+and N-doping layers inside the collector–base(CB) space-charge region(SCR). Compared with the single N-type collector, the introduction of the thin P+layers provides a reverse electric field weakening the electric field near the CB metallurgical junction without changing the field direction, and the thin Nlayer further effectively lowers the electric field near the CB metallurgical junction. As a result, the electron temperature near the CB metallurgical junction is lowered, consequently suppressing the impact ionization, thus BVCEOis improved with a slight degradation in fT. The results show that the product of fT×BVCEOis improved from 309.51 GHz·V to326.35 GHz·V.     

Thermal resistance matrix representation of thermal effects and thermal design in multi-finger power heterojunction bipolar transistors

The thermal resistance matrix including self-heating thermal resistance and thermal coupling resistance is presented to describe the thermal effects of multi-finger power heterojunction bipolar transistors. The dependence of thermal resistance matrix on finger spacing is also investigated. It is shown that both self-heating thermal resistance and thermal coupling resistance are lowered by increasing the finger spacing, in which the downward dissipated heat path is widened and the heat flow from adjacent fingers is effectively suppressed. The decrease of self-heating thermal resistance and thermal coupling resistance is helpful for improving the thermal stability of power devices. Furthermore, with the aid of the thermal resistance matrix, a 10-finger power heterojunction bipolar transistor (HBT) with non-uniform finger spacing is designed for high thermal stability. The optimized structure can effectively lower the peak temperature while maintaining a uniformity of the temperature profile at various biases and thus the device effectively may operate at a higher power level.     

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.     

A Novel Fully Depleted Air AlN Silicon-on-Insulator Metal--Oxide--Semiconductor Field Effect Transistor

A novel fully depleted air A1N silicon-on-insulator （SOD metai-oxide-semiconductor field effect transistor （MOS- FET） is presented, which can eliminate the self-heating effect and solve the problem that the off-state current of SOI MOSFETs increases and the threshold voltage characteristics become worse when employing a high thermal conductivity material as a buried layer. The simulation results reveal that the lattice temperature in normal SOI devices is 75K higher than the atmosphere temperature, while the lattice temperature is just 4 K higher than the atmosphere temperature resulting in less severe self-heating effect in air A1N SOI MOSFETs and A1N SOI MOSFETs. The on-state current of air A1N SOI MOSFETs is similar to the A1N SOI structure, and improves 12.3% more than that of normal SOI MOSFETs. The off-state current of A1N SOI is 6. 7 times of normal SOI MOSFETs, while the counterpart of air A1N SOI MOSFETs is lower than that of SOI MOSFETs by two orders of magnitude. The threshold voltage change of air A1N SOl MOSFETs with different drain voltage is much less than that of A1N SOI devices, when the drain voltage is Mased at 0.8 V, this difference is 28mV, so the threshold voltage change induced by employing high thermal conductivity material is cured.     

A Base-Emitter Self-Aligned Multi-Finger Sil-xGex/Si Power Heterojunction Bipolar Transistor

With a crystal orientation dependent on the etch rate of Si in KOH-based solution, a base-emitter self-Migned large-area multi-finger configuration power SiGe heterojunction bipolar transistor （HBT） device （with an emitter area of about 880μm^2） is fabricated with 2μm double-mesa technology. The maximum dc current gain is 226.1. The collector-emitter junction breakdown voltage BVcEo is 10 V and the collector-base junction breakdown voltage BVcBo is 16 V with collector doping concentration of 1 × 10^17 cm^-3 and thickness of 400nm. The device exhibited a maximum oscillation frequency fmax of 35.5 GHz and a cut-off frequency fT of 24.9 GHz at a dc bias point of Ic = 70 mA and the voltage between collector and emitter is VCE = 3 V. Load pull measurements in class-A operation of the SiGe HBT are performed at 1.9 GHz with input power ranging from OdBm to 21 dBm. A maximum output power of 29.9dBm （about 977mW） is obtained at an input power of 18.SdBm with a gain of 11.47dB. Compared to a non-self-aligned SiGe HBT with the same heterostructure and process, fmax and fT are improved by about 83.9% and 38.3%, respectively.     

Substrate bias effects on collector resistance in SiGe heterojunction bipolar transistors on thin film silicon-on-insulator

An analytical expression for the collector resistance of a novel vertical SiGe heterojunction bipolar transistor(HBT) on thin film silicon-on-insulator(SOI) is obtained with the substrate bias effects being considered.The resistance is found to decrease slowly and then quickly and to have kinks with the increase of the substrate-collector bias,which is quite different from that of a conventional bulk HBT.The model is consistent with the simulation result and the reported data and is useful to the frequency characteristic design of 0.13 μm millimeter-wave SiGe SOI BiCMOS devices.     

A New silicon—on—Insulator Structure of Metal—Oxide—Semiconductor Field Effect Transistor to Reduce Self—Heating Effect

A new silicon-on-insulator(SOI)device stucture is proposed.This new design provides a new path to reduce the temperature of the channel of SOI metal-oxide-semiconductor field effect transistor(MOSFET).The device has been verified in two-dimensional device simulation,The new structure reduces the self-heating effect of SOI MOSFET and decreases the negative differential transconductance.     

Novel fast-switching LIGBT with P-buried layer and partial SOI

A novel silicon-on-insulator lateral insulated gate bipolar transistor(SOI LIGBT)is proposed in this paper.The proposed device has a P-type buried layer and a partial-SOI layer,which is called the BPSOI-LIGBT.Due to the electric field modulation effect generated by the P-type buried layer and the partial-SOI layer,the proposed structure generates two new peaks in the surface electric field distribution,which can achieve a smaller device size with a higher breakdown voltage.The smaller size of the device is beneficial to the fast switching.The simulation shows that under the same size,the breakdown voltage of the BPSOI LIGBT is 26%higher than that of the conventional partial-SOI LIGBT(PSOI LIGBT),and 84%higher than the traditional SOI LIGBT.When the forward voltage drop is 2.05 V,the turn-off time of the BPSOI LIGBT is 71%shorter than that of the traditional SOI LIGBT.Therefore,the proposed BPSOI LIGBT has a better forward voltage drop and turn-off time trade-off than the traditional SOI LIGBT.In addition,the BPSOI LIGBT effectively relieves the self-heating effect of the traditional SOI LIGBT.     

Improving breakdown voltage performance of SOI power device with folded drift region

A novel silicon-on-insulator(SOI) high breakdown voltage(BV) power device with interlaced dielectric trenches(IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer,which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges(holes) at the corner of IDT.The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V.     

Thermal resistance matrix representation of thermal effects and thermal design of microwave power HBTs with two-dimensional array layout

Based on the thermal network of the two-dimensional heterojunction bipolar transistors(HBTs) array, the thermal resistance matrix is presented, including the self-heating thermal resistance and thermal coupling resistance to describe the self-heating and thermal coupling effects, respectively.For HBT cells along the emitter length direction, the thermal coupling resistance is far smaller than the self-heating thermal resistance, and the peak junction temperature is mainly determined by the self-heating thermal resistance.However, the thermal coupling resistance is in the same order with the self-heating thermal resistance for HBT cells along the emitter width direction.Furthermore, the dependence of the thermal resistance matrix on cell spacing along the emitter length direction and cell spacing along the emitter width direction is also investigated, respectively.It is shown that the moderate increase of cell spacings along the emitter length direction and the emitter width direction could effectively lower the self-heating thermal resistance and thermal coupling resistance,and hence the peak junction temperature is decreased, which sheds light on adopting a two-dimensional non-uniform cell spacing layout to improve the uneven temperature distribution.By taking a 2 × 6 HBTs array for example, a twodimensional non-uniform cell spacing layout is designed, which can effectively lower the peak junction temperature and reduce the non-uniformity of the dissipated power.For the HBTs array with optimized layout, the high power-handling capability and thermal dissipation capability are kept when the bias voltage increases.     

SOI部分耗尽SiGe HBT集电结空间电荷区模型

SOI上的薄膜异质SiGe晶体管通过采用"折叠"集电极,已成功实现SOI上CMOS与HBT的兼容.本文结合SOI薄膜上的纵向SiGe HBT结构模型,提出了包含纵向、横向欧姆电阻和耗尽电容的"部分耗尽 (partially depleted) 晶体管"集电区简化电路模型.基于器件物理及实际考虑,系统建立了外延集电层电场、电势、耗尽宽度模型,并根据该模型对不同器件结构参数进行分析.结果表明,空间电荷区表现为本征集电结耗尽与MOS电容耗尽,空间电荷区宽度随集电结掺杂浓度减小而增大,随集电结反偏电压提高而增大, 关键词： SOI SiGe HBT 集电区 空间电荷区模型     

新型宽温区高热稳定性微波功率SiGe 异质结双极晶体管

宽温区大电流下的热不稳定性严重制约着功率SiGe 异质结双极晶体管 (HBT) 在射频和微波电路中的应用.为改善器件的热不稳定性, 本文利用SILVACO TCAD建立的多指功率SiGe HBT模型, 分析了器件纵向结构中基区Ge组分分布对微波功率SiGe HBT电学特性和热学特性的影响. 研究表明, 对于基区Ge组分为阶梯分布的HBT, 由于Ge组分缓变引入了少子加速电场, 使它与均匀基区Ge组分HBT相比, 具有更高的特征频率f_T, 且电流增益β和f_T随温度变化变弱, 这有利于防止器件在宽温区工作时电学特性的漂移.同时, 器件整体温度有所降低, 但器件各指温度分布均匀性较差.考虑多指HBT各发射极指散热能力存在差异, 在器件纵向结构设计为基区Ge组分阶梯分布的同时, 对其横向版图进行发射极指间距渐变结构设计, 用于改善器件各指温度分布的均匀性, 进而提高HBT的热稳定性.结果表明, 与基区Ge组分为均匀分布的等发射极指间距结构HBT相比, 新器件各指温度分布均匀性明显改善, f_T保持了较高的值, 且β和f_T 随温度变化不敏感, 热不稳定性得到显著改善, 显示了新器件在宽温区大电流下工作的优越性. 关键词： SiGe 异质结双极晶体管 Ge组分分布 发射极指间距渐变技术 热稳定性     

Novel high-K with low specific on-resistance high voltage lateral double-diffused MOSFET

A novel voltage-withstand substrate with high-K (HK, k>3.9, k is the relative permittivity) dielectric and low specific on-resistance (R_on,sp) bulk-silicon, high-voltage LDMOS (HKLR LDMOS) is proposed in this paper. The high-K dielectric and highly doped interface N⁺-layer are made in bulk silicon to reduce the surface field drift region. The high-K dielectric can fully assist in depleting the drift region to increase the drift doping concentration (N_d) and reshape the electric field distribution. The highly doped N⁺-layer under the high-K dielectric acts as a low resistance path to reduce the R_on,sp. The new device with the high breakdown voltage (BV), the low R_on,sp, and the excellent figure of merit (FOM=BV²/R_on,sp) is obtained. The BV of HKLR LDMOS is 534 V, R_on,sp is 70.6 mΩ·cm², and FOM is 4.039 MW·cm^-2.     

Early effect modeling of silicon-on-insulator SiGe heterojunction bipolar transistors

Silicon germanium(SiGe) heterojunction bipolar transistor(HBT) on thin silicon-on-insulator(SOI) has recently been demonstrated and integrated into the latest SOI BiCMOS technology.The Early effect of the SOI SiGe HBT is analysed considering vertical and horizontal collector depletion,which is different from that of a bulk counterpart.A new compact formula of the Early voltage is presented and validated by an ISE TCAD simulation.The Early voltage shows a kink with the increase of the reverse base-collector bias.Large differences are observed between SOI devices and their bulk counterparts.The presented Early effect model can be employed for a fast evaluation of the Early voltage and is useful to the design,the simulation and the fabrication of high performance SOI SiGe devices and circuits.     

Reduced self-heating by strained silicon substrate engineering

Substrate engineering innovations such as SOI and the use of Si/SiGe virtual substrates become necessary in order to maintain performance leverage of integrated circuits with continued scaling. The relevance of thermal effects in device design increases since the thermal conductivity of these new materials is poor. The electrical performance of devices fabricated on thin virtual substrates grown by two different techniques is presented. It is found that self-heating is reduced and that thermal resistance measurements agree with modelling predictions. The reduction in performance enhancement seen in many strained Si MOSFETs is found here to be largely due to self-heating effects, rather than parasitics or the loss of strain.     

三维数值仿真研究锗硅异质结双极晶体管总剂量效应

为探索锗硅异质结双极晶体管(SiGe HBT)总剂量效应的损伤机理,采用半导体器件三维模拟工具(TCAD),建立电离辐照总剂量效应损伤模型,分析比较电离辐射在SiGe HBT不同氧化层结构的不同位置引入陷阱电荷缺陷后,器件正向Gummel特性和反向Gummel特性的退化特征,获得SiGe HBT总剂量效应损伤规律,并与⁶⁰Coγ辐照实验进行对比.结果表明:总剂量辐照在SiGe HBT器件中引入的氧化物陷阱正电荷主要在pn结附近的Si/SiO₂界面处产生影响,引起pn结耗尽区的变化,带来载流子复合增加,最终导致基极电流增大、增益下降;其中EB Spacer氧化层中产生的陷阱电荷主要影响正向Gummel特性,而LOCOS隔离氧化层中的陷阱电荷则是造成反向Gummel特性退化的主要因素.通过数值模拟分析获得的SiGe HBT总剂量效应损伤规律与不同偏置下⁶⁰Coγ辐照实验的结论符合得较好.     

薄膜SOI上SiGe HBT集电结耗尽电荷和电容改进模型

文章研究了SOI衬底上SiGe npn异质结晶体管集电结耗尽电荷和电容.根据器件实际工作情况,基于课题组前面的工作,对耗尽电荷和电容模型进行扩展和优化.研究结果表明,耗尽电荷模型具有更好的光滑性;耗尽电容模型为纵向耗尽与横向耗尽电容的串联,考虑了不同电流流动面积,与常规器件相比,SOI器件全耗尽工作模式下表现出更小的集电结耗尽电容,因此更大的正向Early电压;在纵向工作模式到横向工作模式转变的电压偏置点,耗尽电荷和电容的变化趋势发生改变.SOI薄膜上纵向SiGe HBT集电结耗尽电荷和电容模型的建立和扩展为毫米波SOI BiCMOS工艺中双极器件核心参数如Early电压、特征频率等的设计提供了有价值的参考. 关键词： 耗尽电容 SiGe HBT SOI     

含有本征SiGe层的SiGe异质结双极晶体管集电结耗尽层宽度模型

本文分别建立了含有本征SiGe层的SiGe HBT(异质结双极晶体管)集电结耗尽层各区域的电势、电场分布模型,并在此基础上,建立了集电结耗尽层宽度和延迟时间模型,对该模型进行了模拟仿真,定量地分析了SiGe HBT物理、电学参数对集电结耗尽层宽度和延迟时间的影响,随着基区掺杂浓度和集电结反偏电压的提高,集电结耗尽层延迟时间也随之增大,而随着集电区掺杂浓度的提高和基区Ge组分增加,集电结耗尽层延迟时间随之减小. 关键词： SiGe HBT 集电结耗尽层 延迟时间     

A device model for thin silicon-on-insulator SiGe heterojunction bipolar transistors with saturation effects

In this paper, we describe the saturation effect of a silicon germanium (SiGe) heterojunction bipolar transistor (HBT) fabricated on a thin silicon-on-insulator (SOI) with a step-by-step derivation of the model formulation. The collector injection width, the internal base—collector bias, and the hole density at the base—collector junction interface are analysed by considering the unique features of the internal and the external parts of the collector, as they are different from those of a bulk counterpart.