Temperature- and voltage-dependent trap generation model in high-k metal gate MOS device with percolation simulation

High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to the breakdown characteristic.In this work,a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up,and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation.It is found that all degradation factors,such as trap generation rate time exponent m,Weibull slope β and percolation factor s,each could be expressed as a function of trap density time exponent α.Based on the percolation relation and power law lifetime projection,a temperature related trap generation model is proposed.The validity of this model is confirmed by comparing with experiment results.For other device and material conditions,the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.     

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

A multi-deposition multi-annealing technique(MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device's performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown(TDDB) characteristics of positive channel metal oxide semiconductor(PMOS) under different MDMA process conditions, including the deposition/annealing(DA) cycles, the DA time, and the total annealing time. The results show that the increases of the number of DA cycles(from 1 to 2) and DA time(from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail(TTF) at 63.2% increases by about several times. However, too many DA cycles(such as 4 cycles) make the equivalent oxide thickness(EOT) increase by about 1 ?A and the TTF of PMOS worsen. Moreover, different DA times and numbers of DA cycles induce different breakdown mechanisms.