Charge trapping behavior and its origin in Al_2O_3/SiC MIS system

Charge trapping behavior and its origin in Al2O3/SiC MOS structure are investigated by analyzing the capacitance–voltage(C–V) hysteresis and the chemical composition of the interface. The C–V hysteresis is measured as a function of oxide thickness series for an Al2O3/SiC MIS capacitor. The distribution of the trapped charges, extracted from the C–V curves, is found to mainly follow a sheet charge model rather than a bulk charge model. Therefore, the electron injection phenomenon is evaluated by using linear fitting. It is found that most of the trapped charges are not distributed exactly at the interface but are located in the bulk of the Al2O3 layers, especially close to the border. Furthermore, there is no detectable oxide interface layer in the x-ray photoelectron spectroscope(XPS) and transmission electron microscope(TEM)measurements. In addition, Rutherford back scattering(RBS) analysis shows that the width of the Al2O3/SiC interface is less than 1 nm. It could be concluded that the charge trapping sites in Al2O3/SiC structure might mainly originate from the border traps in Al2O3 film rather than the interface traps in the interfacial transition layer.     

Comparative study of electrical characteristics for n-type 4H–SiC planar and trench MOS capacitors annealed in ambient NO

The interface properties and electrical characteristics of the n-type 4H-SiC planar and trench metal–oxide–semiconductor(MOS) capacitors are investigated by measuring the capacitance voltage and current voltage. The flat-band voltage and interface state density are evaluated by the quasi-static method. It is not effective on further improving the interface properties annealing at 1250℃ in NO ambient for above 1 h due to the increasing interface shallow and fast states.These shallow states reduce the effective positive fixed charge density in the oxide. For the vertical MOS capacitors on the(1120) and(1100) faces, the interface state density can be reduced by approximately one order of magnitude, in comparison to the result of the planar MOS capacitors on the(0001) face under the same NO annealing condition. In addition, it is found that Fowler–Nordheim tunneling current occurs at an oxide electric field of 7 MV/cm for the planar MOS device.However, Poole–Frenkel conduction current occurs at a lower electric field of 4 MV/cm for the trench MOS capacitor. This is due to the local field crowded at the trench corner severely causing the electrons to be early captured at or emitted from the SiO_2/Si C interface. These results provide a reference for an in-depth understanding of the mobility-limiting factors and long term reliability of the trench and planar SiO_2/Si C interfaces.     

Compound buried layer SOI high voltage device with a step buried oxide

A silicon-on-insulator (SOI) high performance lateral double-diffusion metal oxide semiconductor (LDMOS) on a compound buried layer (CBL) with a step buried oxide (SBO CBL SOI) is proposed.The step buried oxide locates holes in the top interface of the upper buried oxide (UBO) layer.Furthermore,holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide (LBO) layer.Consequently,the electric fields in both the thin LBO and the thick UBO are enhanced by these holes,leading to an improved breakdown voltage.The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer.Moreover,SBO CBL SOI can also reduce the self-heating effect.     

Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET

In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal–oxide semiconductor field-effect transistors(VDMOSFETs) subjected to negative bias temperature(NBT)stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps(permanent component).Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.     

Different charging behaviors between electrons and holes in Si nanocrystals embedded in SiN_x matrix by the influence of near-interface oxide traps

Si-rich silicon nitride films are prepared by plasma-enhanced chemical vapor deposition method,followed by thermal annealing to form the Si nanocrystals(Si-NCs)embedded in Si Nx floating gate MOS structures.The capacitance–voltage(C–V),current–voltage(I–V),and admittance–voltage(G–V)measurements are used to investigate the charging characteristics.It is found that the maximum flat band voltage shift(△VFB)due to full charged holes(～6.2 V)is much larger than that due to full charged electrons(～1 V).The charging displacement current peaks of electrons and holes can be also observed by the I–V measurements,respectively.From the G–V measurements we find that the hole injection is influenced by the oxide hole traps which are located near the Si O2/Si-substrate interface.Combining the results of C–V and G–V measurements,we find that the hole charging of the Si-NCs occurs via a two-step tunneling mechanism.The evolution of G–V peak originated from oxide traps exhibits the process of hole injection into these defects and transferring to the Si-NCs.     

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

An analytical model for a novel triple reduced surface field(RESURF) silicon-on-insulator(SOI) lateral doublediffused metal–oxide–semiconductor(LDMOS) field effect transistor with n-type top(N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional(2D) Poisson's equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage(BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer(Q_(ntop)) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.     

Investigation on latch-up susceptibility induced by high-power microwave in complementary metal–oxide–semiconductor inverter

The latch-up effect induced by high-power microwave(HPM) in complementary metal–oxide–semiconductor(CMOS) inverter is investigated in simulation and theory in this paper. The physical mechanisms of excess carrier injection and HPM-induced latch-up are proposed. Analysis on upset characteristic under pulsed wave reveals increasing susceptibility under shorter-width pulsed wave which satisfies experimental data, and the dependence of upset threshold on pulse repetitive frequency(PRF) is believed to be due to the accumulation of excess carriers. Moreover, the trend that HPMinduced latch-up is more likely to happen in shallow-well device is proposed.Finally, the process of self-recovery which is ever-reported in experiment with its correlation with supply voltage and power level is elaborated, and the conclusions are consistent with reported experimental results.     

Closed-form breakdown voltage/specific on-resistance model using charge superposition technique for vertical power double-diffused metal–oxide–semiconductor device with high-κ insulator

An improved vertical power double-diffused metal–oxide–semiconductor(DMOS) device with a p-region(P1) and high-κ insulator vertical double-diffusion metal–oxide–semiconductor(HKP-VDMOS) is proposed to achieve a better performance on breakdown voltage(BV)/specific on-resistance(Ron,sp) than conventional VDMOS with a high-κ insulator(CHK-VDMOS).The main mechanism is that with the introduction of the P-region,an extra electric field peak is generated in the drift region of HKP-VDMOS to enhance the breakdown voltage.Due to the assisted depletion effect of this p-region,the specific on-resistance of the device could be reduced because of the high doping density of the N-type drift region.Meanwhile,based on the superposition of the depleted charges,a closed-form model for electric field/breakdown voltage is generally derived,which is in good agreement with the simulation result within 10% of error.An HKP-VDMOS device with a breakdown voltage of 600 V,a reduced specific on-resistance of 11.5 m?·cm~2 and a figure of merit(FOM)(BV~2/Ron,sp)of 31.2 MW·cm~(-2) shows a substantial improvement compared with the CHK-VDMOS device.     

Near-interface oxide traps in 4H–SiC MOS structures fabricated with and without annealing in NO

Near-interface oxide traps(NIOTs)in 4H–Si C metal–oxide–semiconductor(MOS)structures fabricated with and without annealing in NO are systematically investigated in this paper.The properties of NIOTs in Si C MOS structures prepared with and without annealing in NO are studied and compared in detail.Two main categories of the NIOTs,the"slow"and"fast"NIOTs,are revealed and extracted.The densities of the"fast"NIOTs are determined to be 0.76×10~(11)cm~(-2)and0.47×10~(11)cm~(-2)for the N_2 post oxidation annealing(POA)sample and NO POA sample,respectively.The densities of"slow"NIOTs are 0.79×10~(11)cm~(-2)and 9.44×10~(11)cm~(-2)for the NO POA sample and N_2POA sample,respectively.It is found that the NO POA process only can significantly reduce"slow"NIOTs.However,it has a little effect on"fast"NIOTs.The negative and positive constant voltage stresses(CVS)reveal that electrons captured by those"slow"NIOTs and bulk oxide traps(BOTs)are hardly emitted by the constant voltage stress.     

Modeling of high permittivity insulator structure with interface charge by charge compensation

An analytical model of the power metal–oxide–semiconductor field-effect transistor(MOSFET)with high permittivity insulator structure(HKMOS)with interface charge is established based on superposition and developed for optimization by charge compensation.In light of charge compensation,the disturbance aroused by interface charge is efficiently compromised by introducing extra charge for maximizing breakdown voltage(BV)and minimizing specific ON-resistance(R_on,sp).From this optimization method,it is very efficient to obtain the design parameters to overcome the difficulty in implementing the R_on,sp–BV trade-off for quick design.The analytical results prove that in the HKMOS with positive or negative interface charge at a given length of drift region,the extraction of the parameters is qualitatively and quantitatively optimized for trading off BV and Ron,sp with JFET effect taken into account.     

Comparative study of electrical properties of Au/n-Si (MS) and Au/Si3N4/n-Si (MIS) Schottky diodes

In this paper, the electrical parameters of Au/n-Si (MS) and Au/Si₃N₄/n-Si (MIS) Schottky diodes are obtained from the forward bias current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. Experimental results show that the rectifying ratios of MS and MIS diode at ± 5 V are found to be 1.25×10³ and 1.27×10⁴, respectively. The main electrical parameters of MS and MIS diode, such as the zero-bias barrier height (Φ _Bo) and ideality factor (n) are calculated to be 0.51 eV (I-V), 0.53 eV (C-V), and 4.43, and 0.65 eV (I-V), 0.70 eV (C-V), and 3.44, respectively. Also, the energy density distribution profile of the interface states (N_ss) is obtained from the forward bias I-V. In addition, the values of series resistance (R_s) for the two diodes are calculated from Cheung's method and Ohm's law.     

Comparison between post-irradiation annealing and post-high electric field stress annealing of n-channel power VDMOSFETs

The behavior of the defects created in the gate oxide and at the Si/SiO₂ interface of n-channel power vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOSFETs) by irradiation and positive high electric field stress have been investigated. Interface traps exhibit the same behavior after both types of stress, while there are significant differences in post-stress responses of the charge trapped in the oxide, consisting of fixed and switching component.     

Layer dependence of the superconducting transition temperature of HgBa2Can−1CunO2n+2+δ

High-pressure methods have been used to synthesize multiphase compositions in the Hg---12{n−1}n homologous series. The phase assemblages were examined by optical, electron diffraction and X-ray diffraction techniques, and their stoichiometries verified by electron microprobe. Transport and magnetic susceptibility measurements were combined with the results of the phase analysis to establish superconducting transition temperatures for both as-prepared and O₂- or Ar-annealed materials. It was found that the transition temperature peaks at T_c = 134 K for N = 3 and then decreases abruptly for n>4, reaching T_c<90 K for n7.     

Correlated use of characterization techniques to optimize the Mg implantation annealing for self-aligned HBT''s

The annealing process of Mg-implanted GaAs/GaAlAs HBT's has been optimized using different analysis techniques. The Mg activation was deduced from a comparison between the atomic profile determined by SIMS and the electrical profile determined by electrochemical C-V profiling. Under the optimum annealing conditions, a record activation value of 87% was reached. Cathodoluminescence analysis has also been used to assess the quality of the implanted materials.     

Charge trapping and breakdown in thin SiO2 polysilicon-gate MOS capacitors

Charge trapping during high-field (Fowler-Nordheim) injection in thin SiO₂ films is investigated. Constant and pulsed current injection as well as C-V measurements are used to determine the evolution of trapped charge and interface state densities. The relation between these charges, which can be influenced by temperature and γ radiation, and dielectric breakdown is studied. We establish the dominant role of negative trapped charge.     

Atomic-layer-deposited Al_2O_3 and HfO_2 on InAlAs: A comparative study of interfacial and electrical characteristics

Al_2O_3 and HfO_2 thin films are separately deposited on n-type InAlAs epitaxial layers by using atomic layer deposition(ALD).The interfacial properties are revealed by angle-resolved x-ray photoelectron spectroscopy(AR-XPS).It is demonstrated that the Al_2O_3 layer can reduce interfacial oxidation and trap charge formation.The gate leakage current densities are 1.37×10~6 A/cm~2 and 3.22×10~6 A/cm~2 at+1V for the Al_2O_3/InAlAs and HfO_2/InAlAs MOS capacitors respectively.Compared with the HfO_2/InAlAs metal-oxide-semiconductor(MOS) capacitor,the Al_2O_3/InAlAS MOS capacitor exhibits good electrical properties in reducing gate leakage current,narrowing down the hysteresis loop,shrinking stretch-out of the C-V characteristics,and significantly reducing the oxide trapped charge(Q_(ot)) value and the interface state density(D_(it)).     

The influence of the DX center on the capacitance of schottky barriers in n-type AlGaAs

The significance of both the density N, and the apparent built-in voltage V_a, as usually obtained from C-V measurements on Schottky barriers containing DX centers, is clarified. It is also shown that, owing to the non-equilibrium occupancy of the DX center, at low temperature the electron density in the flat-band region depends on the cooling rate of the sample.     

MOSFET 辐照诱生界面陷阱形成过程的1/f噪声研究

基于界面陷阱形成的氢离子运动两步模型和反应过程的热力学平衡假设，推导了金属-氧化物-半导体-场效应晶体管(MOSFET)经历电离辐照后氧化层空穴俘获与界面陷阱形成间关系的表达式.利用初始1/f噪声功率谱幅值与氧化层空穴俘获之间的联系，建立了辐照前的1/f噪声幅值与辐照诱生界面陷阱数量之间的半经验公式，并通过实验予以验证.研究结果表明，由于辐照诱生的氧化层内陷阱通过与分子氢作用而直接参与到界面陷阱的建立过程中，从而使界面陷阱生成数量正比于这种陷阱增加的数量，因此辐照前的1/f噪声功率谱幅值正比于辐照诱生的界面陷阱数量.研究结果为1/f噪声用作MOSFET辐照损伤机理研究的新工具，对其抗辐照性能进行无损评估提供了理论依据与数学模型. 关键词： 辐照效应 界面陷阱 1/f噪声 氧化层空穴俘获     

氢化非晶硅薄膜晶体管的低频噪声特性

针对氢化非晶硅薄膜晶体管(hydrogenated amorphous silicon thin film transistor,a-Si:H TFT)的低频噪声特性展开实验研究.由测量结果可知,a-Si:H TFT的低频噪声特性遵循1/f~γ(f为频率,γ≈0.92)的变化规律,主要受迁移率随机涨落效应的影响.基于与迁移率涨落相关的载流子数随机涨落模型(?N-?μ模型),在考虑源漏接触电阻、局域态俘获及释放载流子效应等情况时,对器件低频噪声特性随沟道电流的变化进行分析与拟合.基于a-Si:H TFT的亚阈区电流-电压特性提取器件表面能带弯曲量与栅源电压之间的关系,通过沟道电流噪声功率谱密度提取a-Si:H TFT有源层内局域态密度及其分布.实验结果表明:局域态在禁带内随能量呈e指数变化,两种缺陷态在导带底密度分别约为6.31×10~(18)和1.26×10~(18)cm~(-3)·eV~(-1),特征温度分别约为192和290 K,这符合非晶硅层内带尾态密度及其分布特征.最后提取器件的平均Hooge因子,为评价非晶硅材料及其稳定性提供参考.